KT3170 SAMSUNG | Alldatasheet

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KT3170 LOW POWER DTMF RECEIVER INTRODUCTION The KT3170 is a complete Dual Tone Multiple Frequency (DTMF) receiver that is fabricated by low power CMOS and the Switched-Capacitor Filter technology. This LSI consists of band split filters, which seperates counting section which verifies the frequency and duration of the received tones before passing the cor- responding code to the output bus. It decodes all 16 DTMF tone pairs into a 4bits digital code. The externally required components are minimized by on chip provision of a differential input AMP, clock oscillator and latched three state interface. The on chip clock generator requires only a low cost TV cystal as an external component.

FEATURES

  • Detects all 16 standard tones.
  • Low power consumption : 15mW (Typ)
  • Single power supply : 5V
  • Uses inexpensive 3.58MHz crystal
  • Three state outputs for microprocessor interface
  • Good quality and performance for using in exchange system
  • Power down mode/input inhibit APPLICATIONS PIN CONFIGURATION
  • PABX
  • Central Office
  • Paging Systems
  • Remote Control
  • Credit Card Systems
  • Key Phone System
  • Answering Phone
  • Home Automation System
  • Mobile Radio
  • Remote Data Entry Fig. 1 Device Package Operating KT3170N 18-DIP-300A - 25°C ~ + 75°C 9 10 KT3170 IN+ IN- GS VREF IIN PDN OSC1 OSC2 GND VDD SI/GTO ESO DSO OE 18-DIP-300A

ORDERING INFORMATION

KT3170 LOW POWER DTMF RECEIVER PIN DESCRIPTION Pin No Symbol Description 1 IN + Non inverting input of the op amp. 2 IN - Inverting input of the op amp. 3 GS Gain Select. The output used for gain adjustment of analog input signal with a feedback resistor.

4 VREF

Reference Voltage output (VDD/2, Typ) can be used to bias the op amp input of VDD/2.

5 IIN

Input inhibit. High input states inhibits the detection of tones. This pin is pulled down internally.

6 PDN

Control input for the stand-by power down mode. Power down occurs when the signal on this input is in high states. This pin is pulled down internally. 7, 8 OSC1 OSC2 Clock input/output. A inexpensive 3.579545MHz crystal connected between these pins completes internal oscillator. Also, external clock can be used. 9 GND Ground pin. 10 OE Output Enable input. Outputs Q1-Q4 are CMOS push pull when OE is High and open circuited (High impedance) when disabled by pulling OE low. Internal pull up resistor built in. 11 - 14 Q1 - Q4 Three state data output. When enabled by OE, these digital outputs provide the hexadecimal code corresponding to the last valid tone pair received.

15 DSO

Delayed Steering Output. Indicates that valid frequencies have been present for the required guard time, thus constituting a valid signal. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on SI/GTO falls below VTH.

16 ESO

Early Steering Outputs. Indicates detection of valid tone output a logic high immediately when the digital algorithm detects a recognizable tone pair. Any momentary loss of signal condition will cause ESO to return to low.

17 SI/GTO

Steering Input/Guard Time Output. A voltage greater the VTS detected at SI causes the device to register the detected tone pair and update the output latch. A voltage less than VTS frees the device to accept a new tone pair. The GTO output acts to reset the external steering time constant, and its state is a function of ESO and the voltage on SI

18 VDD Power Supply (+5V, Typ)

KT3170 LOW POWER DTMF RECEIVER ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VDD = 5V, Ta = 25°C, unless otherwise noted) Characteristics Symbol Value Unit Power Supper Voltage Analog Input Voltage Range Digital Input Voltage Range Output Voltage Range Current On Any Pin Operating Temperature Storage Temperature VDD VI (A) VI (D) VO II TOPR TSTG - 0.3 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 - 40 ~ + 85 -60 ~ + 150 V V V V mA Characteristic Symbol Test Conditions Min Typ Max Unit Operating Voltage VDD - 4.75 - 5.25 V Operating Current IDD - - 3.0 9.0 mA Power Dissipation PD - - 15 45 mW Input Voltage Low VIL - - - 1.5 V Input Voltage High VIH - 3.5 - - V Input Leakage Current II (LKG) VIN = GND or VDD - 0.1 - µA Pull Up Current On OE Pin IPU OE = GND - 7.5 15 µA Analog Input Impedance RI fIN = 1KHz 8 10 - MΩ Steering Input Threshold Voltage VTH - 2.2 - 2.5 V Output Voltage Low VOL No Load - - 0.03 V - VOH No Load 4.97 - V Output Current IO (SINK) VOL = 0.4V 1 2.5 - mA Output Current IO (SOURCE) VOH = 4.6V 0.4 0.8 - mA VREF Output Voltage VO (REF) - 2.4 - 2.8 V VREF Output Resistance RO (REF) - - 10 - KΩ Analog Input Offset Voltage VIO - - 25 - mV Power Supply Rejection Ratio PSRR Gain Setting Amp at 1KHz - 60 - dB Common Mode Rejection Ratio CMRR - 3.0V < VIN < 3.0V - 60 - dB Open Loop Voltage Gain GV Gain Setting Amp at 1KHz - 65 - dB Open Loop Unit Gain Bandwidth BW - - 1.5 - MHz Analog Output Voltage Swing VO (P-P) RL = 100K - 4.5 - VP-P Acceptable Capacitive Load CL GS - 100 - pF Acceptable Resistive Load RL GS - 50 - KΩ Analog Input Common Mode Voltage Range VCM No Load - 3.0 - VP-P

KT3170 LOW POWER DTMF RECEIVER AC ELECTRICAL CHARACTERISTICS (VDD = 5V, Ta = 25°C, fCK = 3.579545MHz) Notes : 1. Digit sequence consists of all 16 DTMF tones. 2. Tone duration = 40mS, Tone pause = 40mS. 3. Nominal DTMF frequencies are used. 4. Both tones in the composite signal have an equal amplitude. 5. Tone pair is deviated by ± 1.5% ± 2Hz. 6. Bandwidth limited (3KHz) Gaussian Noise. 7. The precise dial tone frequencies are (350Hz and 440Hz) ± 2%. 8. For an error rate of better than 1 in 10000. 9. Referenced to lowest level frequency component in DTMF signal. 10. Minimum signal acceptance level is measured with specitied maximum frequency deviation. 11. This item also applies to a third tone injected onto the power supply. 12. Referenced to Fig. 1 Input DTMF tone level at -28dBm. Characteristic Symbol Test Conditions Min Typ Max Unit Valid Input Signal Range (each tone of composite signal) - - Dual Tone Twist Accept TW - - ± 10 - dB Acceptable Frequency Deviation Δf - - - ± 1.5% ± 2Hz Frequency Deviation Reject ΔfR - ± 3.5% - - - Third Tone Tolerance T3rd - -25 -16 - dB Noise Tolerance TN - - -12 - dB Dial Tolerance DT - 18 22 - dB Crystal Clock Frequency fCK - 3.5759 3.5795 3.5831 MHz Maximum Clock Input Rise Time tR (MAX) External Clock - - 110 nS Maximum Clock Input Fall Time tF (MAX) External Clock - - 110 nS Acceptable Clock Input Duty Cycle DCK External Clock 40 50 60 % Acceptable Capacitive Load CL OSC2 PIN - - 30 pF Tone Present Detect Time tDET (P) - 5 11 14 mS Tone Absent Detect Time tDET (A) - 0.5 4 8.5 mS Minimum Tone Duration Accept tTDA (MIN) User Adjustable - - 40 mS Maximum Tone Duration Reject tTDR (MAX) User Adjustable 20 - - mS Acceptable Interdigit Pause tIDP (A) User Adjustable - - 40 mS Rejectable Interdigit Pause tIDP (R) User Adjustable 20 - - mS Propagation Delay Time SI to Q tD (SI-Q) OE = High - 8 11 µS Propagation Delay Time SI to DSO tD (SI-D) OE = High - 12 16 µS Output Data Setup Q to DSO tSU OE = High - 3.4 - µS Propagation Delay Time OE to Q (Enable) tD (QE-Q) EN - Propagation Delay Time OE to Q (disable) tD (OE-Q) DIS - - VI (VAL) RL = 10K, CL = 50pF RL = 10K, CL = 50pF -29 1.0 dBm 300 60 nS nS

KT3170 LOW POWER DTMF RECEIVER TEST CIRCUIT HL74LS47 b c LT RDO ABI d GND VCC f g a c d HL74HCTLS02 R3C1 300K LED KT3170 910 100K 100K X - tal 2 0.1µF 3 2 1 456 789 0 *# 8 7 18 1 X - tal 1 VCC VCCVCCVCC a LTS542R comd c dp VCC 109876 gcomfab R10 VCC KS58006 Fig. 2

KT3170 LOW POWER DTMF RECEIVER TIMING DIAGRAM Fig. 3 DIGITAL OUTPUT Outputs Q1-Q4 are CMOS push pull when enabled (EO = High) and open circuited (high impedance) when disabled by pulling EO = Low. These digital outputs provide the hexadecimal code corresponding to the DTMF signals. The table below describes the hexadecimal. Z : High Impedance H : High Logic Level L : Low Logic Level DTMF INPUT ESO SI/GTO Q1 - Q4 DSO OE DTMF #n DTMF #n + 1 DECODED TONE # (n - 1) tTDR (MAX) t TDA (MIN) tIDP (A) tIDP (R) tDET (P) tDET (A) t PGT t AGT t SU t D (SI-D) tD (OE-Q) DISt D (OE-Q) EN V TH DTMF #n + 1 NO LOW FREQUENCY HIGH FREQUENCY OE Q4 Q3 Q2 Q1 1 697 1209 H 0 0 0 1 2 697 1336 H 0 0 1 0 3 697 1477 H 0 0 1 1 4 770 1209 H 0 1 0 0 5 770 1336 H 0 1 0 1 6 770 1477 H 0 1 1 0 7 852 1209 H 0 1 1 1 8 852 1336 H 1 0 0 0 9 852 1477 H 1 0 0 1 0 941 1336 H 1 0 1 0 * 941 1209 H 1 0 1 1 # 941 1477 H 1 1 0 0 A 697 1633 H 1 1 0 1 B 770 1633 H 1 1 1 0 C 852 1633 H 1 1 1 1 D 941 1633 H 0 0 0 0 ANY - - L Z Z Z Z

KT3170 LOW POWER DTMF RECEIVER APPLICATION CIRCUIT R3 = R2R5/(R2+R5), VOLTAGE GAIN = R5/R1 INPUT IMPEDANCE : 2 + (1/wC) 2 All resistors are 1% tolerance All resistors are 1% tolerance All capacitors are 5% tolerance All capacitors are 5% tolerance Fig. 4 Single Ended Input Configuration Fig. 5 Differential Ended Input Configuration tPGT = (R1C) In (VDD/VDD-VTH) tPGT = (RPC) In (VDD/VDD-VTH) tAGT = (RPC) In (VDD/VTST) tAGT = (R1C) In (VDD/VTH) R P = R1R2/(R1 + R2) R P = R1R2 (R1 + R2) (a) Decreasing tAGT (tPGT > tAGT) (a) Decreasing tPGT (tPGT< tAGT) Fig. 6 Guard Time Adjustment Fig. 7 Oscillator Connection IN+ IN- GS VREF IIN PDN OSC1 OSC2 GND VDD SI/GTO ESO DSO OE 0.1uF 100K 100K 3.58MHz +5V 0.1uF 300K 1 10nF 100K C1 R1 10nF 100K C2 R2 R3 37.5K 60K VREF 100K GS IN- IN+ KT3170 V DD SI/GTO ESO C SI/GTO ESO C KT3170 OSC1 OSC2 30pF 3.579545MHz OSC1 OSC2 KT3170 TO OSC1 of next KT3170 √R1