KS9282B

Samsung semiconductor

CMOS INTEGRATED CIRCUIT

Manufacturer: Samsung semiconductor

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KS9282B CMOS INTEGRATED CIRCUIT DSP+ DAC (16BIT) FOR CDP 80-QFP— 14208 The KS92828 is a CMOS integrated circuit designed for the Digital Audio Signal processor of the CDP (Compact Disc Player) application. itis a Monolithic IC that builts-in 16-Bit Digital to Analog Converter to add to the conventional DSP function FEATURES s . * EFM Data Demodulation a y * Built-in frame sync detection, protection and Injection circuit Se * Correction of C1, C2 error Bi. SE * Interpolation . os Pre. Se * 8ts oversampling Digital filter (51th+ 13th +9th) LILY + Subcode data serial output * CLV Servo Controlier * Tracking Counter + Micom interface * Built-in 16K SRAM = Digital Audio out + Double speed avaliable + Bullt-in Digital PLL * Bultin 16-Bit D/A converter ORDERING INFORMATION aD 163 Te

KS9282B CMOS INTEGRATED CIRCUIT BLOCK DIAGRAM i ai Co] wer svecone | | suxcoe Qe “OT se ars - in orron Ga ———] ame maar or, Borat (7) ene Fs Fig. 1 eee —a> tha eee eee O_O

KS9282B CMOS INTEGRATED CIRCUIT PIN CONFIGURATION OHODOOODOOOOODOOO avant (1) 2) eeus 0200 (3) Osan open (3) saz oprour (2) seu: enrvor (8) Oc avssi (6) (2) we atx) Berm xn) GS) cam ror) ar woo Q G5) urxes sown) kS9282B Qn ovssi@) Crack sox Qs) G) cere coro) 65) core vecri2() ear aces (9) Scar avooe (8) Corrs acuour(s) Goes uctour G0) (<5) 082 avsse @) C5) 080 vers @) Soe vrerHe @3) (42) 08» emp (24) (088 QOOOOQOOQOOOOOOOOOO) TD 165 i

6 AVSS1 Analog Ground1 _ _ _

ry DATX Digital audio output ~ ~ -

8 XIN Xtal oscillator input - _ __

| 9 | xour a Xtal oscillator output __ _ | 10 7 wocH Word clock of 48 bit/SLOT | (Normal speed = 88.2 KHz, Double speed = 176.4KHz) ae Channel clock of 48 bit/SLOT _ ~ (Normal speed = 44.1KHz, Double speed = 88.2KH2) 12__[_apata | © | Serial audio data output of 48 bitiSLOT (MS=B first) _ 13 pvssi |_| Digital Ground 1 7 L* | ™ [e] Audio data Bit clock for 48 bit/SLOT 7 i (Normal speed = 2.1168KHz, Double speed = 4.2336KH2) [| “ears [o | czar tr ouput audio eta [ “te | er.2 || pt tinal 2 eteencevotage"CFicaing | [| WRERLt_|1 | puttin! ooereoevotge "(ND Gomecion) | [te ["avooe | | ang voor [19 [| RcHoUT | 0 | Right-Channel audio output through D/A Converter _ - [20 | ucHouT | 0 | Left-channel audio output through D/A converter | 21 | avssz | | Analog Ground 2 _— [22 | VREFH1 | 1 | Input terminal 1 of reference voltage “H” (Voo connection) [23 | VREFH2 | | | input terminal 2 of reference vollage “H” (Floating) oo a MN N a

30 Serial output of Subcode-Q data _ —

SQ0K | 0 | The CRC check result signal output of subcode-Q [32 | SBCk | 1 | CLOCK foroutput subcodeQdata _ SDAT | 0 | Subcode serial data output _ : | DVoo1 | Digital Vect _ _ 35 muTe | 1 | Mute control input ("H”:MuteON) —

36 MLT | 1 | Latch Signal Input from Micom __

a7 Serial data Input from Micom — 38 | MCK | 1 | SerialClock input fromMicom 39 | p88 | vO | SRAM data li0 Port 8 (MSB) - 40 pe7 | NO | SRAM data lO Port 7 : WO | SRAM data 1i0 Port 6 [| 42 | 0B5_ | WO | SRAMdatal/0 Ports [ao [ 0a | vo) SRAM gna one | 44 | 083 | VO | SRAMdatalio Ports | 4 | DB2 | VO | SRAMdataliO Port2 [46 | 0B1_ | v0 | SRAMdata VO Port 1(\\S8) a eS Pen cu a

50 C2F2 Monitoring output ofr C2 error correction (RA4)

st | G2FL C2 decoder flag | (High: When the processing C2 code is impossible correction State) (RA5) ; er ce (Normal speed = 4.3218MHz, Double speed = 8.6436MH7z) (RAG) [so over | PotaGromnse se) FeoW T55 Frame sync protection state (RAB)

56 Display of either RAM overflow or undertlow for = 4 frame Jitter margin(RA9)

Only monitoring signal (Normal playback: 4.2396MHz) (RA10) 58 | CIEeM 16.9344MHz signal output (RA11)

59 WE Terminal fortest __ _

60 ICS__"| WO | Terminal for test -

[a SEL Mode Selection Terminal 1 (H: 33.8688MHz, L: 16.9344MHZ) __

62 SeL2__| |_| Mode Selection Terminal 2 (H: APLL L: DPLL) :

63 | SEL3 Mode Selection Terminal 3 (H: CDROM L: CDP)

64 SELA Mode Selection Terminal 4 (L: Internal SRAM) _

65 “TEST “Test Terminal (L= Normal operating state)

6 EFMI EFM Signal input

87 | APDO Charge Pump output for analog PLL

68 ISTAT The internal status output |

a a ™ BecrmoNics mm 7964142 0025636 097 Ml

KS9282B CMOS INTEGRATED CIRCUIT @® ABSOLUTE MAXIMUM RATINGS [charterer] eres or J) er ve | 0s-r9 | Opwating Tempers | Yom | =a0=8 | Storage Tempore | tae | aaa] ee @ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (Vo0 =5V, Vss = OV, Ta = 25°C, unless Otherwise Specified) Test [| _ cramer [ores T cntnn | M[ [wae Winpor vortacey [vin wote) | ooo | =| =| ‘U INPUT VOLTAGE1 VIL (1) (Note 1) = v vm @ | wot me “HW OUTPUT VOLTAGET VOH (1) | 1OH=—imA | Voo-05 vob v (Note 3) ‘L’ OUTPUT VOLTAGE1 VOL (1) 1OL=1mA v (Note 3) ‘H’ OUTPUT VOLTAGE2 VOH (2) 10H = - 1mA Voo ~ 0.5 voD v (Note 4) “LU OUTPUT VOLTAGE2 VOL (2) 1OL=2ma v _ - (Note 4) INPUT LEAK CURRENT KG VI=0-VDD uA (Note §) THREE STATE OUTPUT lok) | VO=0-VvoD LEAK CURRENT (Note 5) | (Note 1) Related pins: All input pins except for pins of Notes (Note 2) Related pins: DB8~DB1, TRCNT, MCK (Note 3) Related pins: All output pins except for pins of Notes (Note 4) Related pins: /ISTAT (Note 5) Related pins: SMEF, SMPD, SMSD, APDO1, APDO2, DPDO ee PSisunig ”~ MH 7964242 0025638 IbT

KS9282B CMOS INTEGRATED CIRCUIT ee 2. AC Characteristics A. XIN, Voi (When the pulse Inputs to) (Vo0 = 5V, Vss=0V, Ta = 25°C, Unless otherwise Specified) [characterise] svsor [in|] wax |] LEVEL PULSEWIDTH [wen |} — | 08 % ns INPUT ‘L? LEVEL Vw [= 08 Vv RISING & FALLING TIME te tF | = 8 | ns ; | a _ | | ' === Vin x09 fl \\ I | i = vin \\ | ' | == == vinx || 1 | | tr | th ee Io to 8B. Mex, MDAT, MLT, TRCNT (Vo0 = 5V, Vss=OV, T.=25°C, unless otherwise specified) CLOCK FREQUENCY fet - = 1 CLOCK PULSE WIDTH tw _ 0 | - | = SETUP TIME ty 300 ee HOLD TIME _ tH LL 300 _ i _ DELAY TIME to | 300 = i _ IME oe - | = LATCH PULSE WIDTH _ ‘tw (LATCH) } 300 __ = i _ TRCNT SQCK FREQUENCY fekatSQck) _ i = = i 1 TRCNT SQCK PULSE WIDTH twsack, | 300 - | - ——— ELECTRONICS MM 2964142 0025639 8Tb mm ———ooeoOoOOOeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee SS...

KS9282B CMOS INTEGRATED CIRCUIT 4) CNTLZ REGISTER Itis a register to control zero cross mute of audio data, phase terminal control, phase servo and having or not of CRCF data in SQDT. i DATA DATA=0 DATA=1 ZOMT Zero cross mute is OFF Zero cross mute is ON | Hippo | D2 _| tt Operates phase normally The phase becomes “L” to “Hi-Z” NCLV | D1 | Phase Servo is acted by frame sync Phase servo is controlled by base counter crca | Do | SQDT outputs except for SAOK SQDT =CRCF when SOS1 = "H" (Tabe 2) 2) CNTL-S REGISTER It is a register to control frame sync protection and attenuation. FSEM FRAME (_WSEL CLOCK 0B 0 0 2 : o #3 fo [ o | o | 1 1 3 | 1 1 =12 (Table 3) 3) CNTL-L, U REGISTER ; After the counter of track that must be counted is inputed from Micom, the data is loaded to tracking counter by CNTL-L, U register. a” " FLECTRONICS wy 79Q4142 OO25b41 454 Ml aoe aaa

KS9282B CMOS INTEGRATED CIRCUIT ee 2. Tracking counter block This block is used to improve track-jump characteristics. The number of tracks that are to be jumped are loaded into either register CNTL-L or CNTL-U. After either register CNTL-L or CNTL-U has been loaded, and at the rising edge of the next MLT, the TRCNT pulse count begins. ‘When n (if register CNTL-L = register = CNTL-U=0, thenn= 256) is loaded into the register, and then at low level tor succeeding pulses. When the address is set in CNTL-U, the ‘signal (COUNT) TRCNT/2n is output. The following is timing chart of tracking counter block. Mur aes ll 2 CNTL-L,U = - Yor Er Tracking Count Bi jal a Load! Ing = (COUNT) + N N ASTAT xX = nN =(/COMPLI (Fig 2. Tracking Counter timing chart) PA O— > coe El poems I meres Ol eee OA pee CNTL State (CORTEX CHIT Kotor Mode STAT CToomplet YX ~Teount XX 7Pws64_ Xz (Fig 3. ISTAT output signal according to CNTL Register) ——— FLECTRONICS = 796442 0025643 227 Ml 0 eee

KS9282B CMOS INTEGRATED CIRCUIT 3. EFM demodulation block The EFM block consists of EFM demodulator which demodulates EFM data obtained from a disc, EFM phase de- tector and controller etc. 1) EFM phase detector. As the EFM signal inputed from a disc includes the components of 2.1609MHz, the EFM phase detector uses the Bit clock (PBCK) of 4.3218MHz to detect the phase of this signal. This PBCK detects the phase at the edge of EFM signal and the result is outputed to the APDO terminal. A, At Normal operating veo: CLA UU ULL. Pecks Lk EFMI: J 1 I t 1 ! _ APDO: “it _ im Hi-Z ial Hi-Z 1 2 3 In the case of 1: When the EFM signal is slow than VCO In the case of 2: When the EFM signal is locked with VCO In the case of 3: When the EFM signal is faster than VOC. (Fig 4, Timing chart of the EFM phase detector) B. At abnormal operating | If the HIPD of CNTL.Zis “H” and “L" of the LKFS is shorter than 3.5T (a period PBFS Is 7), the Hi-Z is outputed to | APDO terminal as many as “L" and if be over 3.8T, the Hi-Z is outputed as many as 3.8T. ' a ELECTRONICS MB 7964142 OO25b4u4u 163

= eee 2) EFM demodulator The 14 Bit data through the circuit changes to demodulate 8 bit data. Demodulated data has two kind of signal, the one is subcode data and the other is audio data, and that one is inputed into the subcode block and this one is written in the 16K SRAM and performs error correction. 3) Frame sync detector, protector and inserter A. Frame sync detector The data consists of frame units, that is, it consists of frame sync, subcode data, PCM data, Redundancy dataetc. The frame sync is detected in order to maintain the sync. B. Frame sync protectorlinserter . Occasionally, the frame sync is omitted or detected in the place where it doesn't exist by the effect of error or Jitter on a disc. In these cases, we need to protect or insert the signal. The window is made by using the WSEL to protect the frame sync. If the frame sync is inputed to window, it is true data and if isn't inputed, it is ignored. The width of window Is determined by WSEL of CNTL-S register. If the frame sync is not detected in the frame sync protection window, one is inserted from the internal counter block. When the appointed number of frame is achieved by FSEM, FSEL of CNTL-S register, ULKFS becomes “L” and frame sync protection window is ignored. ‘The frame sync is received absolutely at that time. When the frame sync is received, the ULKFS signal becomes “H" and the frame ‘sync In window is received. vcs [comment

1 Corresponding with playback frame sync and generated frame sync

1 Out of corresponding with playback frame sync and generated frame sync

but PBFR Sync is detected in the window selected by WSEL. 1 2 Out of corresponding with PBFR Sync and XTFR Sync, and sync is insert- ed because it isn't detected in the window selected by WSEL. 0 * After insertion as many as the frame decided by FSEM and FSEL of CNTL- | S register as frame sync isn’t detected in the window.

2 In the case that the PBFR sync is not detected continually after @

(Table 7) 4) Subcode Block The 14 Bit subcode sync signal (that is SO, S1) is detected in the sub code syne block. After SO + S1 signal is outputed to S0S1 terminal, and the subcode data is outputed to SDAT terminal when the S0S1 signal is “H” It Is synchronized with PBFR signal and it Is outputed to SDAT by SBCK Clock Among the eight subcode data, only Q1 data is selected and loaded to the eighty shift register by PBFR signal The result of checking the CRC (Cycle Redundancy Check) of toading data is synchronized with S0S1 rising edge and outputed to SQOK terminal. If the result of checking is error, “L" is outputed to SQOK terminal and if It is. true, “H” is outputed to. And if the CRCD of CNTL-Z Mode is “H", the result of CRC check is ‘Outputed to SQDT terminal during from S0S1, “H” to SQCK following edge. TT an” ” ics. BECTRONES wm 79641U2 0025645 OTT ml ee

KS9282B CMOS INTEGRATED CIRCUIT The following is the timing chart of subcode block 1) At SQEN ="L”: SDAT, SQDT, SOS1, SQOK, VCO! timing Chart. Let ei Veol: Ba Og gO eB PBFR: 1 . ‘$0S1: x SQOK: X SQCK: | ——l SDAT: SQOT: (Fig 5. Subcode-Q Timing Chart 1) 2) At SQEN =""L”: SQOK, SQDT, S0S1 timing Chart. s00K: JX >73> SOOT: WOTEKGTKSTOR NK EX TK TINK GEK GENS, NINOS GSENGT SOOO? (Fig 6. Subcode-Q timing chart 2) 3) At SQEN =H”: SQCK, SQDT, SOS1, SQCK Timing chart. 800K: XFS > sock: LALLA SaQoT: ° VED CE CECT) CE OD OE OEY STF, Ay LTE OLE" CF 0 SOX | CRCD=0 =~ RCD = 17 ~—— | (Fig 7. Subcode-Q timing chart 3) eeeSeSSeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSssssesese ELECTRONICS | MM 7964142 OO2564b T3b - EE EE EE EEE Eee SSS 8.

KS9282B CMOS INTEGRATED CIRCUIT ss eee Comment: If the SQOK of the subcode Q data is "H” the subcode Data is outputed to SQDT according to SQCK signal. If the SQOK is “L”, it is outputed to SQDT with “L”. 4) VCOI, SDAT, SBCK Timing chart. JT he veo LTR Luu uur PRFR: ~~ a. 1 Z se AAA AAA A SDAT: Kp XOKXRXSXTXUXVK WX a (Fig 8. Timing chart of subcode data output) pa a: After PBFR becomes failing edge, SBCK becomes “'L” during about 10usec. b: If SOS1 is "L”, subcode P is outputed. And if “"H", SOS1 is outputed. c: If a period of VCOI is “T", the width of c is 4T-6T. eee Poimsunad = BLECTRONCS gs 754142 OO25b47 I72 Ml

KS9282B CMOS INTEGRATED CIRCUIT ———— 4, ECC (Error Correction Code) block The function of ECC Block is to recover damaged data to some extent when data on a disk is damaged. By using CIRC (Crossed-interleave Reed-solomon Code), C1 (32, 28) and C2 (28, 24) errors are corrected. ECC is performed by the unit of one symbol of eight bit. In correcting C1, a C1 pointer is generated, and in correcting C2, a C2 pointer is generated. C1, C2 pointers send error information or the data which ECC is given. . After correcting C2, against uncorrectable data, Error data is sent to display by outputing a C2 flag. The C2FL signal is handied in the interpolator by using the Signal of C2F1 and C2F2. [cir Gre] 64, HERRON Sats [0] NoeROR [0 1 _SINGLE ERROR CORRECTION | 0 | [oq 0 DOUBLE ERROR CORRECTION 1 lo | p+ 0 | __DOUBLE ER 1 1 1 IRRETRIEVABLE ERROR 1 [1 | (Table 8) C1F1, C1F2; The error correct status is outputed by C1 decoder. C2F1, C2F2: The error correct status is outputed by C2 decoder. C2FL: In the case that the error can’t be corrected by C2 decoder, becomes “H”, and the reverse case becomes "'L”. am “ euecrronics = MM 7964142 0025648 809 mm

KS9282B CMOS INTEGRATED CIRCUIT See ees 5. Interpolator/Mute block 1) Interpolator When a Burst error occurs on a disc, sometimes the data can’t be corrected even if a ECC process is performed. The interpolator block revises data by using a C2 pointer outputed through the ECC block. The data inputed to a data bus is inputed to the left and right channel, respectively, in the order of C2 pointer, Low- er &-bit, and upper 8-bit. A pre-hold method is taken when a C2 pointer is “H™ continuously. In case of the occurrence of a single error, an average interpolation method is carried out with the range of the data before and after an error happens, When a check against a checked cycle is “L”, R-CH data is outputed. L-CH data is outputed when the check is “HH”. A Sy ae cs ee a pinter p= At© : AVERAGE INTERPOLATION F=£=D : PREVIOUS DATA HOLD G@= F+H ‘AVERAGE INTERPOLATION (Fig 9. Interpolation) —— ees BECTRONICS ag PqQyL42 OO25b49 745 Me ee

KS9282B CMOS INTEGRATED CIRCUIT een nee 2, Mute and Attenuation - By using a mute terminal and the ATTM signal of the CNTL-S Register, Audio data is muted or attenuated. There are two kinds of mute: Zero-Cross muting and muting A. Zero-Cross muting The audio data is muted, after ZOMT of CNTLZ register goes to“H”, and in case that mute is “H” and the upper 6 Bit of audio data become all "L" or "H”. B. Muting The audio data is muted when ZCMT of the CNTL-Z register is “L" and mute terminal is “H”, ©. Attenuation The signal attenuation is occured by ATTM of the CNTL-S register and mute signal as following. a _ ° - — 0d8 _ 9 i dB | ot _o = 1268 | 1 1 = 1208 (Table 9) SSF a . ™ NICS. | mm 7964142 OO25650 467 Le

KS9282B CMOS INTEGRATED CIRCUIT 6. Digital Filter The KS9282B has a built-in FIR (Finite impulse response) Digital filter This Digital filter Consists of 8 over sampling filter. A. Block Digram 1. Normal Speed Play mode fs} Sith ats ‘3th 4s oth ats FIR FIR FIR

16 BIT

Double Speed Play mode pa tee | ith ats* sth ats" FIR FIR

(Fig. 10 Digital filter block digram) LL {CTRONICS Be mm 7964142 OO25b51 373 oOoOoemeO a...

KS9282B CMOS INTEGRATED CIRCUIT ee B. Filter characteristic 1. Ripple in passband: Within + 0.508. 2. Attenuation in stopband: below - 42dB (a) NORMAL SPEED L} tT TT LTE | tT 2 (wm | AAT | UN WR Aer 2 t i PP ry [i Pe frequency (Fs) (b) DOUBLE SPEED. y V PLT TT Ty fp - LL EaAtTal ae CCP , frequency (Fs) (Fig 11. Filter Characteristic Curve) <r ™ FECTROMCS MM 7964142 OO25b52 237 Me

KS9282B CMOS INTEGRATED CIRCUIT 7. Digital audio out block The 2-channel, 16-Bit data is connected and outputed serially to other digital system by the digital Audio intertace format. 4) Digital audio intertace format for CD =lele[e [=]? alee = To] l+—t— | | | ‘OL: L-CH format included block sync preamble 1L~191L: L-CH format included L-CH sync preamble OR ~ 191A: R-CH format included R-CH sync preamble PREAMBLE] modulated ‘0’ 8 BIT | modulated 16 BIT AUDIO DATA Lvfofele| CONTROL signal (Fig 12. Digital audio out format) A. Preamble Its used to discriminated against the block sync of data and L/R-channel of data. a See Sa L-CH SYNC (Except for Block Sync) ' 1 711} now ewe rs on oy es fl |, BLOCK SYNC (L-CH) I | (Fig 13. Preamble Signal) — eee an “ ELECTRONICS wg 79b4L42 0025653 17b Ml Oe

KS9282B CMOS INTEGRATED CIRCUIT 8. Control Signal 1 Validity bit: It is indicated that the error of 16-Bit audio data exists, or don’t (“H” Error, “L”: Valld data) 2 User definable bit: Subcode data input. ss SC Ss a: as cs i seck ——— WU SeOgog000!G SDAT (Fig 14. Timing chart of digital audio out) 3. Channel status bit;Output a high position information of 4-bit of subcode Q indicate the number of channel, preemphasis, and copy etc. Indicate CDP category ee i soot ——L TT) HL 100 1D1 COPY EMPH rere LLL Le (Fig 15. Timing chart of channet status data output) 4 parity bit: Making even parity LL _ ELECTRONICS We 7964142 0025654 O02 me satan,

KS9282B CMOS INTEGRATED CIRCUIT Kserepp CMOS INTEGRATED CIRCUIT 8. CLV Servo block The CNTL-C register is selected to control CLV (Constant Linear Velocity) servo by the data inputed from Micom In the CNTL-C register, the CLV servo action mode isappointed by the data inputed from Micom to contro! the spindle motor. 1) Forward Mode The terminal condition of output mode is that SMPD is “H", SMSD is “Hi-2", SMEF is “L" and SMON is “H". 2) Reverse mode The condition of reverse mode is that SMPD is “L", SMSO is “Hi-2", SMEF is “L” and SMOD is “H”. 3) Speed-Mode The spindle motor is controlled roughly by the mode when track jumping or EFM phase is unlocked. if a period of VCO is “T", the pulse width of frame sync is 22T. in case that the signal detected from EFM signal exceed 22T” by noise on the disk... etc., it must be removed, if not, the right frame sync can't be detected. In these case, the pulse width of EFM signal is detected by period of XTFRV2 or XTFR/4 and the pulse width of EFM singal is detected by the period of XTFR/16 or XTFRI32. *Peak hold clock is XTFR/2 or XTFR/4, and bottom hold clock is XTFRI16 or XTFR/32 The detected value is used for syncronized frame signal. Mf syncronized frame signal is less than 24T, the SMPD terminal outputs ‘L’, equal to 22T, outputs ‘Hi-Z’, and more than 23T. outputs ‘H’. If the gain signal of CNTL-W Reg is L the output of SMPD terminal is reduced up to-12 GB. If it is ‘H’, there is no. reduction. (refer to figure 4) Output conditions SMSD = HI-z SMEF ='L' SMON =‘H’ 4) Hi-speed-Mode The mirror does main of track which havn't pit is duplicated with 20KHz ‘signal to EFM. in this case, servo action be to unstable because the peak value of mirror singal which is longer than original frame syne signal is detected. In Hi-speed mode, by using the 8.4672/256 MHz signal against peak hold and XTFR/16 or XTFR/32 signal against bottom hold, the mirror is removed, and hi-speed servo action be to stable. Output is that SMSD is ‘Hi-z’, SMEF is ‘L’ SMON is “H™. 5) Phase-Mode The mode for controls EFM phase. Phase difference between PBFR/4 and XTFR/4 is detected when NCLV of CNTL-Z is L’ and phase difference between Read Base Counter/4 and Write Base Counter/4 is detected when NCLV is ‘H’, and the difference is outputed to SMPD. “H’ is outputed from falling edge of PBFR during (WPO-278T) x 32 to SMSD terminal and *L’ is outputed up to falling edge of next PBFR (refer to figure 5) 6) XPHSD-Mode The mode for using normal action. The LKFS signal made from frame sync block is to sampling which period is PBFR. If ‘sampling is “H", Phase Mode is performed, and if the sampling is eight of ‘L’ continuously, speed mode is performed automatically. Selecting Peak hold period of speed mode, and bottom hold period and gain of speed/hi-speed mode is determined by CNTL-W Reg. 7) VPHSP —Mode The mode to controls rough servo. instead of X'tal VCO is used to test EFM pattern. f the center value of VCO is varid the rotation of spindle motor is varied to same direction and VCO is locked easily. 8) STOP ‘The mode for stop spindle motor. Output is that SMDP is “L', SMSD= ‘Hi-Z’ SMEF is ‘L', and SMON is ‘L’. an ELECTRONICS me 7964142 0025655 THI ae eee OO EE eeese————SaaaQaQg«

KS9282B CMOS INTEGRATED CIRCUIT XTFRIS l J l J (XTFRIB) H 1 ' { ' \\ PBFRI4 ee es Re ee a ees (PBFRI8) i it emso: Hiz A en SO u (Fig 16 Timing chart of SMSO output) —287T-- rere —J LS LL ‘MSD: SR re (a) Timing chart of SMSD output when PBFR is “2877”. = 206T > corr —F LS Le J itll oes fl pam fl GD — (b) Timing chart of SMSD output when PBFA is “294T (Fig 17. Timing chart of SMSD output at phase mode) a ELECTRONICS «MM 7964142 0025656 985 Ml

KS9282B CMOS INTEGRATED CIRCUIT Oren ever onc oo EFM WIDTH (2227) ¢ Lj PH FIF (2237) a a lis (i) rs ‘aten@an (2 yo I 2: 227 (output for.) i i (Fig 18. Timing chart of SMPD output when the Gain is “H” in the speed Mode). eee ELECTRONICS gs 7qQ4142 OO25b57 81) ml eee

KS9282B CMOS INTEGRATED CIRCUIT 9. Digital PLL Biock This device contains Analog PLL and digital PLL together in order to obtain the stable channel Clock for demodulating . EFM signal. The application diagram of digital PLL is as follows. DPDO Frequency DPFIN Xtal . ‘Synthesizer DPFOUT CNTVOL, (Fig 19. Digital PLL Circuit diagram) 10. DIA Converter (Digital to Analog Converter) The.KS9282B has a built-in 16-Bit D/A converter. Digital audio data is a 2’s complement serial signal. (MSB first) a” Xm ELECTRONICS gy 29,4142 0025658 758 Ml

KS9282B CMOS INTEGRATED CIRCUIT nena A, Vref terminal (See. Fig 20) Vref, the reference voltage across a resistor-ladder, is usually recommended with vrefHi1 = SV, VrefL1 = OV. One way of avoiding an amplitude mismatching between the Vref and op amp input connected to the output of the DIA converter is to reduce the analog output amplitue with VrefH2= SV and VrefL2 = OV (at this time about 11004) Capacitor should be connected from Vref and VrefL1 to GND) By the effect of built-in RH and RL with this choice, the maximum analog output amplitude results in a narrow range of about 1.5 ~ 3.sy for 0dB playback. VretHt = VrefH2 1@) Le) 03~Do, ANALOG CHIOUT D1S~ D7 —O . | | Mux cH2ouT VOLATE DIVIDING DIA CONVERTER ai CONTROL CIRCUIT Dé~D4 O oO Vref Lt Vref L2 (Fig 20. Vref relation circuit) B. D/A Converter Electrical Characteristic The D/A Converter electrical characteristic built in KS92828 is as follows. (Veo =5V, Ves=OV Ta = 25°C) Characteristics ‘Symbol Test condition Min | Typ | Max [Unit Total harmonic THD DATA=1KHz, 0dB —- 7, - 0.08 ~ | distortion L ee | ae | Signal to noise SIN Voo =4.6V — | ¢ — | ratio _ DATA = 1KHz, 048 | Cross talk cT DATA = 1KHz, 0B. - 85 - | (Table 10) a PSimsunig " BLECTRONICS wm 7964142 OO25659 654 ml ee

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KS9282B specifications and overview.

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CMOS INTEGRATED CIRCUIT

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CMOS INTEGRATED CIRCUIT

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