KS9210

Samsung semiconductor

CMOS INTEGRATED CIRCUIT

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KS9210 CMOS INTEGRATED CIRCUIT TT _, DIGITAL SIGNAL PROCESSOR } The KS9210 which is CDP DSP IC improved digital filter characteristic 00 GFP includes digital audio output to interface other system directly. | oe | FEATURES = aS * EFM Phase detector circuit is < / * EFM data demodulator ~ | * Include sync frame detection, protection, and injection circuit } * Correction of C1, C2 error © Interpotator * Subcode data processor | * CLV-servo controller * Tracking counter * ,-com interface * Digital filter (Linear-phase FIR) + S-RAM address generator ORDERING INFORMATION + 16K SRAM * Digital Audio out [Device | Package | Operating Temperature * 1.2um CMOS process [_Ksez10 | eoarP | -20°C~ +75°C & SAMSUNG ae Electronics

KS9210 CMOS INTEGRATED CIRCUIT ees se cee BLOCK DIAGRAM O“O-AQOCOLL mb 2 PTT McK (13) our U a ~ omer (1) | swon (2) J suo (3) Senvo suscove @ om sso (a>) too (79 | e088 sos | =s6 5 | | veoo (8) yoo FRAME SYNC vot (3) GENERATION BLOCK j (62) crs 8 on rT | & ore | eS | LC car EFMO. | 2 CF roase | UL en | {Ov ou ETOR Dewooutaror [9 Tf wm | (5) v00 Pras G1) (s2) vss Cd a td ST COOOO—O) ©) OOO) Fig. 1 eee & SAMSUNG “° Electronics

KS9210 CMOS INTEGRATED CIRCUIT PIN CONFIGURATION BS EefEP RG gee e8eyeh8 859988 OOOO OOO VOOO ODD OCTOOOOO8 cara @8) Gd) 108 cert 6) G9) ave par. 67) G8) 01 OXTFR 68) 67 pet para G9) Ge) vee PBCK, (70) @) 063 tsow (7) G4) 08 uses (72) @) ve0 voo (%3) G2)o0s or &) G)) os6 awock (5) Go) 08 wax) 5) 088 ocx) Ques pata (78) QDowre 6) sen woon @) G5)socx cucx 0) QOOCOOOOOOHOGHGOOOHOHOPOSS PePREP EERE P FSR SRE ERE HEEB Fig. 2 a 420 & SAMSUNG Electronics

KS9210 CMOS INTEGRATED CIRCUIT eee PIN DESCRIPTION Pin No| Symbol vo Description L a _ SMEF OO _ LPF time constant contro! signal of the spindle motor error signal 2 'SMON ° On/Off contro! signal for the spindle motor “3 | smpo | Oo} Spindle motor drive, (Rough control in the S-Mode, phase control in the a ne SO a | smso | 0 | Spindle motor drive. | | | | Velocity control in the P-Mode : __ |

5 EFMI | 1__|_EFM signal input terminal _

6 EFMO | Oo | Slice level control signal of EFM signal |

14 MUT 1 LATCH CLOCK from y-com

45 MOAT DATA from j-com

19 MUTE | 1 Muting input — 7 — |

26 SQEN | 1 | SQCKWOselectionterminal SSS

i ((L': SQCK output, ‘H’: SQCK input) a7 ~DATX. | OO ~ Digital Audio Output ~

28 LKFS | O Output the Lock Conditions of frame syne —

29 pes) «vo | CMSB — ~ ~ | ~ | Hi2 at the normal operating (TEST ="'L", SRAM="L")

2 DBS | WO | Data Infoutput at SRAM TEST ee

33 Vo | — +5V

34 vas | 10 - ~ 37 pet vo (sa) —CHFOT_CFO FER NroO2€4ONNuoAURN SAMSUNG “ Electronics

KS9210 CMOS INTEGRATED CIRCUIT PIN DESCRIPTION (continued) (oom om [| oe 38 iH (LSB) Hi-2 at the normal operating (TEST ='L’, SRAM ='L’) H - ~ in/output at test (TEST ='H’, SRAM ="H’)

48 Aptt (mse)

HiZ output at the normal operating, and Write enable input at the SRAM test 50 cs vo Hi-Z output at the normal operating | _ Chip enable input at the SRAM test |

51 McK ° Divider output of Xiw

{= 4.2336 MHz | se | Vs | — | Ground a 7 |

53 Xe | 1] Input terminal of crystal oscillation circuit

| According to mode, f = 8.4672 MHz or 16.9344 MHz | _S4 _Xor__| 0 Output terminal of crystal oscillation cireue 55 seu) Mode selection terminal 1 |

56 SEL2 | | | Mode selection terminal 2 —

a7 | se | Mode selection terminal 3 } “58 “SEL4 | |_| Mode selection terminal 4 - |

59 SRAM 1 Normal operating ='L’, TEST="H" |

‘eo | aptR | o Output to compensate R-CH Aperture (H'=R-CH) j “se | apm | oO Output to compensate L-CH Aperture (‘H’ = L-CH) | | 62 ciF1 | © | __ Output when SEL4 is ‘L” : 1 [63 | ciF2 | © | _ Outputwhen SEL4is‘L’ OS : i 64 cori | Oo Output when SEL4is‘U a

65 Core ° Output when SEL4 is ‘L’ oO i

70 PBCK ° Output when SEL4 is ‘L’ ;

KS9210 CMOS INTEGRATED CIRCUIT Notes) 1. XTFR_ : 7.35 KHz frame sync signal made by X'tal. 2. PBFR 7.35 KHz frame sync signal of PLAY BACK made by DATA which being reproduced. 3. PBCK Channel bit clock of DATA which being reproduced. “oo at the normal mode. 4. FSOW Unprotected frame sync. 5. ULKFS : FRAME sync protection condition. 6. JIT Display of either RAM overflow or underflow for +4 frame jitter margin, 7. 2WDCK : Strobe signal Digital filter On=352.8 KHz Off = 176.4 KHz 8. BLCK BIT CLOCK Output signal. Digital filter On = 4.2336 MHz Off = 2.1168 MHz a & SAMSUNG 23 Electronics

KS9210 CMOS INTEGRATED CIRCUIT ABSOLUTE MAXIMUM RATINGS (ra=25°C) ‘Supply Voltage Voo -03~+7 v Input Voltage vi -03~+7 v Output Voltage Vo -03~+7 v Operating Temperature Tora -20~ +75 °c | Storage Temperature Tero ~40~ +125 °C

ELECTRICAL CHARACTERISTICS

DC Characteristics (Voo=5V + 10%, Vss=0V, Ta=25°C, unless otherwise specified) [input High Voltage | Vn Note 1 “0.7Voo Vo |v Input Low Voltage Vent Note 1 0 0.3Vo | V f Input High Voltage Vine Note 2 0.8V00_ i v h Volta, M i v |__ Input Low Voltage ine _| __Nowo2 dt 12.200 |v Output High Voltage _ Vou | lon= - 1A Voo - 0.5 Voo v Output Low Voltage — | Vou l= mA | 0 04 v | Input Leakage Current lino | Vw=0~5.5V | | | +8 A Three State Pin \\ =0~ j | |__Output Leakage Current ne Vour=0~5.6V ) #5 | A Note 1. Related Pins - EFMI, RESET, TEST, MUTE, SEL 2~5, MLT, MDAT, SQEN. SQCK Note 2. Related Pins - TRCK, MCK, SRAM 2. AC Characteristics ‘A. Xw and Veo) terminal (Voo = 5V + 10%, Vss = OV, Topa =O~ + 70°C, unless otherwise specified) Oscillation Frequency [tose Pe Tie & SAMSUNG “ Electronics

KS9210 CMOS INTEGRATED CIRCUIT B. Pins MCK, MDAT, MLT, TRCK, SQCK (Von =5.0V + 10%, Vss=OV, Topr = 25°C) Clock Frequency fxs | I 1 MHz Clock Pulse Width tons 300 _ | _1s [Set Up Time tu 300 | - | _ns [Delay Time & [300 __t_ ns C. D/A Converter Interface Terminal (Pins CHCK, WOCK, APTR, APTL, C1F1, C1F2, C2FL, DAFL, XTFR, 2WDCK, DATA) it symbot | OF OFF [eecrrusowen fw] pe fe [Goa stow rasn | wm | Tw | dt —_[$ & SAMSUNG “ Electronics

KS9210 CMOS INTEGRATED CIRCUIT

APPLICATION INFORMATION

MODE SELECTOR SEL1 | SEL2 | SEL3 | SEL4 | SRAM DF DAC__| AUDIO 1exsRAM | Ps |2s/oB| /ROM o To [oo | o | o | ‘ON ON | S | 28 | AUDIO | intemal o|o!]o0 1 ° - i Poop i | ° 1} olfolo OFF ‘ON | i _| pet “Lr 6s po tifa fe ee ee _4 1 olofilo | p foo) | a poy yy sles) | Lpoltt | i Pp | 08 1 ry ° 16M on | | | s /es 1 1 [tio 8M OFF in ROM | 1) Xm is the input terminal of crystal oscillator. 16M = 16.9344 MHz, 8M = 8.4672 MHz 2) DF is imernal aigital titer On condition: Output the data after pass by fiter Off condition: The opposite of ON condition DO shows digital audio out 3) S of DAC is outputed serially to PAD 78 and 2S is 2's complement. OB is OFFSET BINARY and shows inversed MSB. 4) When SRAM is ‘L’, use internal SRAM. 5) Audio use Audio Application and ROM use CD-ROM application in the Audio/ROM 2. u-Com Interface tne DATA inputed from ,-Com is inputed to MDAT and transtered by MCK The signal is inputed to MLT terminal in order that the data inputed is loaded to one of six control register. "LLL Moat Xb0Xd1 Xb2 Ys X04 X05 Xo6 X_b7 Mss, — DATA. == — ADDRESS. MLT es fe Internal Rea. Appointment, VALID DATA Fig. 3 -COM DATA INPUT TIMING CHART & SAMSUNG 42s Electronics

f 2 | DATA CONTROL _ toon | EcwT oe. Table 1. Control Register Selection u-Com Data ‘or not of CRCF DATA in SQDT. It is a register to control FRAME SYNC, PROTECTION, ATTENUATION... etc.

5) CNTL-C Register FORWARD 1000 H Hi-Z L | H REVERSE 1010 | L Hi-Z L H SPEED 1110 SPEED Hi-Z L H HSPEED | 1110 1100 { HSPEED Hi-Z L H | PHASE | wit PHASE PHASE Hi-Z H XPHSP_ ij 0110 | SPEED, PHASE | Hi-Z, PHASE L, Hi-Z | H VPHSP 0101 SPEED Hi-Z, PHASE L, Hi-Z H STOP 0000 L Hi-Z L t 3. Tracking Counter ‘This block used for track jump perform that the data, which must be jumped, inputed from ,-Com is loaded to CNTL-L, U at rising edge. Loaded Data is starting the count by ‘tracking counter clock track, if CNTL-L is selected COMPLETE ‘signal is outputed to ISTAT terminal, and if CNTL-U is selected, COUNT signal is outputed to. When CNTL-L reg is selected, if the pulse width of bottom hold exceed 64T (T: a period of PBFS) ‘L’ is outputed to ISTAT terminal. The result is detected after reverse command is inputed from y-com and is that the speed of spindle motor reduce. The following is timing chart of tracking counter block. on, XO ma ve FU AL Le (COMPLETE), | Ll Fig. 4 Tracking Count Timing Chart Fig. 5 CNTL Reg. According to Output Signal of ISTAT a & SAMSUNG nad Electronics

KS9210 LINEAR INTEGRATED CIRCUIT ksezio OE eee 1) Block Diagram oO © " bed) ™ Lo ==) TMCK = V [PX) | y Ee D Ee cx Fig. 6 X'tal OSC Block Diagram 2) Using the X’tal osc of 16.9344 MHz, Timing Chart (Sel=0) ' ' ' aMCK: of 3) Using the X'tal osc of 8.4672 MHz, Timing Chart (Sel=1) 1 1 1 1 a A rr ee 5. EFM EFM consist of EFM demodulator which demodulate EFM DATA inputed from the Disk, EFM phase detector, frame sync detector/protector/inserter, subcode sync detector, and controller which controls EFM block etc. So & SAMSUNG 42s Electronics

KS9210 CMOS INTEGRATED CIRCUIT MOS INTEGRATED CIRCUIT 1) EFM Phase Detector As EFM inputed from disk includes the component of 2.11 MHz, EFM Phase Detector generate the bit clock (PBCK) of 4.32 MHz to detect the phase of this signal. This PBCK detects the phase at the edge of EFM signal and the result is outputed to phase terminal. A. At normal operating ec JS LILILSLPFLrYLrert_reL_rei_ | i H i H : HZ Hid HiZ Hz LW “LU “Lu Fig. 7 EFM Phase Detection Timing Chart In case of ©: when EFM signal is slow than VCO In case of @: when EFM ‘signal is locked with VCO In case of @: when EFM signal is faster than VCO 8. At abnormal operation It HIPD of CNTL-2 is selected ''L" by »-com EFM phase detector operates like (Figure 5) If HIPD is ‘H’ and ‘L’ of LKFS is shorter than 3.5T (a period of PBFS is T) Hi-Z is outputed to PHAS terminal as many as ‘L' and be over 3.5T, Hi-Z is outputed as many as 3.5T 2) EFM Demodulator Modulated 14 Bit DATA is inputed into NRE-T circuit in the DSP. The 14 bit DATA through the circuit changes demodulated 8 bit DATA as NRE-I circuit convert 14 bit EFM data to 8 bit data. Demodulated DATA have two kind of ‘signal, the one is subcode data and the other is PCM data, and that one is inputed into subcode block and this one is written in the 16K SRAM by CE and WE signal. a & SAMSUNG “0 Electronics

3) FRAME SYNC DETECTOR INSERTER/PROTECTOR a. Frame sync detector The Data consist of PRAME units, that is, it consist of frame sync, subcode data, PCM data, redundancy data... ete he frame sync is detected by one per frame unit

1 Frame (588 CHANNEL BITS)

Ot Frame (688 CHANNEL BITS) REDUNDANT BITS FOR MERGING AND LOW FREQ. SUPPRESSION / / DATA C1 PARITY DATA C2 PARITY A 7 A FO De WaWeefedaeafel alfa salalf ve ve fbsa vw Moulds Me eva Hse He We Wie Wo Well sels sl easel se 28 VYVV ieee ee eee see se see ss eee ees 3 \\ PCM Data Symbol and Parity Symbols \\ (14 Channel Bits = 8 bits Symbol) \\ ———< Control Display Symbol Data ——————< Frame Syne. Pattern (24 Channel Bits) Fig. 8 (Frame Format) B. Frame sync protector/inserter Frame sync is omitted or detected in the place where it don't exist by the effect of ERROR or JITTER on the disk. In these cases, we need to insert or protect the signal. The window is made by using the WSEL signal to protect the Frame Sync. The frame sync inputed to window is ture data, and don't inputed is ignored. ‘A width of window is determined by WSEL of CNTL-S Reg. If frame sync didn't be detected in the FRAME SYNC PROTECTION WINDOW, frame sync made by EFM Block is inserted in case of the sync is inserted sequencely. When the appointed number of FRAMEs is achieved by FSEM, FSEL of CNTL-S Reg, the ULKFS becomes “L” and FRAM SYNC PROTECTION WINDOW is ignored. FRAME SYNC is received absolutely at that time. When Frame Sync is received, the ULKFS signal becomes "H"" and FRAME sync detected in window is received. LKFS: ULKFS: Explanations 1 1 ‘Accordance with PLAYBACK FRAME SYNC and generated FRAME SYNC. ° 1 @ Out of accordance with PLAYBACK FRAME SYNC and generated FRAME j | SYNC, but PBFR SYNC is detected in the window selected by WSEL | | | @ Out of accordance with PBFR SYNC and XTFR SYNC, and SYNC is inserted | because it don’t be detected in the window selected by WSEL. | ° © | _ @ After insertion as many as the Frame decided by FSFM and FSEL of CNTL-S | Reg. as frame sync don’t be detected in the window. i @ In case that PBFR SYNC don't be detected — SSeS & SAMSUNG ‘1 Electronics

KS9210 CMOS INTEGRATED CIRCUIT ae MOS INTEGRATED CIRCUIT 6. Subcode 14 bit Subcode Sync Signal (this is SO, S1) is detected in the Subcode Sync. After SO is detected, a frame of S1 is detected. At that time SO + S1 signal is outputed to S0S1 terminal, and SO, $1 signal is outputed to SDAT terminal when SOS1 signal is “H". After 14 bit subcode data becomes EFM demodulation, the 8 BIT of subcode data (P, Q, R, S, T, U, V, W) is syncronized with PBFR signal and is outputed to SDAT by SBCK CLOCK. Among the eight subcode DATA, Q1 data is selected and loaded to the eighty shift resister by PBFR signal. The result ‘of checking the CRC (cycle redundancy check) of roading data is syncronized with SOS1 rising edge and outputed to SQOK terminal. If the result of checking is error. “L” is outputed to SQOK terminal and if it is true ““H” is outputed to and if the CRCD of CNTL-Z Mode is "'H"’, the result of CRC CHECK is outputed to SQDT terminal during from SOS1, 'H’ to SQCK FALLING EDGE. The following is the timing chart of subcode block. 1) at SQEN =‘L’, SDAT, SQDT, SO0S1, SQOK, VCOI Timing Chart TH ver LIL LS LLL LLL PBFR: — s0s1 X SQOK: X SQCK: —_I b—2T—_+ SDAT: X SQDT: X Fig. 9 a & SAMSUNG se Electronics,

Ks9210 CMOS INTEGRATED CIRCUIT 2) at SQEN='L', SQOK, SQDT, S0S1 Timing Chart soc. LITLE LLL Le ' 1 sa0K: ES a Sa CRCD=0 sant: oe X 82 KS! Kor Koz Yas Yor Kos Klos KK 09« Ko85 Kove X so X ss Kor X CRCD=1 7. ‘SQDT: CD GS ELD CD ETD OD OD 0 0) CD ed EP ED 9 a Fig. 10 3) at SQEN='H’, SQOK, SQDT, S0S1, SQCK Timing Chart S0S1 a pe fr 800K YF" 806K LULL. ND C9 CD C3 6) CI CD CF CI CD ((0 C2 CD CD Cr a CC SQDT: eam ETD CDC) C2 CDC) CO C9 C9 5D (9 5 CD CD Or GRECIAN CC Fig. 11 Comment: if the SQOK of the subcode Q data is “‘H”, subcode data is outputed to SQDT according to subcode, and it is “L” is outputed. 4) VCOI, SDAT, SBCK Timing Chart Ts veo: SUF LLL Lk ~ PBFR: 1 on 6 1 2 3 4 A 6 7 8 cox —_F LILLE LY LP Lr Ly lL = ©) pn pee : pe soat:_ X_@) Xa Xa X s Xr Xu Xv Kw XY Fig, 12 a) after PBFR becomes falling edge SBCK become “‘L" during about 10 sec. b) If SOS1.is “L”, subcode P is outputed and “H", SO, S1 is outputed. c) If a pefipd of VCO! is “T"’, the width of © is 4T~6T. d) If the pulse inputed to SBCK terminal be over seven, subcode data (P, Q, R, S, T, U, V, W) is repeated. OO & SAMSUNG “se Electronics

ECC In case the data on the disk is damaged, ECC block corrects the damaged data. C1 (32,28) and C2 (28,24) error is corrected by CIRC. ECC is performed by the unit of one symbol of eight bit. C1 pointer is generated for C1 correction, and C2 pointer is generated for C2 correction. C1, C2 send the error informa- tion of the DATA which ECC is performed. The data which don't be corrected is showed the error data by outputing C2 FIAG. ‘The C2FL signal is handled in the interpolator by using the signal of C2F1 and C2F2. | CIF | CiF2 C1C2 Error Condition C2F1 | C2F2 C2FL ° fe} No error fe} | oO ° ° 1 Single error correction ° t ° fl | ° Double error correction 1 fo) o | 1 ' Irretrievable error ' | 1 1 C1F1, C1F2: the error correct condition is outputed by C1 decoder. C2F1, C2F2: the error correct condition is outputed by C2 decoder. C2FL : In case that error can't be corrected by C2 decoder becomes ‘H’ and the reverse case becomes ‘L’ 8. 16K SRAM SRAM Adress Generator and 16KSAM is built in DSP to write the data in the RAM, to read/write the data at the ECC processing, and to output the data to D/A converter after the EFM data from the disk is demodulated. The SRAM (PAD 59) must be ‘L’ when the 16KSRAM is. operating. 1) Address Generation Priority Control These are processed at the same time that write when EFM is demodulated, R/W at the ECC Processing at D/A con- verter read, the priority must be controlled. When these signals are required simultainiously the processing priority is that the first is D/A converter read, the second is EFM write, the third is ECC R/W. eeeeeSeSeeeeeeeSeeSSSSSSSSSSS & SAMSUNG ‘oa Electronics

KS9210 CMOS INTEGRATED CIRCUIT CMOS INTEGRATED CIRCUIT 2) EFM demodulation data write When write requirement signal is send to SRAM ADDRESS. GENERATOR, as the demodulated EFM DATA must be written in the SRAM, the Priority is controlled and the enable ‘signal is inputed to EFM block and the generated address is send to SRAM INTERFACE circuit. The generated adress is a data considering deinterleave thirty-two addresses are generated in the one frame. A, At the time being used 16K SRAM (EFM & ECC. write) * DB1~ DB8 is ‘H” * AD1~AD11 is Hi-Z © CE, WE don't care aucke = WU L LLL LI PLL nes: 7 1 1 ' t t INWE 1 U - l t Lt ! Lt t | i | 1 ! | i] i i il I aot ~1AD11 ' 1 ' | ! i} L | | \\ | 1081~ 1088 =2 SCD OD CD OD Fig. 13 3) ECC DATA R/W At C1, C2 ECC processing, one hundred and twinty-nine address signal is generated during one frame processing as sixty-four PCM Datas and sixty-five pointer must be R/W, at ECC processing, write function is equal to 2). The following is at READ. A. The reading time at 16K SRAM. wo TUL $ LLL LLL, nes TT 1081 ~ 1088: 2 GED @ GED © GED @ Gay 0 Gay 2 GD 0 oc Data Bus Nae ees — Fig, 14 a & SAMSUNG 426 Electronics

4) D/A Converter Read . Thirty-six read enable signals are generated during one frame as six sampling data and twelve C2 pointer data must be read in each L, R-CH. The timing chart is equal to R/W block of ECC data tor D/A converter read. In conclusion, one hundred and seventy-nine of R/W processing action are requerd. 5) Address Generator ‘The Data interleaved at encode is deinterleaved at decode. One hundred and eight frame data is needed for getting one frame of PCM data in CDP format. Two counter is used to get data mached to CDP Format. That is, write base counter is used to write the EFM demodulated data in the SRAM, and read base counter is used to read the data in RAM. 6) JITTER MARGIN The EFM demodulated DATA is disturbed by rolling of the disk, or instability of servo system when the data is written in the SRAM. The data is distructed by time limit when the value of R/W base counter exceed +5 FRAME because of SRAM SIZE. The JITTER MARGIN became less than +4 frame when the value of R/W base counter exceed +5 FRAME be due to the value of READ BASE COUNTER is loaded to the value of WRITE BASE COUNTER compulsorily. The value of READ BASE COUNTER is loaded to the value of WRITE BASE COUNTER compulsarily when the difference of READ/WRITE BASE COUNTER exceed +4 frame, ‘H’ signal is outputed to JIT during a period of PBER. 9. interpolator Mute 1) Interpolator If the BURST ERROR occur on the disk although ECC process is performed, THE data can't be corrected, according to circumstance. The data is corrected by using C2 pointer of ECC in the interpolator block. The PCM data is inputed to DATA BUS and the priority is that the first is 8 BIT C2 pointer the second is lower 8 bit, the third is upper 8 bit against each L. R-CH. When DA FLAG is ‘H’ takes pre hold, and in case that ‘single error occur ‘the average compensation method is performed with the value of PCM DATA, against a period of CHCK, when CHCK is 'L’, RCH DATA is outputed and when CHCK is ‘H’, L-CH DATA is outputed the timing chart of interpolator block refer to (Figure 16) A a NI —.~H -G6 I a Ct ia TT | C2 POINTER: | Ss B oft : average compensation F=E=D: Pre hold compensation o-F ae : average compensation Fig. 15 en & SAMSUNG “ Electronics

KS9210 CMOS INTEGRATED CIRCUIT seem MOS INTEGRATED CIRCUIT 2) Mute, Attenuation The audio data is muted or reduced by the ATTN signal is muting terminal and CNTL-S Reg. The mute have two kind of muting, one is ZERO cross muting, the other is muting. a) Zero cross muting ‘The audio data is muted, after ZCMT of CNTL-Z eg goes to ‘H’, and in case that mute is 'H’ and the upper 6 bit of audio data became all ‘L’ or 'H’. b) Muting The audio data is muted in case that the ECMT of CNTL-Z Reg. is ‘L’ and mute terminal is ‘H’. ) Attenuation The signal reduction is occured by ATTM of CNTL-S reg and mute signal as following. ATTM MUTE ° ° | 0dB ° | 1 | -=d8 i) fo} -12d8 . i) _ L _ i _ L ia 1208 ee & SAMSUNG “ar Electronics

KS9210 CMOS INTEGRATED CIRCUIT zo F At fF . el 1g e 6s) i 3 a 3 ] Es Fy 2 & 2 a) fo & 3 le] 3 D Ss (=) ° Jd f] & 2 if BB Hy a Bg 2 = s > &) 4 (2) . g &) a Fa iD} 2 by E 3} & SAMSUNG “se Electronics

KS9210 CMOS INTEGRATED CIRCUIT --———ooo 10. Digital Filter The FIR (finite impulse response) digital filter is build in KS9210. 1) Block diagram CHCK WoCK tek SIP & PIS DIGITAL FILTER | a 7 | CONVERTER CONTROLLER nn MULTIPLIER | nn OVER FLOW

576 REGISTER ADDER

te | (COEFFICIENT) UMITER’ 16 DATA Fig. 17 2) Specification PASS BAND * Ripple up to 18 KHz band $0.07 Max * Reduction of 1 KHz in 20 KHz | 0.55 max FILTER * Reduction of 1 KHz in 44.1 + 1 KHz [9148 Min | BAND * Reduction of 1 KHz in 44.15 KHz 60 d8 Min * Reduction of 1 KHz in 44.1 10 KHz | 44.48 Min | * Reduction of 1 KHz in 44.14 20 KHz 24 dB Min | | * ~30dB frequency range of 1 KHz 44.1420 KHz ! | ‘* —60dB frequency range of 1 KHz 44.146 KHz | ________* S006 Wequeney range oft KHz TSG KHZ a ener & SAMSUNG ‘s Electronics

KS9210 CMOS INTEGRATED CIRCUIT A. RIPPLE GRAPH. SaGe00S000000-~GEne oe rT Sevavenerececti seceuennereenees Sitio er - Pee ya weet tt FE EEEER SEE LETT TTP tt Ti | Piatt} | HH an Fa -18 on _l ia | - | ee | 0 5 . 10 20.7 B. LOW PASS FILTER GRAPH FREQUENCY (KHz) ; CTT TT TTT Titi itt | | PELE PN pital eee eee eee [fi | i || 1b Lp pet pi wl aaesero WAVANS aN | | (0B) r t+} il Sani AT i ,aSnnneee re WP Beeeeeneeeeee seine To Ty | f a. | 4 i po L + + ‘ neni EEE HAH 0 10 20 30 40 444 FREQUENCY (KHz) & SAMSUNG , “0 Electronics

KS9210 CMOS INTEGRATED CIRCUIT 11. CLV Servo The CNTL-C Reg. is selected to control the CLV servo by Data inputed .-Com. The CLV servo action mode is appointed by the data inputed from y-com to control spindle motor in CNTL-C Reg. 1) Forward The terminal condition of output mode is that SMDP is "H", SMSD is "Hi-Z", SMEF is “L", and SMON is “H" 2) Reverse The condition of reverse mode is that SMOP is ‘L', SMSD is ‘Hi-Z’, SMEF is ‘L’, and SMOD is ‘H’. 3) Speed-Mode The spindle motor is controlled roughly by the mode when track jumping or EFM phase is unlocked. If a period of VCO is ‘T’, the pulse width of frame sync is '22T’ In case that the signal detected from EFM signal exceed '22T' by noise on the disk, ... etc., it must be removed, if Not, the right frame sync can't be detected. In these case, the pulse width of EFM signal is detected by the period of XTFR/2 or XTFR/4 and the pulse width of EFM signal is detected by the period of XTFR/16 or XTFR/32, * Peak hold clock is XTFR/2 or XTFR/4, and bottom hold clock is XTFR/16 or XTFR/32. The detected value is used for syncronized frame signal. If syncronized frame signal is less than 24T, the SMPD terminal outputs ‘L’, equal to 22T, outputs ‘Hi-Z’, and more than 23T, outputs ‘H’. Mf the gain signal of CNTL-W Reg. is ‘L’ the output of SMPD terminal is reduced up to - 12 dB. If it is ‘H’, there is no reduction. (refer to figure 7) Output conditions SMSD = Hi-Z, SMEF = ‘L', SMON ='H’ 4) Hi-Speed-Mode The mirror do main of track which havn't pit is duplicated with 20KHz signal to EFM. In this case, servo action be to unstable because the peak value of mirror signal which is longer than original frame syne signal is detected. In Hi-speed mode, by using the 8.4672/256 MHz signal against peak hold and XTFR/16 or XTFRI/G2 signal against bottom hold, the mirror is removed, and hi-speed servo action be to stable. Output is that SMSD. is ‘Hi-Z’, SMEF is ‘L' SMON is ‘H’. 5) Phase-Mode ‘The mode for controls EFM phase. Phase difference between PBFR/r and XTFR/4 is detected when NCLV of CNTL-Z is 'L' and phase difference between Read Base Counter/4 and Write Base Counter/4 is detected when NCLV is ‘HY, and the difference is outputed to SMPD. (refer to figure 8) ‘H' is outputed from falling edge of PBFR during (WPO-278T) x 32 to SMSD terminal and ‘L’ is outputed up to falling edge of next PBFR. (refer to figure 9) 6) XPHSD-Mode The mode for using normal action. The LKFS signal made from frame sync block is to sampling which period is PBFR. If ‘sampling is ‘H', Phase Mode is performed, and if the sampling is eight of ‘L’ continuously, speed mode is Performed automatically. Selecting Peak hold period of speed mode, and bottom hold period and gain of speed/hi-speed mode is determined by CNTL-W Reg. 7) VPMSP-Mode The mode to controls rough servo. Instead of X'tal VCO is used to test EFM pattern. Ifthe center value of VCO is varid the rotation of spindle motor is varied to same direction and VCO is locked easily, 8) STOP The mode for stop spindle motor. Output is that SMDP is ‘L’ SMSD = ‘Hi-Z’ SMEF is ‘L', and SMON is ‘L’ SS & SAMSUNG “ Electronics

KS9210 CMOS INTEGRATED CIRCUIT ee 5 5 = © FF 9 g ® $3 3 3 33 gene a3 zo? PR 8 ' zo s i a \\ 2 1 z —t m = — == I Se 442 & SAMSUNG Electronics

KS9210 CMOS INTEGRATED CIRCUIT (XTFRIB) H 1 (ware) rt it tt it Wor nenennnen re neenenend Lene Sheen poset wn a Fig. 19 The timing chart of SMDP output [-_—an— eee ee eee Ss Ds (a) The timing chart of SMSD output when PBFR is '287T" [21 —_ He ——_ (©) The timing chart of SMDP output when PBFR is '294T’ Fig. 20 The timing chart of SMDP output at phase mode & SAMSUNG “s Electronics

KS9210 CMOS INTEGRATED CIRCUIT ———— 12. Digital Audio Out The data is outputed serially by audio interface format to other digital set. 4) Digital Audio Interface Format for CDP RPE EEE EEE EEEEEEEE \\ 1 re seer _! i | OL: L:CH Format included block sync preamble 1L-191L: L-CH Format included L-CH sync preamble OR- 191R: R-CH format included R-CH syne preamble _ 1 chex — 1 ~ S i ~~ 1 ~ [aoe [emer PEER ——! Fig. 21 CONTROL SIGNAL ) PREAMBLE Use for discrimate the block of data, L and R-CH DATA i | 7 | n ; L-CH SYNC (EXCEPT BLOCK SYNC) 1 | 7 I | 1 | ) | \\ R-CH SYNC ee ee | 7 n 1 | ! iy BLOCK SYNC (L-CH) rm, to tot ——_487 Fig. 22 ee & SAMSUNG “ Electronics

KS9210 CMOS INTEGRATED CIRCUIT b) Control Signal © Validity bit: it is indicated that the error of 16 bit audio data exists, or don’t ® User definable bit: subcode data output a seck ——ULITUTULL Pa SDAT RC SS 0 Fig, 23 ® Channel status bit: Output a high position information of 4 bit of subcode Q indicate the number of channel, pre-emphasis and copy... etc. Indicate CDP-category. sos: —P LL saot [ioe Tio BorvEwPy] Prl rer COU @ Parity Bit: Make even parity. Fig. 24 ee & SAMSUNG us Electronics

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KS9210 specifications and overview.

Summary

CMOS INTEGRATED CIRCUIT

Description

CMOS INTEGRATED CIRCUIT

Source title KS9210 Datasheet(PDF) - Samsung semiconductor

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