KS88C3216

KS88C3216 SAMSUNG | Alldatasheet

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ELECTRONICS 8-Bit CMOS Microcontroller Product Specification OVERVIEW The KS88C3208/3216 single-chip 8-bit microcontroller is fabricated using a highly advanced CMOS process. The KS88C3208/3216 is using a modular design approach and the following peripherals are intergrated with the SAM8 core to make the KS88C3208/3216 microcontroller suitable for being used in color television and other types of screen display applications.

FEATURES

CPU . Watchdog or oscillation On-Screen Display (OSD) + SAMB8 CPU core stabilization function + Video RAM: 240 x 11 bits Memory Timer/Counters + Character generator ROM: * 16-Kbyte internal program One 8-bit timer/counter (TO) 128 x 18 x 12 bits memory prog with three internal c locks or (128 display characters: fixed: + 272-byte general-purpose an external clock, and three 2, variable: 126) register area operating modes; includes + 240 display positions (10 rows Instruction Set capture input module x 24 columns) nstveton * Two general-purpose 8-bit + 12-dot x 18-dot character + 79 instructions timer/counters with interval resolution + IDLE and STOP instructions timer and PWM modes . ? ; added for power-down modes (timers A and B) be aterent crane sizes Instruction Execution Time 12C-Bus Interface Controller a e erat ors d + 750 ns (minimum) with an 8- + Single master bus controller Fone bekeneunt eer an MHz CPU clock + Two pairs of bus interface i Interrupt: n Pp + — Halftone control signal output; erupts pins selectable for individual + 12 interrupt sources with 12 A/D Converter characters vectors + Four analog input pins; 4-bit + Vertical direction fade-in/fade- + Seven interrupt levels resolution out control + Fast interrupt processing for + 7.68-"1s Conversion time (8- + Fringe function select levels MHz CPU clock) + Synchronous polarity selector General I/O Pulse Width Modulation Module for H-sync and V-sync input + Four I/O ports (30 pins total) + 14-bit PWM with 2-channel Oscillator Frequency + 15 bit-programmable pins for output (one open-drain and + 5-MHz to 8-MHz external general I/O one push-pull) crystal oscillator + Ten open-drain pins for up to . Spit pM with 4channel, * Maximum 8-MHz CPU clock 10-volt loads Ow P 4 Operating Temperature Range + Five open-drain pins for up to ° counter and data 25°C °C 5-volt loads capture input pin * = 25C to +85 8-Bit Basic Timer * Frequency: 5.859 kHz to Operating Voltage Range A 23.437kHz with a 6 -MHz + 45V to 55V + Three selectable internal CPU clock clock frequencies Package Type + 42-pin SDIP 4-1 June 1996

Figure 1. KS88C3208/3216 Block Diagram

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER PIN ASSIGNMENTS P2.6/Pwwo CI} 1 LJ 42/0 P2.5/SDA1 P2.7/Pwa1 C]/2 41/1 P2.4/SCLt P3.0/Pwu2 C]/3 40/0 P2.3/SDA0 P3.1/Pwu3 [1/4 39/[] P2.2/SCLO P3.2/Pwmd C/5 38/[] p2.1/ToCK P3.3/PWM5 [1/6 O 37/10 P2.0/To P3.4/TA C]/7 36/1] P1.7/CAPA P3.5/TB C/8 35/C] P1.6 Po.0 /ADCO []|9 34/1 Vpp Po.1 /ADC1 []}10 KS88C3208 33|L] RESET Po.2/ADC2 C]| 11 KS88C3216 32|[7 Xour Po.3 /ADC3 [1] 12 31/0 Xin Vsg Cl}i3 42-PINSDIP 39/9 test poannto Ci]14 PV) 5915 ogcour POS /INT1 [1/15 28/1] Osc Po.6 /INT2 [J] 16 27/10 P1.5/V-syne P07 /INT3 C]} 17 26/[ P1.4/H-syne P1.0 (]18 O 25/1] Vblank p1.1 O19 24/C] Vred P1.2 C]/20 23/L] Vgreen P1.3/OSDHT []/21 22/1 Vblue Figure 2 KS88C3208/3216 Pin Assignment Diagram <I? 4-3 June 1996

Table 1. KS88C3208/3216 Pin Descriptions P0.0-P0.3 can withstand up to 5-volt loads. digital input or n-channel, open-drain output. external interrupt inputs INTO-INT3. which can withstand up to 10-volt loads. output for the 14-bit PWM module. output pins for timers A and B.

activated when 12V is applied. Figure 3. Pin Circuit Type 1 (RESET)

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION ADDRESS SPACES OVERVIEW (DECIMAL) (HEX) The KS88C3208/3216 microcontroller supports two types. 65,535) FFFFH of address space: — Internal program memory (ROM) — Internal register file noros? A 16-bit address bus and an 8-bit K$88C3208/3216 data bus supports program memory and data memory operations. A separate 8-bit address bus and the 8-bit data bus carryaddresses and data 16,383 16-KBYTE SFFFH between the CPU and the register file. PROGRAM MEMORY AREA The KS88C3208 has a 8-Kbyte wee eeeeeee eee -----] 1 EFF and KS88C3216 has a 16-Kbyte 8-KBYTE mask-programmable ROM. An “| external memory interface is not PROGRAM implemented. MEMORY AREA There are 272 general-purpose 255 INTERRUPT FFH data registers in the internal VECTOR AREA register file. These registers can 0 oH serve as either a source or destination address, or as accumulators for data memory Figure 10. KS88C3208/3216 Program Memory Map operations. . oo Instructions can be fetched, or vectors.) The first 256 bytes of the Sixteen 8-bit registers are used data read, from the ROM. The ROM (0H-FFH) are reserved for for CPU and system control. For KS88C3208 has a 8-Kbyte mask- the maximum number of vector peripheral functions, there are 29 programmable program memory addresses. You can allocate control registers, 13 data (OH-1FFFH). KS88C3216 has a unused locations as normal registers. In addition, there is a 16-Kbyte mask-programmable program memory. Be careful, 240-byte area for on-screen program memory (0H-3FFFH). however, to avoid overwriting display (OSD) video RAM. The reset address in the ROM is vector addresses stored in this 0100H. area. PROGRAM MEMORY (ROM) The KS88 interrupt structure can Program memory (ROM) stores support up to 127 vectors. (The Program code or table data. KS88C3208/3216 uses eight June 1996 4-8 <I

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER REGISTER ARCHITECTURE Internal Register File Register Paging Concept As shown in Figure 12, when the The upper 64-byte area of the The addressable area of the CaOOe be or ine id register : internal register file is logically 256-byte register file is logically dress ‘coated on es 0 0. extended to create the set 7 and extended into four 256-byte pages When the Ocal nioble valu eis set 2 address spaces. (pages 0-3). Only page 0, page 1, '0001B' pp is the ‘selected and a small section of page 2 are destination The | ‘bble of The upper 32-byte area of set 1 is used, however, for the standard he Dodie nointer contrals the further divided into two register KS88C3208/3216 implementation. _ ‘he Page pointer controls the banks, called bank 0 and bank 1. source register page destination After a reset, the page pointer addressing: when the lower nibble In addition, the basic 256-byte always points to page 0. The is ‘0000B’, paged is the selected register space of the register page pointer and source register page; when the KS88C3208/3216 is expanded addressing mode restrictions lower nibble is '0001B', page 1 is into separately addressable 256- support register addressing for the source register page. byte pages. Pages 0-2. Following a reset, the page These extensions into separately Register Page Pointer (PP) pointer's source value (lower addressable register sets, banks, The SAMB archi nibble) and destination value and pages are realized by the 12 SAMS arc Recture supports (upper nibble) are always '0000B', combined implementation of: the logical expansion of the automatically selecting page 0 as physical 256-byte register file in both source and destination. To — Select bank instructions (SB0 -—‘UP to 16 separately addressable select page 1 as the source or and SB1) register pages. Page addressing destination register page, you . : is controlled by the register page must modify the register page — Register page pointer (PP) pointer, PP, pit). Only two pointer values accordingly. — Addressing mode restrictions pages are implemented in the Because only page 0 and page 1

9 Bosses 301 6 microcontroller: are used in the iS08G3208/901 6

the total addressable register purpose register space and page values "0O0OB" and ‘OO01B are space is thereby expanded from 1 contains a 240 x 11-bit area for used 256 bytes to 1120 bytes. The the on-screen display (OSD) KS88C3208/3216 can access 579 video ROM registers in this 1120-byte space. . an 49 June 1996

Figure 11. Register Page Pointer (PP)

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER Register Set 1 Working register addressing is a Part of the OSD video RAM is in function of Register addressing page 1, set 2 (COH-EFH), and the ba bntoe crihe beer upper mode (see Section 3, “Addressing other part (QOH-BFH) is in the locations COH-FFH. This area Modes," for more information). page, p Laid eae area To rows be accessed at any time, Register Set 2 recommend using either Register gardless of which page is . ind Indexed mod currently selected. The upper 32-. The same 64-byte physical space ndirect or Indexed mode to byte area of this 64-byte space is that is used for set 1 register address the entire 240-byte video divided into two 32-byte register locations COH-FFH is logically RAM area. banks, called bank 0 and bank 1. duplicated to add another 64 - You use the select register bank bytes. This expanded area of the Prime Register Space instructions, SBO or SB1, to register file is called set 2. The The lower 192 bytes (QOH—-BFH) address one bank or the other. A logical division of set 1 and set 2 of the KS88C3208/3216's two reset operation automatically is maintained by means of 256-byte register pages is called selects bank 0 addressing. addressing mode restrictions: prime register area. Prime While you can access set 1 using registers can be accessed using The lower 32-byte area of set 1 is Register addressing mode only, any of the seven addressing not banked. This area contains 16 you can only use Register Indirect modes. The prime register area bytes for mapped system addressing mode or Indexed on page 0 is immediately registers (DOH-DFH) and a 16- addressing mode to access set 2. addressable following a reset. In byte common area (COH-CFH) order to address registers on for working register addressing. For the KS88C3208/3216, the set page 1 (in the OSD video RAM), 2 address range (COH-FFH) is you must first set the register Registers in set 1 are directly accessible on page 0 and on page page pointer (PP) to the accessible at all times using the 1. Please note, however, that on appropriate source and Register addressing mode. The page 1, set 2 locations FOH-FFH destination values. 16-byte working register area can are not mapped. only be accessed using working register addressing, however.

2 BANK 0 EFH

Figure 12. KS88C3208/3216 Internal Register File

Table 2. KS88C3208/3216 Set 1 Registers Table 3. KS88C3208/3216 Set 1, Bank 0 Registers

Table 3. KS88C3208/3216 Set 1, Bank 0 Registers (Continued) NOTE: Bit 7 and the lower nibble of the ADCON register are read-only. Table 4. KS88C3208/3216 Set 1, Bank 1 Registers

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — Using Load Instructions to Access Write-Only and Read-Only Registers You cannot use the instructions OR (Logical OR), AND (Logical AND), CP (Compare), and LDB (Load Bit) to access write-only or read-only registers. Use load (LD) instructions instead, except for LDB. Here are some examples: Example 1: OR TOCON,#04H ; Invalid use of logical OR instruction! Use a LD instruction instead to manipulate the TOCON register: BITS STOCON.2 ; STOCON is a shadow register for TOCON LD TOCON,STOCON ; Set bit 2 in the TOCON register Example 2: cP PWMCON,#3CH ; Invalid use of the CP instruction! JP EQ,AAA AAA NOP Use a shadow register instead to manipulate the PWMCON register: cP SPWMCON,#3CH ; SPWMCON is a shadow register for PWMCON JP EQ,AAA AAA NOP Example 3: LDB IICCON.0,RO ; Invalid use of the LDB instruction! Use a shadow register instead to load the value into the IICCON register: LDB SIICCON.O,RO ; SIICCON is a shadow register for IICCON LD lICCON,SSIOCON <I? 4-15 June 1996

microcontroller has fourteen same interrupt level, the interrupt interrupt request. Figure 14. program counter and status flags interrupts are triggered either by active, the interrupt priority interrupt's vector address. This control register settings.

1. Interrupt level IRQS is not used in the KS88C3208/3216 interrupt structure.
2. For interrupt levels with two or more vectors, the lowest vector address usually has the highest priority. For
3. The interrupt names in the ‘Identifier’ column are used in this documentation to refer to specific interrupts, as

distinguished from the interrupt source name or the pin at which an external interrupt request arrives. Figure 13. KS88C3208/3216 Interrupt Structure

KS88C3208/3216 are stored in (OH-FFH). Unused ROM in the addresses stored in this area. Figure 14. ROM Vector Address Area

Table 5. KS88C3208/3216 Interrupt Vectors

252 FCH Timer 0 (match/cap) IRQO 1 Vv

250 FAH __| Timer 0 overflow Fo | vif |

212 D4H V-syne IRQ7 Vv

208 DOH (2C-bus IRQ4 v

190 BEH | Timer A ee ee

188 BCH _| Timer B poo

1. Interrupt priorities are identified in inverse order: '0' is highest priority, '1' is the next highest, and so on,
2. _ If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority

level is the PO.5 external interrupt, vector C2H.

INSTRUCTIONS (El, Dl) value of bit 0 in the SYM register. register (IMR). interrupt structure. All interrupts that you use the El and DI Br priority reg} . The system initialization routine SYSTEM-LEVEL INTERRUPT pending flags for each level. Control interrupt processing: control the external interface. execute the DI (Disable Interrupt) — Each interrupt level is enabled plemented. Table 6. Interrupt Control Register Overview Interrupt priority register RW _| Controls the relative processing priorities of the interrupt levels. group B is IRQ2-IRQ4, and group C is IRQ6 and IRQ7.

level and source. The system- (IPR register) (RPO and RP1). level control points in the interrupt | . Figure 15. Interrupt Function Diagram

generated by that peripheral. These registers and their locations are listed in Table 7. Table 7. Interrupt Source Control Registers

and disable interrupt processing KS88C3208/3216). A reset clears to enable interrupt processing. SYM.1-SYM.4 control fast and disable global interrupt purpose. Figure 16. System Mode Register (SYM)

structure, IRQO-IRQ4, IRQ6, and processing for that level is addressing mode. Figure 17. Interrupt Mask Register (IMR)

structure. The IPR register is used only for IPR register priority IRQ1 interrupts. IPR register values are Group A —_IRQO, IRQ1 . lowest vector address usually has control the relative priority of relationships. hardwired.) example, the setting '001B' would priorities of group C interrupts. Figure 18. Interrupt Priority Register (IPR)

REGISTER (IRQ) requested for that level. to OOH. the KS88C3208/3216 interrupt addressing mode. You can read disabled, it will not be serviced. IRQ7). Each bit corresponds to register at any time using bit or be detected by polling IRQ values. that no interrupt is requested and disabled. Figure 19. Interrupt Request Register (IRQ)

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER INTERRUPT PENDING in the corresponding mode or If all of the above conditions are FUNCTION TYPES control register. met, the interrupt request is acknowledged at the end of the Overview Pending conditions for the timer 0 instruction cycle. The CPU then Th fi match/capture interrupt, the I2C initiates an interrupt machine pending bits, Ore type alia bus interrupt, the timer A and cycle that completes the following automatically cleared by hardware timer B interrupts, and the V-sync processing sequence: after the interrupt service routine interrupt must be cleared by the woe is application's service routines. 1. Reset (clear to "0") the is acknowledged and executed. : re The other type must be cleared by interrupt enable bit in the SYM the application program's interrupt INTERRUPT SOURCE POLLING register (SYM.0) to disable all service routine. SEQUENCE subsequent interrupts. ; 2. Save the program counter Each interrupt level has a The interrupt request polling and and status flags to stack. corresponding interrupt request bit servicing sequence is as follows: in the IRQ register that the CPU 3. Branch to the interrupt vector polls for interrupt requests 1. A source generates an to fetch the service routine's . interrupt request by setting . address. Pending Bits Cleared the interrupt request bit to "1". 4. Pass control to the interrupt Automatically by Hardware 2. The CPU polling procedure service routine. For interrupt pending bits that are pemaes pending condition cleared automatically by urce. When the interrupt service routine hardware, interrupt logic sets the 3. The CPU checks the source's is completed, an Interrupt Return corresponding pending bit to "1" interrupt level. instruction (IRET) occurs. The when a request occurs. It then IRET restores the PC and status issues an IRQ pulse to tell the 4 iMlonept arora signal flags and sets SYM.0 to "1", CPU that an interrupt is waiting to ° . allowing the CPU to process the be serviced. The CPU 5. Interrupt logic determines the next interrupt request. acknowledges the interrupt Interrupt's vector address. source, executes the service Thi it GENERATING INTERRUPT routine, and clears the pending bit 6. the sourpe’s pending fag and VECTOR ADDRESSES to "0". This type of pending bit is cleared to "0" (either by . not mapped and cannot, hardware or by software) The interrupt vector area in the therefore, be read or written by . ROM contains the addresses of software. 7. The CPU continues polling for the interrupt service routine that interrupt requests. corresponds to each level in the In the KS88C3208/3216 interrupt interrupt structure. Vectored structure, the timer 0 overflow INTERRUPT SERVICE interrupt processing follows this interrupt , the PO.4—P0.7 external ROUTINES sequence: interrupts, the PWM counter overflow interrupt, and the capture Before an interrupt request can be 1. Push the program counter's A interrupt belong to this category serviced, the following conditions low-byte value to stack. of interrupts whose pending must be met: 2. Push the program counter’s conditions are cleared high-byte value to stack. automatically by hardware. — Interrupt processing must be enabled (El, SYM.0 = "1") 3. Push the FLAGS register Pending Bits Cleared by the — Interrupt level must be values to stack. Service Routine enabled (IMR register) 4. Fetch the service routine's The second type of pending bit high-byte address from the Software. The service routine on ‘evel is currenth 5. Fetch the service routine's must clear the appropriate ‘ rently low-byte address from the pending bit before a return-from- requesting service vector address. interrupt subroutine (IRET) — Interrupt must be enabled at occurs. To do this, a0" must be the interrupt's source written to the pending bit location (peripheral control register)

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION GENERATING INTERRUPT DBH. The IP register names are 3. Write a"1" to the fast interrupt VECTOR ADDRESSES IPH (high byte, 1P15—IP8) and IPL enable bit in the SYM register. (CONTINUED) (low byte, IP7—IP0). 6. Branch to the service routine FAST INTERRUPT Fast Interrupt Service Routine specified by the 16-bit vector PROCESSING When an interrupt occurs in the address. level selected for fast interrupt The feature called fast interrupt processing, the following events. NOTE processing lets designated occur: interrupts be completed in A 16-bit vector address approximately six clock cycles 1. The contents of the instruction always begins at an even- instead of the usual 22 clock pointer and the PC are numbered ROM location cycles. Bit 1 of the system mode swapped. from OOH-FFH. register, SYM.1, enables fast 2. The FLAGS register values interrupt processing while SYM.2— are written to the dedicated NESTING OF VECTORED SYM4 are sed 'o Select a FLAGS ' register. specific level for fast processing. INTERRUPTS P 9 3. The fast interrupt status bit in You can nest a higher priority Two other system registers the FLAGS register is set. interrupt request while a lower support fast interrupts: 4. The interrupt is serviced. ese this you is being serviced. — The instruction pointer (IP) 5. Assuming that the fast steps: , holds the starting address of interrupt status bit is set, , the service routine (and is when the fast interrupt service 1. Push the current 8-bit later used to swap the routine ends, the instruction interrupt mask register (IMR) program counter values), and pointer and PC values are value to the stack (PUSH — When a fast interrupt occurs, swapped back. IMR). the contents of the FLAGS 6. The content of FLAGS’ 2. Load the IMR register with a register is stored in an (FLAGS prime) is copied new mask to enable the unmapped, dedicated register automatically back into the higher priority interrupt only. called FLAGS' (FLAGS FLAGS register. 3. Execute an El instruction to prime). 7. The fast interrupt status bit in enable interrupt processing (a FLAGS is cleared higher priority interrupt will be NOTE automatically. processed if it occurs). For the KS88C3208/3216 4. When the lower-priority microcontroller, the Programming Guidelines interrupt service routine ends, service routine for any Remember that the only way to restore the IMR to its original one of the seven interrupt enable or disable a fast interrupt value by returning the uals (ROO TRO, IRQ6, is to set or clear the fast interrupt previous mask from the stack or IRQ7) can be enable bit in the SYM register (POP IMR). interont. as a fast (SYM.1), respectively. Executing 7 an El or DI instruction affects only 5. Exeoute an IRET. normal interrupt processing. . Procedure for Initiating Fast Depending on the application, you Interrupts Also, if you use fast interrupts, may be able to simplify this To initiate fast int " remember to load the IP with a procedure to some extent. O Initiate i? lo M thes teps: new start address when the fast INSTRUCTION POINTER (IP Processing, follow these steps: interrupt service routine ends. ) 1. Load the start address ofthe {0886 fee t the programming The instruction pointer (IP) is used service routine into the : by all KS88-series instruction pointer. microcontrollers to control optional 2. Load the level number into the high-speed interrupt processing fast interrupt select field. called fast interrupts. The IP consists of register pair DAH and June 1996 4-28 eo ANSUN Gell

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER tS” PROGRAMMING TIP — Programming Level IRQO as a Fast Interrupt This example shows you how to program fast interrupt processing for a select interrupt level — in this case, for the timer 0 (capture) interrupt, INTO: LD TOCON,#52H ; Disable TOOVF interrupt ; Enable TO interrupt ; Capture mode; trigger on rising signal edges ; Select fosc /256 as TO clock source LD P2CONL #02H ; Set P2.0 to capture input mode LDW IPH,#TO_INT ; IPH <— high byte of interrupt service routine ; IPL <— low byte of interrupt service routine LD SYM,#02H ; Enable fast interrupt processing ; Select IRQO for fast service El ; Enable interrupts FAST_RET: ; IP <— Address of TO_INT (again) TO_INT: (Fast service routine executes) LD TOCON,#52H ; Clear TOINT interrupt pending bit JP T,FAST_RET AM ELECTRONICS 4-29 June 1996

resonator may range from 0.5 . The Xin and Xour pins connect . Figure 20. Main Oscillator Circuit

follows: by a reset or by an interrupt.

1. An external interrupt (with RC-delay noise filter) can be used to

: type includes INTO-INT3, CAPA, TOINT, and VSYNC.

1. For the KS88C3208/3216, the CLKCON signature code

subsystem clock is implemented). Figure 21. System Clock Circuit Diagram

CaN a ocated rier ‘ at interrupt can be used to trigger a fosc/8. value: non-divided, 2, 8, or 16 and the fosc/16 (the slowest the clock signature code is '000B'. Figure 22. System Clock Control Register (CLKCON)

The L-C f has th settings in the CHACON register. 1e L-C oscillator circuit has the , . Figure 23. L-C Oscillator Circuit for OSD

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION SYSTEM RESET OVERVIEW — Allinterrupts are disabled. settings to the basic timer control register, BTCON, During a power-on reset, the — The watchdog function (basic betore oeein Sto hen timer) is enabled. 9 Stop voltage at Vpp is High level and . mode. the RESET pin is forced to Low — Ports 0, 2, and 3 are set to n- level. The RESET signal is input channel, open-drain output through a Schmitt trigger circuit mode; port 2 pull-up resistors Also, you if you do not a p - ‘ want to use the basic where it is then synchronized with are disabled. timer watchdog function re te gs the — Port 1 is set to input mode (which causes a system operating stata io. a known (including multiplexed inputs reset if a basic timer Pp 19 Ss. for H-syne, Y-syne, and counter overflow occurs), The RESET pin must be held to capture A). you can disable it by Low level for a minimum time — Peripheral control and data writing eer oteON interval after the power supply registers are disabled and upper nibble o! : comes within tolerance in order to reset to their initial control allow time for internal CPU clock values. HARDWARE RESET VALUES oscillation to stabilize. The _ i minimum required oscillation he program Counters set Tables 8-1 through 8- list the stabilization time for a reset is address, 0100H reset values for CPU and system (millisecond. , . ©registers, peripheral control — When the programmed registers, and peripheral data When a reset occurs during oscillation stabilization time registers following a reset normal operation (that is, when interval has elapsed, the operation. The following notation Vpp and RESET are High level), instruction stored in ROM is used to represent reset values: the RESET pin is forced Low and location 0100H (and 0101H) qe ape the reset operation starts. All is fetched and executed. — At" ora“0" shows the reset system and peripheral control bit value as logic one or logic registers are set to their default NOTE Zero, respectively. hardware reset values (see Table — An‘x' means that the bit value 8-1). In summary, the following You can program the _ is undefined after a reset. sequence of events occurs during duration of the oscillation . ; a reset operation: stabilization interval by — Adash (‘—) means that the bit making the appropriate is either not used or not mapped. June 1996 4-34 <a?

Table 8. Set 1 Register Values After a Reset accidentally written to "1" by software, a system malfunction may occur.

Table 9. Set 1, Bank 0 Register Values After a Reset

Table 10. Set 1, Bank 1 Register Values After a Reset Table 11. Page 1 Video RAM Register Values After a Reset

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION POWER-DOWN MODES STOP MODE structure that meet this peripherals except the OSD block requirement are INTO-INT3 and the A/D converter. Port pins Stop mode is invoked by the (P0.4-P0.7), CAPA, TO, and V- retain the mode (input or output) instruction STOP (opcode 7FH). sync. Which interrupt you can use they had at the time Idle mode In Stop mode, the operation of the to release Stop mode in a given was entered. CPU and all peripherals is halted. situation depends on the That is, the on-chip main oscillator microcontroller's current internal There are two ways to release stops and the supply current is operating mode. Idle mode: reduced to less than 5,1A. All system functions stop when the Note that when Stop mode is 1. Execute a reset. All system clock "freezes," but data stored in released by an external interrupt, and peripheral control the internal register file is the current values in system and registers are reset to their retained. Stop mode can be peripheral control registers are not default values and the released in one of two ways: by a changed. When you use an contents of all data registers RESET signal or by an external interrupt to release Stop mode, are retained. The reset interrupt. the CLKCON.3 and CLKCON.4 automatically selects a slow a register values remain clock (1/16) because Using RESET to Release Stop unchanged, and the currently CLKCON.3 and CLKCON.4 Mode selected clock value is used. if are cleared to ‘00B'. i i you use an external interrupt for interrupts are masked, a reset Reger saralosce owner righ Stop mode release, you can also is the only way to release Idle level). All system and peripheral Program the duration of the mode. control registers are reset to their oscillation stabilization interval. To 2. Activate any enabled default values and the contents of do this, you must make the interrupt, causing Idle mode to all data registers are retained. A appropriate control and clock be released. When you use reset operation automatically settings before entering Stop an interrupt to release Idle selects a slow clock (1/16) mode. mode, the CLKCON.3 and because CLKCON.3 and f . . CLKCON.4 register values CLKCON.4 are cleared to ‘00B'. the external intorrupt oh serviced remain unchanged, and the After the programmed oscillation when F | ‘Op mor he RET te currently selected clock value stabilization interval has elapsed, tho wen ‘allowing the IRET from is used. The interrupt is then the CPU starts the system the service routine, the instruction serviced. When the return- Ninartinee . ediately following the one that initialization routine by fetching mm as from-interrupt (IRET) occurs, the address stored in ROM initiated Stop mode is executed. the instruction immediately location 0100H. IDLE MODE following the one that initiated Using an External Interrupt to ale mode is executed. Idle mode is invoked by the NOTE Release Stop Mode instruction IDLE (opoode 6FH). In f | Only external interrupts with an Idle mode, CPU operations are On pathos ole th ‘ie. be RC-delay noise filter circuit can be halted while select peripherals rele ‘0 release Stop mode. To used to release Stop mode. The remain active. During Idle mode, release Idle mode, you can use . . " : her type of interrupt (internal or external interrupts in the the internal clock signal is gated om f KS88C3208/321 6 interrupt Off to the CPU and to all external). June 1996 4-38 <I

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — Initial Settings for Address Space, Vectors, and Peripherals The following sample program shows you recommended initial settings for the KS88C3208/3216 address space, interrupt vectors, and peripheral functions. Program comments guide you through the required steps: OSD_REG EQU OC8H ; OSD working register area osd_fig equ 8 dsp_typ equ 9 VRAMAD EQU OCH WORK1 EQU OBH ; General-purpose area WORK2 EQU OAH ; General-purpose area REMOCON EQU 3FH ; CAPA data save register ORG 00H DW PWM_OVF ; PWM counter overflow vector DW CAPA_INT ; Capture A interrupt ORG OBCH DW TIMERB_INT ; Timer B interrupt DW TIMERA_INT ; Timer A interrupt ORG OCOH DW Po4_INT ; P0.4 external interrupt DW POS_INT ; P0.5 external interrupt DW Po6_INT ; P0.6 external interrupt DW PO7_INT ; P0.7 external interrupt ORG ODOH DW IIC_INT ; lIC-bus interrupt ORG 0D4H DW V_SYNC_INT ; V-sync interrupt ORG OFAH DW TIMERO_OVF ; Timer 0 overflow interrupt DW TIMERO_INT ; Timer 0 interrupt ORG 0100H START DI ; Disable all interrupts LD BTCON,#0AAH ; Disable the watchdog timer LD CLKCON,#98H ; Non-divided clock CLR SYM ; Disable global and fast interrupts CLR SPL ; Stack pointer low byte <— "0" ; Stack area will start at OFFH SBI ; Select bank 1 (Continued on next page) PS AM SUNG 4-39 June 1996

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION [3° PROGRAMMING TIP — Initial Settings for Address Space, Vectors, and Peripherals (Continued) LD HTCON,#0AH ; Enable V-sync interrupt LD DSPCON,#0A0H ; Disable OSD logic SBO ; Select bank 0 LD PWMCON,#0E9H ; Prescaler — 4 ; Enable PWM counter ; Disable PWM overflow interrupt ; Enable capture A interrupt LD IPR,#0AEH ; Interrupt priority settings LD IMR,#0C8H ; Enable level 3, 6, and 7 interrupts LD POCONH,#00H ; Output mode LD POCONL,#0FFH ; ADC input mode LD P1CONH,#0FFH ; Output mode LD P1CONL,#00H ; Input mode LD P2CONH,#00H ; Open-drain output mode LD P2CONL,#00H ; Open-drain output mode LD P2PUR,#02H ; Enable pull-up resistor at P2.1 LD P3CONH,#00H ; Open-drain output mode LD P3CONL ,#00H ; Open-drain output mode LD TACON,#54H ; Prescaler — 6 ; Clock source <— CPU clock / 1000 ; Enable timer A interrupt ; Interval timer mode LD TADATA,#03H ; 4-millisecond interrupt El MAIN NOP NOP NOP JP T,MAIN ; Jump MAIN CAPA_INT: ; CAPA interrupt service PUSH PP ; Save page pointer to stack PUSH RPO ; Save register pointer 0 to stack PUSH RP1 ; Save register pointer 1 to stack LD REMOCON,CAPA ; REMOCON < CAPA data POP RP1 ; Restore register pointer 1 value POP RPO ; Restore register pointer 0 value POP PP ; Restore page pointer value IRET ; Return from interrupt service routine (Continued on next page) June 1996 4-40 <I

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — Initial Settings for Address Space, Vectors, and Peripherals (Continued) TIMERA_INT PUSH PP ; TIMER_A interrupt service PUSH RPO PUSH RP4 LD TACON,#54H ; Clear pending bit POP RP1 POP RPO POP PP IRET ; Return from interrupt service routine V_SYNC_INT PUSH PP ; V_SYNC interrupt service PUSH RPO PUSH RP1 LD TACON,#54H ; Clear pending bit POP RP1 POP RPO POP PP IRET ; Return from interrupt service routine PWM_OVF: ; PWM counter overflow interrupt TIMERB_INT: ; Timer B interrupt P04_INT: ; P0.4 external interrupt POS_INT: ; P0.5 external interrupt PO6_INT: ; P0.6 external interrupt PO7_INT: ; P0.7 external interrupt lIC_INT: ; |IC-bus interrupt TIMERO_INT: ; Timer 0 interrupt TIMERO_OVF: ; Timer 0 overflow interrupt IRET ; Return from interrupt service routine

Table 12. KS88C3208/3216 Port Configuration Overview withstand up to 5 V and the upper nibble pins up to 10 V. for alternative use as external interrupt inputs.

3 General 6-bit I/O port, configurable for digital input or Bit programmable

Table 13. Port Data Register Summary ‘FFH' to close n-channel, open-drain outputs. See Section 8, "RESET and Power-Down," for details. Figure 24. Port Data Register Format

PORTO mode. The pin circuit assigned to INTO-INTS, respectively. (P0.4—P0.7) are assigned different Each pin has an individually or falling signal edges. ‘00H’, configuring the port 0 pins You can alternatively use P0.4— input function.

1 Input mode, interrupt on falling edge

Figure 25. Port 0 High-Byte Control Register (POCONH)

1 ADC input mode (digital input disabled)

Figure 26. Port 0 Low-Byte Control Register, (POCONL)

PORT 1 A reset clears each control normal/multiplexed output. reading the port 1 data register, otherwise to normal input mode. capture A (CAPA) input for P1.7. controlled by the P1CONH and the P1 data register value to P1.3. Figure 27. Port 1 High-Byte Control Register (P1CONH)

01 Input mode; pull-up resistor enabled

Figure 28. Port 1 Low-Byte Control Register (P1CONL)

P2 (E2H, set 1, bank 0). The mode. This setting does not invalid setting.

• ate mode. The lower byte pins pt y.

Figure 29. Port 2 High-Byte Control Register (P2CONH)

01 Push-pull output mode

Figure 30. Port 2 Low-Byte Control Register (P2CONL)

0 Disable pull-up resistor

1 Enable pull-up resistor

Figure 31. Port 2 Pull-Up Resistor Enable Register (P2PUR)

data register, P3 (ESH, set 1, can withstand 10-volt loads. PWM5 output functions.

01 Digital input mode

Figure 32. Port 3 High-Byte Control Register (P3CONH)

Figure 33. Port 3 Low-Byte Control Register (P3CONL)

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION tS” PROGRAMMING TIP — Configuring 1/0 Port Pins to Specification The following sample program shows you how to configure the KS88C3208/3216 I/O ports to specification. The following parameters are given for ports 0, 1, 2, and 3: — Set P0.0 and P0.1 to open-drain output mode — Set P0.2 and P0.3 to ADC input mode — Set P0.4 and PO.5 to input mode with rising edge interrupts — _ Set P0.6 and PO.7 to input mode with falling edge interrupts — Set P1.0—-P1.3 to push-pull output mode — Set P1.4 to H-sync input mode — Set P1.5 to V-sync input mode — Set P1.6 to push-pull output mode — Set P1.7 to CAPA input mode — Set P2.0 and P2.1 to open-drain output mode — Set P2.2-P2.5 to IIC-bus mode — Set P2.6 to open-drain output mode — Set P2.7 to PWM output mode — Set P3.0-P3.5 to open-drain output mode SBO ; Select bank 0 LD POCONH,#0FAH ; P0.4, PO.5 < Input mode; rising edge interrupts ; P0.6, P0.7 <— Input mode; falling edge interrupts LD POCONL,#0FOH ; P0.0, P0.1 < Open-drain output mode ; P0.2, P0.3 <— ADC input mode LD P1CONH,#20H ; P1.4 <— H-sync input mode ; P1.5 <— V-sync input mode ; P1.6 < Push-pull output mode ; P1.7 <— CAPA input mode LD P1CONL,#0AAH ; P1.0-P1.3 <— Push-pull output mode LD P2CONH,#0CFH ; Configure P2.4 and P2.5 as IIC-bus lines ; P2.6 <— Open-drain output mode ; P2.7 <— PWM output mode LD P2CONL,#0FOH ; P2.0, P2.1 <— Open-drain output mode ; Configure P2.2 and P2.3 as IIC-bus lines LD P3CONH,#00H ; P3.4, P3.5 <— Open-drain output mode LD P3CONL,#00H ; P3.0-P3.4 <— Open-drain output mode June 1996 4-52 <I

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — Clearing Port 0 Interrupt Pending Bits This sample program shows you how to clear the interrupt pending bits for port 0. The program parameters are as follows: — Enable only interrupt level 1 (IRQ1) for P0.4—-P0.7 — Set the interrupt priorities as P0.4 > P0.5 > P0.6 > P07 ORG OCOH VECTOR EXT_INT_P04 VECTOR EXT_INT_P0S. VECTOR EXT_INT_P06 VECTOR EXT_INT_PO7 ORG 0100H RESET DI ; Disable all interrupts SBO ; Select bank 0 LD BTCON,#0AAH ; Disable the watchdog timer LD CLKCON,#98H ; Non-divided clock CLR SPL ; Stack pointer low byte <— "0" ; Stack area starts at OFFH LD IMR,#06H ; Enable IRQ1 and IRQ2 interrupts LD IPR,#11H ; IRQ1 > IRQ2 LD POCONH,#0FAH ; P0.4, PO.5 < Input mode; rising edge interrupts ; P0.6, PO.7 <— Input mode; falling edge interrupts LD POCONL ,#0FOH ; P0.0, P0.1 < Open-drain output mode ; P0.2, P0.3 <— ADC input mode SRP #0C0H ; Set register pointer to OCOH El ; Enable interrupts MAIN NOP NOP JP T,MAIN (Continued on next page) <a 4-53 June 1996

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION [3° PROGRAMMING TIP — Clearing Port 0 Interrupt Pending Bits (Continued) EXT_INT_P04: ; P0.4 external interrupt service PUSH PP ; Save page pointer to stack PUSH RPO ; Save register pointer 0 to stack PUSH RP1 ; Save register pointer 1 to stack POP RP1 ; Restore register pointer 1 value POP RPO ; Restore register pointer 0 value POP PP ; Restore page pointer value IRET ; Return from interrupt service routine EXT_INT_P05: ; P0.5 external interrupt service PUSH PP PUSH RPO PUSH RP1 POP RP1 POP RPO POP PP (RET EXT_INT_P06: ; P0.6 external interrupt service PUSH PP PUSH RPO PUSH RP1 POP RP4 POP RPO POP PP IRET EXT_INT_P07: ; PO.7 external interrupt service PUSH PP PUSH RPO PUSH RP1 POP RP1 POP RPO POP PP IRET June 1996 4-54 PS ANSUN Gall

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER BASIC TIMER and TIMER 0 MODULE OVERVIEW by the appropriate TOCON the watchdog timer function. It is register setting: interval timer located in set 1, address D3H, The KS88C3208/3216 output mode, PWM output mode, and is read/write addressable microcontroller have two default and capture input mode. Timer 0 using Register addressing mode timers: an 8-bit basic timer (BT) has the following components: only. and one 8-bit general-purpose timer/counter, called timer 0 (TO). — Clock frequency divider (fosc A reset clears BTCON to ‘00H’. divided by 4096, 256, or 8) This enables the watchdog The basic timer (BT) has two with multiplexer function and selects a basic timer alternative functions: 1) It can be clock frequency of fosc/4096. To used as a watchdog timer to — External clock input pin, TOCK disable the watchdog function, provide an automatic reset — 8-bit counter (TOCNT), 8-bit you must write the signature code mechanism in the event of a comparator, and 8-bit '1010B' to the basic timer register system malfunction, and 2) It can reference data register control bits BTCON.7-BTCON.4. be used to signal the end of the (TODATA) required oscillation stabilization F The 8-bit basic timer counter, interval after a reset or a Stop ~~ VO pin (P2.0/r 0) for capture BTCNT (set 1, bank 0, FDH), can mode release. The components of Pi Pl be cleared during normal the basic timer are: — Timer 0 overflow interrupt operation by writing a "1" to (TOOVF) and match/capture BTCON.1. To clear the frequency — Clock frequency divider (fosc interrupt (TOINT) generation dividers for both the basic timer divided by 4096, 1024, or — Timer 0 control register. input clock and the timer 0 clock 128) with multiplexer TOCON (set 1, D2H, , (unless timer 0 is using an . — 8-bit basic counter, BTCNT read/write) external clock source), you write a (set 1, bank 0, FDH, read- 0 0. only) BASIC TIMER CONTROL — Basic timer control register, REGISTER (BTCON) BTCON (set 1, D3H, . read/write) The basic timer control register, BTCON, is used to select the - - , to clear the Timer 0 (TO) has three operating ree ieee feat frequency modes, one of which is selected dividers, and to enable or disable <n 4-55 June 1996

1010B = Disable watchdog er a . Figure 34. Basic Timer Control Register (BTCON)

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function system reset. In other words, in When bit 4 of the BT counter i normal operating condition the overflows, a signal is generated to programed teenie a reset basic timer overflow loop (a bit 7 indicate that the stabilization by setting the BTCON.7— overflow of the 8-bit BT counter) is interval has elapsed. This allows 1 , always broken by a clear counter the clock signal to be gated on to BTCON.4 bits to any value other . . . . instruction. the CPU so that it can resume than '1010B'. (The '1010B' value 5 disables the watchdog function.) A ; normal operation. In summary, the I An application program can use following events occur when Stop eset clears the BTCON register the basic timer as a watchdo. ean 4 1g mode is released: to ‘00H’, automatically enabling timer to trigger an automatic the watchdog timer function. A system reset in case a 1. During Stop mode a power-on reset also selects the CPU clock : - malfunction occurs. reset or an external interrupt (as determined by the CLKCON occurs to trigger the Stop register setting) divided by 4096 Oscillation Stabilization Interval mode release, and oscillation as the BT clock. Timer Function starts. With every overflow of the basic The basic timer determines the 2. If a power-on reset occurred, timer counter, a reset occurs. oscillation stabilization interval the basic timer counter will During normal operation, this following a reset or after the increase at the rate of overflow-generated reset should release of Stop mode by an fosc/4096. If an external be prevented from occurring. To external interrupt. Whenever a interrupt is used to release do this, the basic timer counter reset or an external interrupt Stop mode, the basic timer value must be cleared by software occurs during Stop mode, the value increased at the rate of (write BTCON.1 to "1") in regular oscillator begins operating. The the preset clock source. intervals. basic timer value then starts a ati increasing at the rate of 3. Clock oscillation stabilization If a system malfunction occurs fosc/4096 (in the case of a reset), interval begins and continues ircuit Noi until bit 4 of the basic timer due to circuit noise or some other or at the rate of the preset clock rfl error condition, the basic timer source (in the case of an external counter overflows. counter Clear operation may not interrupt). 4. When a bit 4 overflow of B be executed and a basic timer TCNT occurs, normal CPU overflow will occur, initiating a Operation resumes. <a 4-57 June 1996

edge, counter running, OVF can occur) a. Figure 35. Timer 0 Control Register (TOCON)

address: FCH. The TOOVF value written to the TO reference at the TO output pin is inverted. Figure 36. Timer 0 Function Diagram (Interval Timer Mode)

interrupts are typically not used. Figure 37. Timer 0 Function Diagram (PWM Mode)

data register. Rising edges or overflow occurs, and TOINT is signal being input at the TO pin. . generated when the counter value (See Figure 39). Figure 38. Timer 0 Function Diagram (Capture Mode)

stabilization interval (until bit 4 of the basic timer counter overflows). Figure 39. Basic Timer and Timer 0 Block Diagram

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER tS” PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to sample specifications: ORG 0100H RESET DI ; Disable all interrupts SBO ; Select bank 0 LD BTCON,#0AAH ; Disable the watchdog timer LD CLKCON,#98H ; Non-divided clock CLR SYM ; Disable global and fast interrupts CLR SPL ; Stack pointer low byte <— "0" ; Stack area starts at OFFH SRP #0C0H ; Set register pointer — OCOH El ; Enable interrupts MAIN LD BTCON,#52H ; Enable the watchdog timer ; Basic timer clock: fosc /4096 ; Clear basic timer counter NOP NOP JP T,MAIN <a 4-63 June 1996

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION 03° PROGRAMMING TIP — Configuring Timer 0 This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. The program givens are as follows: — _ Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds — Oscillation frequency is 6 MHz — General register 60H (page 0) < 60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0 interrupt ORG OFAH ; Timer 0 overflow interrupt VECTOR TOOVER ORG OFCH ; Timer 0 interrupt (match/capture) VECTOR TOINT ORG 0100H RESET DI ; Disable all interrupts SBO ; Select bank 0 LD BTCON,#0AAH ; Disable the watchdog timer LD CLKCON,#98H ; Non-divided clock CLR SYM ; Disable global and fast interrupts CLR SPL ; Stack pointer low byte <— "0" ; Stack area starts at OFFH LD TOCON,#42H ; 01000010B ; Input clock is fogc/256 ; Interval timer mode ; Enable the timer 0 interrupt ; Disable the timer 0 overflow interrupt LD TODATA,#5DH ; Set timer interval to 4 milliseconds SRP #0C0H ; Set register pointer — OCOH El ; Enable interrupts TOINT PUSH PP ; Save page pointer to the stack PUSH RPO ; Save RPO to stack SBO ; Select bank 0 LD PP,#00H ; Page pointer < OOH (select page 0) SRPO #60H ; RPO < 60H INC RO ; RO — RO+1 ADD R2,RO ; R2 — R2+RO0 ADC R3,R2 ; R38 — R38 +R2+Carry ADC R4,RO ; R4 — R4+RO0+Carry cP RO,#32H ; 50 x 4 = 200ms JR ult.NO_200MS_SET BITS R1.2 ; Bit setting (61.2H) (Continued on next page) June 1996 4-64 <I

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER 1S" PROGRAMMING TIP — Configuring Timer 0 (Continued) NO_200MS_SET: LD TOCON,#42H ; Clear pending bit POP RPO ; Restore register pointer 0 value POP PP ; Restore page pointer value TOOVER (RET ; Return from interrupt service routine <I? 4-65 June 1996

interrupt is generated. The enable . both the 8-bit and 14-bit PWM PWM module. Figure 40. PWM Control Register (PWMCON)

the following components: , , . Figure 41. Block Diagram for PWM2-PWM5

data register and 8-bit values. toggles High and Low at a for subsequent clock cycles (see. frequency equal to the counter — The counter is stopped Figure 44).

1. Acounter clock value of 10 MHz is assumed for all timing values.

Figure 42. PWM Waveforms for PWM2—-PWM5

Figure 43. PWM Clock to PWM2—PWM5 Output Delays

pulse width modulation (PWM) order to achieve higher "1". prescaler (an 8-bit counter extended counter value is value. are enabled by the PWMCON - four. upper byte counter. The same 16- | CPU clock. Table 14. PWMO and PWM1 Control and Data Registers

module's base duty cycle. extension register is '1', the 32nd frequencies. Table 15. PWM Output "Stretch" Values for Extension Registers PWMOEX and PWM1EX

1 Not used

0 Not used

Figure 44. Block Diagram for PWM0 and PWM1

1. Set the PWMO frequency to 23.437 kHz

Figure 45. Decision Flowchart for PWMO Programming Tip

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION [3° PROGRAMMING TIP — Programming PWMO to Sample Specifications (Continued) LD PWMCON,#20H ; PS <— 0 (Select 23.437-kHz PWM frequency) ; Enable the PWM counter BTJRF pwm0_dec,R3.0 ; If R3.0 = “O", then jump to pwm0_dec pwm0_inc: ADD R1,#48H ; IfR3.0 = "1", then add 48H to the PWM data JR NC,pwm0_data_end ; If no carry, go to pwm0_data_end INC RO ; RO <— RO+1 JR NZ,pwm0_data_end ; If no overflow, jump to pwm0_data_end for update LD RO,#0FFH ; If overflow, set OFFH to RO LD R1,#0FCH ; Set OFCH to R1 JR T,pwm0_data_end ; Jump to pwm0_data_end unconditionally pwm0_dec: SUB Rt ,#44H ; R3.0 = "0", so subtract 44H from PWM data JP NC,pwm0_data_end ; If no borrow, jump to pwm0_data_end for update SUB RO,#01H ; Decrement RO (RO <— RO - 1) JR NC,pwm0_data_end ; If no borrow, jump to pwm0_data_end CLR RO ; Clear data RO CLR R1 ; Clear data R1 pwm0_data_end: LD PWMOEX,R1 ; Load new value to PWMOEX (bits 2-7) LD PWMO,RO ; Load new value to PWMO June 1996 4-74 <a?

PRODUCT SPECIFICATION *KS88C3208/3216 MICROCONTROLLER CAPTURE UNIT The capture unit captures the The capture interrupt is level 3 upper 8-bit value of the 16-bit (IRQ3) and its vector address is An 8-bit capture unit is integrated counter when a signal edge 02H. Level IRQ3 has two in the PWM module. The capture transition is detected at the CAPA. interrupts: the PWM counter unit detects incoming signal pin. The captured value is then overflow interrupt (vector 00H) edges and can be used to dumped into the capture A data and the capture A interrupt (vector measure the pulse width of the register, also called CAPA, where 02H). The PWM counter overflow incoming signals. PWMCON it can be read. interrupt has higher priority in the register settings control the interrupt structure. capture unit, which has the Using PWMCON.0 and following components: PWMCON.1 settings, you can set Using the capture A interrupt, you edge detection at the CAPA pin can read the contents of the — 8-bit capture data register for rising edges, falling edges, or CAPA data register from edge to (CAPA) for both signal edge types. edge and use the values to _ i calculate the elapsed time eeoaea pin You can also use signal edges at between pulses. . the CAPA pin to generate an — 8-bit capture interrupt (IRQ3, interrupt. PWMCON.3 is the vector 02H) capture A interrupt enable bit. <n 4-75 June 1996

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION [3° PROGRAMMING TIP — Programming the Capture Module to Sample Specifications This example shows you how to program the KS88C3208/3216 capture A module. The sample parameters are as follows: — The main oscillator frequency is 6 MHz — Timer A interrupt occurs every 2 ms — The following waveform is currently being input at the capture (CAP) pin: + t, —— + ty — — The following registers are assigned for program values: Register 70H LDR ; First captured count value Register 71H ; Second captured count value Register 72H ; Third capture count value Register 73H DWNCNT ; Down-counter; decremented by 1 with each timer A interrupt Register 74H CAPCNT ; Capture counter Register 77H FLAG ; Flags June 1996 4-76 <I

1. If4.35ms < ty, tL < 4.6 ms, then set bit zero (LDR) in register 77H; otherwise clear the zero bit (LDR) in
2. If the interval between two rising signal edges (capture trigger) is > 30 ms, disregard the capture setting.

Figures 47 and 48 show decision flowcharts for the sample program. Figure 46. Decision Flowchart (Main Routine and Timer A Interrupt)

Figure 47. Decision Flowchart for Capture A Interrupt

PRODUCT SPECIFICATION *KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — Programming the Capture Module to Sample Specifications (Continued) LDR EQU 0 DWNCNT EQU 3 CAPCNT EQU 4 FLAG EQU 7 CLR PP ; Select page 0 LD P1CONH,#00H ; Set P1.7 to capture input mode LD TACON,#54H ; PS < 5, interval mode ; Enable timer A interrupt LD TADATA,#01H ; 2-ms interval (6 MHz /1000 + 6 + 2 = 0.5 kHz = 2 ms) exec_main: SRPO #70H ; RPO <— 70H cP RDWNCNT,#00H ; Down-counter = "0"? JP NE,MAIN ; If not zero, then jump to MAIN BITR R7.FLAG ; Clear the 'FLAG' LD PWMCON,#0AH ; Enable capture A interrupt ; Trigger interrupt on rising edges MAIN: ; Other job... JP T,exec_main ; For looping TAINT PUSH PP ; Save page pointer PUSH RPO ; Save register pointer 0 SRPO #70H ; RPO <— 70H cP RDWNCNT,#00H ; R83 (down-counter) = "0"? JP EQ,ta_exec : DEC RDWNCNT ; If not zero, then decrement R3 by 1 ta_exec: POP RPO ; Restore register pointer 0 POP PP ; Restore page pointer IRET ; Return from timer A interrupt service routine (Continued on next page) <I? 4-79 June 1996

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION [3° PROGRAMMING TIP — Programming the Capture Module to Sample Specifications (Continued) CAPINT PUSH PP ; Save the page pointer to stack PUSH RPO ; Save register pointer 0 to stack SRPO #70H ; RPO <— 70H INC RCAPCNT ; Increment the capture counter BTJRT cap_one,R7.FLAG ; R7.FLAG — "1", then jump to cap_one BITS R7.FLAG ; Set R7.FLAG CLR RCAPCNT ; Clear capture counter LD RDWNCNT,#0FH ; Down-counter < 15 (for counting 30 ms) LD RO,CAPA ; RO <— 1st captured count value ; CAPA = 0F9H, page 0 LD PWMCON,#0BH ; Enable capture interrupt ; Trigger interrupt on both rising and falling edges cap_end = POP RPO ; Restore the register pointer 0 value POP PP ; Restore the page pointer value IRET ; cap_one cP RCAPCNT,#01H ; CAPCNT = #01H? JP NE,cap_con2 ; LD R1,CAPA ; R1 © 2nd captured count value JR T,cap_end ; cap_con2 CP RCAPCNT,#02H ; CAPCNT = #02H? JP EQ,cap_con3 ; cap_con4 BITR R7.LDR ; Clear the LDR bit in R7 cap_conS LD PWMCON,#00H ; Disable the capture module JR T,cap_end ; cap_con3 LD R2,CAPA ; R2 © 8rd capture count value SUB R2,R1 ; R2 < (8rd capture value — 2nd capture value) SUB R1,RO ; R1 © (2nd capture value — 1st capture value) cP R1,#24H ; 24H = 4.6ms JP UGT,cap_con4 ; If High signal period > 4.6 ms, then go to cap_con4 cP R2,#24H ; JP UGT,cap_con4 ; If Low signal period > 4.6 ms, then go to cap_con4 cP R1,#22H ; 22H = 4.35ms JP ULT,cap_con4 ; If High signal period < 4.35 ms, then go to cap_con4 cP R2,#22H 3 JP ULT,cap_con4 ; If Low signal period < 4.35 ms, then go to cap_con4 BITS R7.LDR ; Set bit ‘LDR’ JP T,cap_con5 ; Jump to cap_cond unconditionally June 1996 4-80 PSANSUN Gl

the time, and other information on INTERNAL OSD CLOCK frequency is 6.5 MHz. For application development using settings in the CHACON register. of the character color. software (filename determined by H-sync input. The. Table 16. OSD Function Block Summary halftone or character background color display control bit, and a 3-bit color code. blank (no-display) data and 7FH is used for a factory test pattern. (blue, green, red, and blank) are output from the OSD block at pins 22-25.

Figure 48. On-Screen Display Function Block Diagram

1. When programming the OSD, writing operations to the OSD video RAM

format. Otherwise, flicker will occur.

1. The contents of the color buffer COLBUF are changed each time the

Figure 49. On-Screen Display Video RAM Data Organization

1. When creating a character background function, the below three conditions

Figure 50. OSD Display Control Register (DSPCON)

recommend that you keep pulses enter a polarity option selected. DSPCON.0 cleared to "0" in order circuit that is controlled by the . displayed character (see Figure display for individual characters. characters. Figure 51. OSD Fringe Display Function

CHARACTER SIZE CONTROL Vertical character size is defined CHACON.4-CHACON.7 to "0". Using the character size control defined by bits 4 and 5. There are to'1111B". select rows (0-9) for the character size character, you would clear 54). fade function (see Figure 53). values listed above are used. Figure 52. OSD Character Size Control Register (CHACON)

Figure 53. OSD Character Sizing Dimensions

The OSD block lets you program the CHACON and FADECON matrix is faded starting with line 0. decrements the matrix line-by-line "1", (FADECON.7 is not used). a horizontal value for the character display matrix. Figure 54. OSD Fade Control Register (FADECON)

Figure 55. Line and Row Addressing Conventions

Figure 56. OSD Fade Function Example: Fade After

Figure 57. OSD Fade Function Example: Fade Before

Figure 62. OSD Display Formatting and Spacing Conventions For inter-row spacing, the desired margin register value) H Stored in the video RAM. written to bits 0-2 of the CLMCON _ Inter-column space = color value into the color buffer. set the top margin at 4 x the top CONTROL REGISTER will, of course, be the same color.

Figure 63. OSD Character Color Buffer Register (COLBUF) color display. Bit 3 in the green colors to produce yellow. haracters in a pleasing g H : and no color appears.

bit 7 setting). The halftone signal .

1. The HTCON.7 setting applies to halftone output only. The active High setting ("0") means

("1"), the normal halftone signal output is High level.

1. The active High setting ("0") for HTCON.6 means that the normal RGB polarity is Low level.

When you select the active Low setting ("1"), the normal RGB polarity is High level. Figure 66. Halftone Signal Control Register (HTCON)

Figure 67. Halftone Control Signal Output Options

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — Writing Character Code and Color Data to the OSD Video RAM This example shows how to write character code and color data to the OSD video RAM. The sample program performs the following operations: 1. Write red character 'A' (code 0A, for example) to the video RAM from address 00H to 77H 2. Write green character 'B' (code OB, for example) to the video RAM from address 78H to OEFH. SBI ; Select bank 1 LD DSPCON,#0F9H ; OSD module on; negative sync trigger is selected LD PP,#11H ; Select OSD video RAM page (page 1) SRPO #0COH ; Select common working register area LD COLBUF #04H ; Load color buffer (red color) CLR RO ; Load starting address (00H) to RO OSDLP1 LD @RO,#0AH ; Write red character A to video RAM address 00H-77H INC RO 3 " cP RO,#77H ; " JP ULE,OSDLP1 : " LD COLBUF ,#02H ; Load green color code (02H) to the color buffer OSDLP2 LD @RO,#0BH ; Write green character B to RAM address 78H-OEFH INC RO 3 " cP RO,#0EFH 3 " JP ULE,OSDLP2 ; " SBO ; Select bank 0 t= PROGRAMMING TIP — OSD Fade Function; Line and Row Counters This example is a continuation of the previous OSD example in which character code and color data were written to the video RAM. Assuming a timer A interrupt interval of 2 milliseconds, the sample program should meet the following specifications: 1. If bit fade (R4.0) is set, then enable the fade function. 2. Interval time between two lines = 20 ms. (The flag INTVAL' is set at 20-ms intervals in the timer A service routine.) 3. Fade direction is ‘fade after’. <I? 4-99 June 1996

Figure 68. Decision Flowchart for Fade Function Programming Tip

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — OSD Fade Function; Line and Row Counters (Continued) ROWCNT EQU 6 LINECNT EQU 7 FADE EQU 0 F_STRT EQU 1 INT_CNT EQU 5 INTVAL EQU 2 SB1 ; Select bank 1 LD PP,#11H ; Select OSD video RAM page (page 1) SRPO #0COH ; RPO <— OCOH (common working register area) BTJRF EXIT1,R4.FADE ; If flag FADE = "0", then jump to EXIT1 BTJRT FAD1,R4.F_STRT ; If F_STRT = "1", then jump to FAD1 BTJRF EXIT,R4.INTVAL ; IFINTVAL = "1", then jump to EXT INC RLINECNT ; Line counter < line counter + 1 BITR R4.INTVAL > INTVAL <— "0" cP. RLINECNT,#13H ; Line counter > 19? JP ULT,FAD2 ; Ifline counter < 19, then jump to FAD2 CLR RLINECNT ; Line counter < "0" INC RROWCNT ; Rowcounter < rowcounter + 1 cP RROWCNT,#0BH ; Rowcounter < 11? JP ULT,FAD2 ; Ifrow < 10, then jump to FAD2 LD R1,#0F1H ; Ifrow > 10, then finish the fade function LD R2,@R1 BITR R2.6 ; Fade disable LD @R1,R2 FAD3 LD DSPCON,#0F9H ; OSD module on JR T,EXIT FAD1 CLR RROWCNT ; Row counter (R6) <— OH CLR RLINECNT ; Line counter (Rn) <— OH BITS R4.F_STRT FAD2 LD R2,CHACON ; R2 — CHACON AND R2,#0FOH ; Clear the fade row address OR R2,RROWCNT ; Load new fade row address to R2 LD CHACON,R2 ; CHACON <— R2 INC Ri ; R1 © OFIH (fade line address) LD R2,RLINECNT ; R2 < new fade line address OR R2,#60H ; Enable fade function, select fade after LD FADECON,R2 JR T,FAD3 EXIT1 BITS R4.F_STRT EXIT SBO ; Select bank 0 (Continued on next page) PS AM SUNG 4-101 June 1996

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION [3° PROGRAMMING TIP — OSD Fade Function; Line and Row Counters (Continued) TAINT PUSH PP PUSH RPO LD PP,#11 ; Select video RAM page (page 1) SRPO #0COH ; RPO <— 0COH INC RINT_CNT ; Interval counter < interval counter + 1 cP RINT_CNT,#0AH. ; Interval counter < 10? (Has 20 ms elapsed?) JP ULE,TA1 ; If yes, then jump to TA1 CLR RINT_CNT ; 20 ms has elapsed, so clear interval counter BITS R4.INTVAL. > INTVAL — "1" TAI NOP POP RPO POP PP IRET 53° PROGRAMMING TIP — Manipulating OSD Character Colors; Halftone Function This example is a continuation of the previous OSD examples. Following the second sample program, red character A is in video RAM address 00H-77H and green character B has been written to addresses 78H-OEFH. The program performs the following additional actions: 1. Change the color of character ‘A’ to white. 2. Change the color of character 'B' to its complementary color. 3. Enable the halftone function for character 'B'. SBi ; Select bank 1 LD PP,#11H ; Select video RAM page (page 1) SRPO #0COH ; RPO < OCOH (common working register area) LD COLBUF,#07H ; Color buffer <— white color code (07H) CLR RO ; FO (video RAM address) < 00H OSDLP1 LD @RO0,#0AH ; Video RAM (OOH-77H) < white ‘A’ INC RO ; " cP RO,#77H ; " JP ULE,OSDLP1 3 " LD R2,COLBUF ; R2 © color buffer (color of character in address 78H) COM R2 ; R2 < (not R2) AND R2,#07H ; Mask out bit 7 through bit 3 of R2 LD COLBUF,R2 ; Color buffer <— complementary color of the character ; in address 78H (Continued on next page) June 1996 4-102 <I

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER tS” PROGRAMMING TIP — Manipulating Character Colors; Halftone Function (Continued) LD DSPCON,#0F9H ; OSD module on; negative sync trigger selected halftone CALL halftone1 ; Halftone signal control halftone1 PUSH PP ; Stack <— PP PUSH RPO ; Stack — RPO PUSH FLAGS ; Save flags to stack SBi ; Select bank 1 LD PP,#11H ; Page 1 selected SRPO #20H ; RPO < 20H (working register area) CLR RO ; RO <— 00H loop_halftone LD HTCON,#02H ; Disable halftone control register ; Enable V-sync interrupt LD DSPCON,#0F9H ; Enable OSD; select negative sync trigger LD R1,@RO ; Video RAM zero address INC RO cP RO,#0EFH ; Video RAM end? JP UGT,end_halftone tm R1,#80H ; Check bit 7 value JR Z,loop_halftone LD HTCON,#0AH ; Enable halftone ; Enable V-sync interrupt LD DSPCON,#0FDH ; Halftone output mode ; Select negative sync trigger ; No line is double size JP tloop_halftone end_halftone POP FLAGS ; Restore flag values from stack POP RPO ; Restore register pointer 0 value POP PP ; Restore page pointer RET ; Return PS AM SUNG 4-103 June 1996

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION [3° PROGRAMMING TIP — OSD Character Size, Fringe, Background Color, and Display Position This example is a continuation of the previous OSD examples. It performs the following additional actions: 1. Change the character size to horizontal x3 and vertical x2. 2. Enable the fringe function. 3. Enable character background color to the complementary color of the character code in address OEFH of the video RAM. 4. Enable the frame background; select the color cyan. 5. Set top margin to 16H, set inter-row spacing to 1H, set left margin to 24 dots, and set inter-column spacing to three (3) dots. SB1 ; Select bank 1 LD PP,#11H ; Select video RAM page (page 1) SRPO #0COH ; Select common working register area LD CHACON, #60H ; Horizontal x3, vertical x2 for character size LD FADECON #00H ; Disable the fade function LD ROWCON,#21H ; Top margin <— 16H, inter-row space <— 1H LD CLMCON,#1BH ; Left margin < 24 dots, inter-column space < 3 dots LD R3,COLBUF ; R38 < color of the character in address OEFH COM R3 ; R38 <— not R3 AND R3,#07H ; Mask out bit 7 through bit 3 of R3 OR R3,#0B8H ; R3 < cyan frame background color LD COLBUF,R3 ; Enable character and frame background color LD DSPCON,#0FBH ; Falling edge sync trigger, fringe function on, OSD on SBO ; Select bank 0 tS PROGRAMMING TIP — Helpful Hints About COLBUF and OSD Character Code 0 When working with the OSD module, please note the somewhat unusual characteristics of the color buffer register (COLBUF) and the OSD character code 0: — The color buffer register, COLBUF (OF7H, set 1, bank 1) provides a somewhat unusual method for manipulating character color data. — OSD character code 0 produces a no-display and no-background condition, regardless of the font coding used. June 1996 4-104 ELECTRONICS

bit conversions for one input elapsed.

• requires a total of 25 clocks to be overwritten.

Figure 69. A/D Converter Functional Block Diagram

11 ADC3

Figure 70. A/D Converter Control Register (ADCON)

1. Select the analog input The ADC module then enters range Vgs to Vref, where VReF

channel by writing the an idle state. = Vpp.

1. Analog data is input within the the ADCON register. each conversion step. The
2. After 24 clocks have elapsed, VOLTAGE LEVELS

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — A/D Converter Noise Level and Sampling Frequency This example shows how to program the A/D converter module to sample specifications. It is assumed that the noise level on the analog channel is relatively low, and that the A/D converter sampling frequency is relatively high. The program performs the following actions: — Given a low noise level and high sampling frequency, load an A/D conversion value to the register RO and set bit 7 in R1. — Enable ADCO. — Disable ADC1-ADC3. ADFLAG EQU 7 CLR PP ; Select page 0 LD ADCON,#00H ; Select the ADCO pin and start conversion NOP ; Allow sufficient wait time for the conversion; NOP ; minimum 25 cycles are required. NOP NOP NOP NOP LD RO,ADCON ; RO <— conversion value AND RO,#0FH ; Need lower nibble only (mask upper nibble) BITS R1.ADFLAG ; Set R1.7 PS AM SUNG 4-107 June 1996

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION [3° PROGRAMMING TIP — A/D Converter Noise Level and Sampling Frequency (Continued) In some systems, the noise level may be quite high or the A/D conversion sampling frequency may be low. In such cases, you could use the following method to filter out noise: Perform each A/D conversion three times, discard the maximum and minimum values that you obtain, and use the median value as the result. The following program code uses this method to perform the same operation as the first A/D converter sample program: — Assume a high noise level and a low sampling frequency. — Use median value of three conversions as the result. — Load an A/D conversion value to the register RO and set bit 7 in R1. ADO EQU 0 AD1 EQU 1 AD2 EQU 2 AVE EQU 0 MIN EQU 1 MAX EQU 2 TEMP EQU 3 ADFLAG EQU 7 CLR PP ; Select page 0 LD RTEMP,#03H ; R3 — 03H ADLOOP LD ADCON,#00H ; Select ADCO pin and start conversion NOP ; Wait minimum 25 cycles for conversion NOP ; NOP ; NOP ; NOP 3 NOP 3 LD RADO,RAD1 ; Save conversion result to RO-R2 LD RAD1,RAD2 ; (first conversion result will be in RO, the second result is ; in R1, and the third result is in R2) LD RAD2,ADCON ; AND RAD2,#0FH ; We only need the lower nibble DJNZ RTEMP,ADLOOP. : Conversion completed three times? If no, return to loop cP RMAX,RMIN ; JP UGE,JAD1 ; If MAX > MIN, jump to JAD1 LD RTEMP,RMIN ; If MAX < MIN, exchange values (MAX <> MIN) LD RMIN,RMAX 3 . LD RMAX,RTEMP 3 " (Continued on next page) June 1996 4-108 <I

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — A/D Converter Noise Level and Sampling Frequency (Continued) JAD1 cP RMAX,RAVE ; JP UGE, JAD2 ; If MAX > AVE, go to JAD2 LD RTEMP,RMAX ; If MAX < AVE, exchange MAX and AVE LD RMAX,RAVE ; " LD RAVE,RTEMP ; " JAD2 cP RMIN,RAVE ; JP ULE,JAD3 ; If MIN < AVE, go to JAD3 LD RTEMP,RMIN ; If MIN > AVE, exchange MIN and AVE LD RMIN,RAVE ; " LD RAVE,RTEMP ; " JAD3 BITS R1.ADFLAG ; Set ADFLAG <I? 4-109 June 1996

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION 12C-BUS INTERFACE OVERVIEW line changes only when the clock 12C-BUS SHIFT REGISTER (IIC) signal on the SCLO/1 line is Low The KS88C3208/3216 level. The data shift register for the I2C- microcontroller include support for bus interface, called 'IIC’, is the |2C-bus interface. Two pairs of A High-to-Low transition of located at EDH in set 1, bank 0. It serial data (SDA) and serial clock SDAO/1 signals a START is read/write addressable. When (SCL) lines are provided to carry condition. A Low-to-High transition —_you read or write the IIC buffer, information between the master of SDAO/1 while SCLO/1 is High the IIC interrupt pending bit and peripherals that are level signals a STOP condition. (IICCON.0) is cleared. After a connected to the bus. START and STOP conditions are reset, all shift register values are always generated by the master. undetermined. The KS88C3208/3216 behave as A 7-bit value in the first incoming a single master and can operate byte after the START condition is 12C-BUS INTERRUPT as a receiver or a transmitter of met determines which slave will serial data to/from slave devices. be selected by the master. The I2C-bus interrupt is assigned Because the KS88-series chip is level IRQ4 in the interrupt the master, it initiates data Every data byte puton the structure. Its vector address is transfers and also generates the SDAO0/1 line must be eight bits in DOH. The enable bit for the 12c- clock signal to permit the transfer. length. The number of bytes that bus interrupt is IICCON.1 The master also terminates each you can send or receive per Software polls the IIC interrupt transfer of data over the I2C-bus. transfer is unrestricted. Data is pending bit IICCON.0 in order to The multi-master and arbitration transferred with the most determine when a receive or functions of the standard I2C-bus significant bit (MSB) first. Each transmit procedure is in-progress are not supported in the byte must be followed by an or has been completed. When the KS88C3208/3216 implementation. acknowledge bit. CPU acknowledges the interrupt request, the interrupt service There are two pairs of serial data |2C-BUS PRESCALER (IICPS) routine must also tear the 8 and clock output PSCLt. The programmable 8-bit prescaler Pending bit, ICCON.0, to "0". Using the IICCON control register, _for the I°C-bus shift clock, IICPS, 12C-BUS CONTROL REGISTER you can select one pair or the is located at EFH in set 1, bank 0. (lICCON) other. This feature gives you To determine the shift clock additional flexibility in supporting frequency (speed), you use this The |2C-bus control register, various types of applications. formula: IICCON, is located at EEH in set SDAO and SDA1 are bi-directional A 1, bank 0. Although the IICCON and SCLO and SCL1 are output- Shift clock frequency = CPU register is read-write addressable, only. When the bus is free, both Clock frequency /16 + two bits are read-only: bit 2 (the lines are at High level. Data on (Prescaler value + 1) last-received bit flag) and bit 6 the SDAO/1 line must remain " the 12C-bus busy status flag). A stable when the clock period is The shift clock may be “stretched (res clears ICCON to Sore High level. The state of the data if'a slow slave device holds the clock for clock synchronization. June 1996 4-110 an .

Figure 71. 12C Bus Control Register (IICCON)

Figure 72. Decision Flowchart for I2C-Bus Programming Tip (Main Routine)

Figure 73. Decision Flowchart for |2C-Bus Programming Tip (2C-Bus Interrupt)

KS88C3208/3216 MICROCONTROLLER PRODUCT SPECIFICATION tS” PROGRAMMING TIP — Programming the I2C-Bus Interface (Continued) SLAVE EQU 0 SUBADDR EQU 1 IICDATA EQU 2 IIC_CON EQU 3 iic_start equ 1 CLR PP ; Select page 0 LD P2CONL,#0FOH ; Set P2.2 and P2.3 to IIC-bus data/clock mode ; SCLo, SDAO mode enable LD P2CONH,#00H ; P2.2 and P2.3 are open-drain outputs ; SCL1, SDA1 mode disable LD IICCON,#02H ; Enable the IIC-bus interrupt exec_main: SRPO #60H ; RPO < 60H cP RIIC_CON,#00H ; Down counter = "0" JP NE,MAIN ; IF not zero, then jump to MAIN BITS RIIC_CON.iic_start ; Set "iic_start” bit LD RSLAVE ,#0A0H ; Slave address <— #0A0H LD RSUBADDR,#10H ; Subaddress <— #10H LD RIICDATA,#20H ; Slave IIC data <— #20H MAIN: ; Other job... JP T,exec_main ; For looping HICINT PUSH PP ; Save the page pointer PUSH RPO ; Save register pointer 0 SBO ; Select bank 0 SRPO #60H ; RPO < 60H cP RIIC_CON,#00H ; R8 (IIC condition code control register) = "#00H"? JP NE, iic_control1 LD IICCON, #1 2H ; IC start condition LD lIC, RSLAVE ; Slave address INC. RIIC_CON end_iicint: RL RIIC_CON end_iicint1: LD IICCON,#02H ; lIC generate condition POP RPO ; Restore register pointer 0 POP PP ; Restore page pointer IRET (Continued on next page) June 1996 4-114 eo ANSUN Gell

PRODUCT SPECIFICATION KS88C3208/3216 MICROCONTROLLER [3° PROGRAMMING TIP — Programming the I2C-Bus Interface (Continued) iic_controlt : cP RIIC_CON,#02H JP NE, iic_control2 LD lIC, RSUBADDR ; Slave sub address JP T,end_iicint iic_control2: cP RIIC_CON,#04H JP NE, iic_control3 LD lIC,RIICDATA ; Slave data JP T,end_iicint iic_control3: LD IICCON,#22H ; IIC stop condition CLR RIIC_CON ; Clear IIC_CON data JP T,end_iicint1 PS AM SUNG 4-115 June 1996

Table 17. Absolute Maximum Ratings Table 18. D.C. Electrical Characteristics

Table 19. D.C. Electrical Characteristics (Continued) NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

Table 20. Input/Output Capacitance Table 21. A.C. Electrical Characteristics

0.8 Vpp

0.2 Vpp

NOTE: The unit tcpy means one CPU clock period. Figure 74. Input Timing Measurement Points for tury and tnr2

Table 22. Data Retention Supply Voltage in Stop Mode

1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2. During the oscillator stabilization wait time (tyarr), all CPU operations must be stopped.

4 VpDDR

Figure 75. Stop Mode Release Timing When Initiated by a Reset

Table 23. Main Oscillator and L-C Oscillator Frequency

0.15 Vpp

Figure 76. Clock Timing Measurement Points for Xin

Table 24. Main Oscillator Clock Stabilization Time

1. The unit tepy is one CPU clock period.
2. Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a

power-on occurs, or when Stop mode is released.

1. The oscillation stabilization interval is determined by the basic timer (BT) input clock setting.

Table 25. A/D Converter Electrical Characteristics

1. Excluding quantization error, absolute accuracy values are within + 1/2 LSB.
2. ‘Conversion time’ is the time required from the moment a conversion operation starts until it ends.
3. The unit tepy means one CPU clock period.

not, however, represent guaranteed operating values. Figure 77. Ippi vs. Frequency

Figure 78. Ipp2 vs. Frequency

Figure 79. Ipp3 vs. Vpp (Stop Mode Current)

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