KS86C6104

KS86C6104 SAMSUNG | Alldatasheet

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KS86C6104/P6104 PRODUCT OVERVIEW 1- 1

1 PRODUCT OVERVIEW

Samsung's SAM87R I family of 8-bit single-chi p CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device . A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included t o support real-time operations. KS86C6104/P6104 MICROCONTROLLER The KS86C6104/P6104 microcontroller with USB function can be used in a wide range of general purpose applications. It is especially suitable for mouse or joystick controller and is available in 20 -pin DIP and 24 -pin SO P package. The KS86C6104/P6104 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM87R I CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The KS86C6104/P6104 has 4 Kbytes of program memory on-chip and 208 bytes of RAM including 16 bytes of working register . Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core: — Two configurable I/O ports (11 pins) — 7 bit-programmable pins for external interrupts — 8-bit timer/counter with two operating modes OTP The KS86C6104 microcontroller is also available in OTP (One Time Programmable) version, KS86P6104. KS86P6104 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The KS86P6104 is comparable to KS86C6104, both in function and in pin configuration.

PRODUCT OVERVIEW KS86C6104/P6104 1- 2

FEATURES

• SAM87RI CPU core Memory
• 4 -Kbyte internal program memory (ROM)
• 208-b yte RAM
• 16 bytes of working register Instruction Set
• 41 instructions
• IDLE and STOP instructions added for power- down modes Instruction Execution Time
• 1. 0 µs at 6 MHz f OSC Interrupts
• 12 interrupt sources with one vector
• One level, one vector interrupt structure Oscillation Circuit Options
• 6 MHz crystal/ceramic oscillator
• External clock source General I/O
• 11 bit-programmable I/O pins Timer/Counter
• One 8-bit basic timer for watchdog function and programmable oscillation stabilization interval generation function
• One 8-bit timer/counter with Compare/Overflow counter USB Serial Bus
• Compatible to USB low speed (1.5 Mbps) device 1.0 specification.
• Serial bus interface engine (SIE) — Packet decoding/generation — CRC generation and checking — NRZI encoding/decoding and bit-stuffing
• Two 8-byte receive/transmit USB buffer Operating Temperature Range
• – 4 0 °C to + 85 °C Operating Voltage Range
• 4. 0 V to 5.25 V Package Types
• 20 -pin DIP
• 24-pin SO P Comparator
• 4-channel mode, 4-bit resolution
• 3-channel mode, external reference low EMI design

KS86C6104/P6104 PRODUCT OVERVIEW 1- 3 BLOCK DIAGRAM I/O PORT AND INTERRUPT CONTROL USB SIE PORT 1/ COMPA- RATOR P0.0/INT0 P0.1/INT0 P0.2/INT0 3.3Vout P1.0/CIN0/SCLK P1.1/CIN1/SDAT P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 P1.6/INT1 P1.7/INT1 TIMER 0 BASIC TIMER OSC RESET TEST X IN X OUT SAM87RI CPU 208-BYTE REGISTER4 -KB ROM PORT 0 Figure 1-1 . Block Diagram

PRODUCT OVERVIEW KS86C6104/P6104 1- 4 PIN ASSIGNMENTS VSS Xout Xin TEST P0.0/INT0 P0.1/INT0 RESET P0.2/INT0 P1.7/INT1 P1.6/INT1 KS86C6104 (TOP VIEW) VDD P1.0/CIN0 P1.1/CIN1 P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 3.3Vout Figure 1-2. Pin Assignment Diagram (20 -Pin DIP Package)

KS86C6104/P6104 PRODUCT OVERVIEW 1- 5 V SS X out X in NC TEST P0.0/INT0 P0.1/INT0 RESET NC P0.2/INT0 P1.7/INT1 P1.6/INT1 KS86C6104 (TOP VIEW) V DD P1.0/CIN0 P1.1/CIN1 NC P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 NC 3.3V out Figure 1-3. Pin Assignment Diagram (24 -Pin SOP Package)

PRODUCT OVERVIEW KS86C6104/P6104 1- 6 PIN DESCRIPTIONS Table 1- 1. KS86C6104/P6104 Pin Descriptions Pin Names Pin Type Pin

Description

P0.0–P0.2 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are individually assignable to input pins by software and are automatically disable for output pins. Port0 can be individually configured as external interrupt inputs . D 5, 6, 8 INT0 P1.0–P1.3 I/O Bit-programmable I/O port for Schmitt trigger input o r push-pull output. Pull-up resistors are individually assignable to input pins by software. Port1.0–1.3 can be configured as comparator input F-8 19–16 CIN0– CIN3 P1.4 -P 1 .7 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. Port1.4–1.7 can be individually configured as external interrupt inputs. D 15, 14, 10, 9 INT 1 D+/D- I/O Only used as USB tranceive/receive port. – 12–11 – 3.3VOUT O Internal regulator 3.3 V output pin for referencing the voltage – 13 – X IN , X OUT – System clock input and output pin (crystal/ceramic oscillator, or external clock source) – 3–2 – INT 0 I External interrupt for bit-programmable port0. D 5, 6, 8 Port0 INT1 I External interrupt for bit-programmable port1 D 9, 10, 14, 15 Port1 RESET I RESET signal input pin. – 7 – TEST I Test signal input pin (for factory use only; must be connected to V SS ) – 4 – V DD – Power input pin – 20 – V SS – V SS is a ground power for CPU core. – 1 –

PRODUCT OVERVIEW KS86C6104/P6104 1- 8 IN/OUT V DD DATA OUTPUT DISABLE PULL-UP ENABLE ANALOG/ EXTERNAL VREF INPUT V DD CIRCUIT TYPE C Figure 1-6 . Pin Circuit Type F-8

KS86C6104/P6104 PRODUCT OVERVIEW 1- 9 CON_B C1 R3 Right Button Button 1 2 3 Left Button Button 1 2 3 V DD V SS X OUT V3.3 KS86P6104 P0.0/INT0 P0.1/INT0 P1.7/INT1 P1.3/CIN3 P1.2/CIN2 Array 4 P0.2/INT0 RESET P1.1/CIN1 P1.0/CIN0 USB Cable X IN Figure 1-7 . USB Mouse Circuit Diagram

PRODUCT OVERVIEW KS86C6104/P6104 1- 10 NOTES

KS86C6104/P6104 ELECTRICAL DATA 1 3- 1 1 3 ELECTRICAL DATA OVERVIEW In this section, the following KS86C6104/P6104 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — I/ O capacitance — A.C. electrical characteristics — Input timing for RESET — Oscillator characteristics — Operating voltage range — Oscillation stabilization time — Clock timing measurement points at X IN — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by a RESET — Stop mode release timing when initiated by an external interrupt — Characteristic curves — Comparator Electrical Characteristics

ELECTRICAL DATA KS86C6104/P6104 1 3- 2 Table 13- 1. Absolute Maximum Ratings (T A = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – – 0.3 to + 6.5 V Input voltage V IN All in ports – 0.3 to V DD + 0.3 V Output voltage V O All o utput ports – 0.3 to V DD + 0.3 V Output current high I OH One I/O pin active – 18 mA All I/O pins active – 60 Output current low I OL One I/O pin active + 30 mA Total pin current for ports 0, 1 + 100 Operating temperature T A – – 40 to +85 °C Storage temperature T STG – – 65 to + 150 °C

KS86C6104/P6104 ELECTRICAL DATA 1 3- 3 Table 13- 2. D.C. Electrical Characteristics (T A = – 4 0 °C to + 85 °C, V DD = 4. 0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit Input highvoltage V IH 1 All input pin s except V IH 2, D+, D– 0.8 V DD – V DD V V IH2 X IN V DD – 0.5 V DD Input low voltage V IL 1 All input pin s except V IL2 , D+, D– – – 0.2 V DD V V IL2 X IN – – 0.4 Output high voltage V OH V DD = 4. 5 V – 5.5 V IOH = – 200 µA All output port s except D+, D– V DD – 1.0 – – V Output low voltage V OL V DD = 4. 5 V – 5.5 V IOL = 2 mA All output ports except D+, D– – – 0.4 V Input high leakage current ILIH 1 V IN = V DD All inputs except I LIH 2 except D+, D– – – 3 µA ILIH2 V IN = V DD X IN , X OUT – – 20 Input low leakage current ILIL 1 V IN = 0 V All inputs except I LIL 2 except D+, D– – – – 3 µA ILIL2 V IN = 0 V X OUT , X IN – – – 20 Output high leakage current ILOH V OUT = V DD All output pin s except D+, D– – – 3 µA Output low leakage current ILOL V OUT = 0 V All output pins except D+, D– – – – 3 µA Pull-up resistors R L1 V IN = 0 V; V DD = 5.0 V, 25 50 100 K Ω R L2 V IN = 0 V ; V DD = 5.0 V, RESET only 100 220 400 Supply current (note) IDD1 Normal operation mode 6 -MHz CPU clock – 6.5 15 mA IDD2 Idle mode; 6 -MHz CPU clock – 4 8 mA IDD3 Stop mode; oscillator stop – 150 300 µA NOTE S : 1. Supply current does not include current drawn through internal pull-up resistors or external output current load. 2. This parameter is guaranteed, but not tested (include D+, D–).

ELECTRICAL DATA KS86C6104/P6104 1 3- 4 Table 13- 3. Input/Output Capacitance (T A = – 4 0 °C to + 85 °C, V DD = 0 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance C IN f = 1 MHz; unmeasured pins are connected to V SS – – 10 pF Output capacitance C OUT I/o capacitance C IO Table 13- 4. A.C. Electrical Characteristics (T A = – 4 0 °C to + 85 °C, V DD = 4. 0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit Noise filter tNF1H , t NF1L P 1 (RC delay) 100 – 200 ns tNF2 RESET only (RC delay) – 800 – RESET input low width tRSL Input 10 – – µs t NF1H

0.2 V DD

0.5 V DD

0.8 V DD

0.5V DD Figure 13- 1. Input Timing for RESET

KS86C6104/P6104 ELECTRICAL DATA 1 3- 5 Table 13- 5. Oscillator Characteristics Oscillator Clock Circuit Test Condition Min Typ Max Unit Main crystal Main ceramic (f OSC ) XIN XOUT Oscillation frequency V DD = 4.0 V – 5.25 V – 6.0 – MHz External clock XIN XOUT Oscillation frequency V DD = 4.0 V – 5.25 V – 6.0 – Table 13- 6. Oscillation Stabilization Time (T A = – 4 0 °C + 85 °C, V DD = 4. 0 V to 5.25 V) Oscillator Test Condition Min Typ Max Unit Main crystal V DD = 4. 5 V to 5.5 V , f OSC > 6.0 MHz – – 10 ms Main ceramic (Oscillation stabilization occurs when V DD is equal to the minimum oscillator voltage range.) Oscillator stabilization wait time tWAIT stop mode release time by a reset – 2 1 6 /f OSC – tWAIT stop mode release time by an interrupt – – – NOTE : The oscillator stabilization wait time, t WAIT , when it is released by an interrupt, is determined by the setting in the basic timer control register, BTCON.

ELECTRICAL DATA KS86C6104/P6104 1 3- 6 X IN tXL tXH 1 / f OSC V DD – 0.5 V 0.4 V Figure 13-2 . Clock Timing Measurement Points at X IN Table 13- 7. Data Retention Supply Voltage in Stop Mode (T A = 0 °C to + 70 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR Stop mode 2.0 – 6 V Data retention supply current IDDDR Stop mode; V DDDR = 2.0 V – – 5 µA

KS86C6104/P6104 ELECTRICAL DATA 1 3- 7 t WAIT V DD RESET EXECUTION OF STOP V DDDR DATA RETENTION MODE STOP MODE INTERNAL RESET IDLE MODE (BASIC TIMER ACTIVE)0.5 V DD NORMAL OPERATING MODE Figure 13-3 . Stop Mode Release Timing When Initiated by a RESET tWAIT VDD EXECUTION OF STOP INSTRUCTION VDDDR DATA RETENTION MODE STOP MODE IDLE MODE (BASIC TIMER ACTIVE)0.8 VDD

0.2 VDD

Figure 13-4 . Stop Mode Release Timing When Initiated by an External Interrupt

ELECTRICAL DATA KS86C6104/P6104 1 3- 8 Table 13- 8. Comparator Electrical Characteristics (T A = – 4 0 °C to + 85 °C, V DD = 4. 0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit Conversion time (1) tCON – – 4 × 2 4 or 4 × 2 7 – F CPU Comparator input voltage V ICN – V SS – V DD V Comparator input impedance R CN – 2 1000 – M Ω Comparator reference voltage V REF – 1.8 – V DD V Comparator input current ICIN V DD = 5 V – 3 – 3 µA Reference input current IREF V DD = 5 V – 3 – 3 µA Comparator block ICOM V DD = 5 .5 V – 1 2 mA current (2) V DD = 4.5 V 0.5 1 mA V DD = 5 V (when power down mode) 100 500 n A NOTES: 1. Conversion time is the time required from the moment a conversion operation starts until it ends. 2. ICOM is an operating current during conversion.

ELECTRICAL DATA KS86C6104/P6104 1 3- 10 NOTES

KS86C6104/P6104 MICROCONTROLLER MECHANICAL DATA 1 4- 1

14 MECHANICAL DATA

This section contains the following information about the device package: — Package dimensions in millimeters — Pad diagram NOTE : Dimensions are in millimeters. 0.51MIN 3.25 ± 0.2 3.30 ± 0.3 5.08MAX 26.40 ± 0.2

26.80 MAX

(1.77) 1.52 ± 0.1 0.46 ± 0.1 20-DIP-300A 6.40 ± 0.2 #1 #10 #20 #11 7.62 0-15 ° 0.25 +0.1 – 0.05 2.54 Figure 1 4- 1. 20 - DIP0300A Package Dimensions

MECHANICAL DATA KS86C6104/P6104 MICROCONTROLLER 1 4- 2 NOTE : Dimensions are in millimeters. 7.50 ± 0.2 0-8° 0.85 ±0.20 9.53 0.15 +0.10 - 0.05

0.10 MAX

0.05MIN 2.30 ± 0.2 2.70MAX 15.34 ± 0.2

15.74 MAX

(0.69) 0.38 ± 0.1 24-SOP-375 10.30 ± 0.3 #1 #12 #24 #13 1.27 Figure 1 4- 2. 2 4- SOP-375 Package Dimensions

KS86C6104/P6104 KS86P6104 OTP 15- 1

15 KS86P6104 OTP

The KS86P6104 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS86C6104 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS86P6104 is fully compatible with the KS86C6104, both in function and in pin configuration. Because of its simple programming requirements, the KS86P6104 is ideal for use as an evaluation chip for the KS86C6104. VSS /VSS Xout Xin TEST/TEST P0.0/INT0 P0.1/INT0 RESET /RESET P0.2/INT0 P1.7/INT1 P1.6/INT1 KS86P6104 (TOP VIEW) VDD/VDD P1.0/CIN0/ SCLK P1.1/CIN1/ SDAT P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 3.3Vout Figure 15-1. KS86P6104 Pin Assignments (20-DIP Package)

KS86P6104 OTP KS86C6104/P6104 15- 2 V SS /V SS X out X in NC TEST /TEST P0.0/INT0 P0.1/INT0 RESET / RESET NC P0.2/INT0 P1.7/INT1 P1.6/INT1 KS86P6104 (TOP VIEW) V DD/ V DD P1.0/CIN0/ SCLK P1.1/CIN1/ SDAT NC P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 NC 3.3V out Figure 15-2. KS86P6104 Pin Assignments (24-SOP Package)

KS86C6104/P6104 KS86P6104 OTP 15- 3 Table 15-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. (20 DIP) I/O Function P1.0 (Pin 18) SDAT 18 I/O Serial Data Pin (Output when reading, Input when writing) Input and Push-pull Output Port can be assigned P1.1 (Pin 19) SCLK 19 I/O Serial Clock Pin (Input Only Pin) TEST V PP (TEST) 4 I 0V : OTP write and test mode 5V : Operating mode RESET RESET 7 I Chip Initialization and EPROM Cell Writing Power Supply Pin (Indicates OTP Mode Entering) When writing 12.5V is applied and when reading. V DD /V SS V DD /V SS 20/1 I Logic Power Supply Pin. Table 15-2. Comparison of KS86P6104 and KS86C6104 Features Characteristic KS86P6104 KS86C6104 Program Memory 4 K byte EPROM 4 K byte mask ROM Operating Voltage (V DD ) 4.0 V to 5.25 V 4.0 V to 5.25 V OTP Programming Mode V DD = 5 V, V PP ( RESET )=12.5V Pin Configuration 20 DIP/24 SOP 20 DIP/24 SOP EPROM Programmability User Program 1 time Programmed at the factory

KS86P6104 OTP KS86C6104/P6104 15- 4 OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the V PP ( RESET ) pin of the KS86P6104, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 14-3 below. Table 15-3. Operating Mode Selection Criteria V DD V PP ( RESET ) REG/ MEM Address (A15-A0) R/W Mode

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE : "0" means Low level; "1" means High level. Table 15-4 . D.C. Electrical Characteristics (T A = – 4 0 °C to + 85 °C, V DD = 4. 0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit Supply Current (note) IDD1 Normal mode;

6 MHz CPU clock

– 6.5 15 mA IDD2 Idle mode; IDD3 Stop mode; oscillator stop 150 300 µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

KS86C6104/P6104 KS86P6104 OTP 15- 5 START Address= First Location V DD =5V, V PP =12.5V x = 0 Program One 1ms Pulse Increment X x = 10 Verify 1 Byte Last Address V DD = V PP = 5 V Compare All Byte Device Passed Increment Address Verify Byte Device Failed PASS FAIL NO FAIL YES FAIL NO Figure 15-3. OTP Programming Algorithm

KS86P6104 OTP KS86C6104/P6104 15- 6 NOTES