KS86C4004

KS86C4004 SAMSUNG | Alldatasheet

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KS86C4004/P4004/C4104/P4104 PRODUCT OVERVIEW 1 - 1

1 PRODUCT OVERVIEW

Samsung's SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit- configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. KS86C4004/C4104 MICROCONTROLLER The KS86C4004/C4104 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM87Ri CPU core. The KS86C4004/C4104 is a versatile microcontroller , with its A/D converter and a zero-crossing detection capability it can be used in a wide range of general purpose applications. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The KS86C4004/C4104 has 4 - Kbytes of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM . Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core: — Four configurable I/O ports (KS86C4004: 2 2 pins , KS86C4104: 16 pins ) — Six interrupt s ources with one vector and one interrupt level — Two 8-bit timer/counter with various operating modes — Analog to digital converter (KS86C4004: 8-bit, 8-channel, KS86C4104: 10-bit, 5-channel) — One zero cross detection module The KS86C4004/C4104 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, PWM, ADC, ZCD and capture functions. KS86C4004 is available in a 30- pin SDIP and a 32-pin SOP package. KS86C4104 is available in a 24-pin SDIP and a 24-pin SOP package. OTP The KS86P4004/P4104 is an OTP (one time programmable) version of the KS86C4004/C4104 microcontroller. The KS86P4004/P4104 has on-chip 4-Kbyte one-time programmable EEPROM instead of masked ROM. The KS86P4004/P4104 is fully compatible with the KS86C4004/C4104, in function, in D.C. electrical characteristics and in pin configuration.

PRODUCT OVERVIEW KS86C4004/P4004/C4 104/P4104 1 - 2

FEATURES

• SAM87Ri CPU core Memory
• 4-Kbyte internal program memory (ROM)
• 208-byte general purpose register area (RAM) Instruction Set
• 41 instructions
• IDLE and STOP instructions added for power-down modes. Instruction Execution Time
• 600 n s at 10 MHz f OSC (minimum) Interrupts
• 6 interrupt sources with one vector and o ne level interrupt structure Oscillation Frequency
• 1 MHz to 10 MHz external crystal oscillator
• Maximum 10 MHz CPU clock
• 4 MHz RC oscillator General I/O
• Four I/O ports (2 2 pins for KS86C4004, 16 pins for KS86C4104 )
• Bit programmable ports A/D Converter
• Eight anal og input pins
• 8-bit conversion resolution (KS86C4004)
• 10-bit conversion resolution (KS86C4104) Timer/Counter
• One 8-bit ba sic timer for watchdog function
• One 8- bit timer/counter wit h three operating modes (10-bit PWM 1ch )
• One 8-bit timer/counter for the zero-crossing detection circuit Zero-Crossing Detection Circuit
• Zero-crossing detection circuit that generates a digital signal in synchronism with an AC signal input Buzzer Frequency Range
• 200 Hz to 20 kHz signal ca n be generated Operating Temperature Range
• – 4 0 °C to + 85 °C Operating Voltage Range
• 2.7 V to 5.5 V OTP Interface Protocol Spec
• Serial OTP Package Types
• 3 0-pin S DIP , 32-pin SOP for KS86C4004/P4004
• 2 4-pin SDIP, 24-pin SOP for KS86C4104/P4104

KS86C4004/P4004/C4104/P4104 PRODUCT OVERVIEW 1 - 3 BLOCK DIAGRAM PORT 0 PORT 2 SAM87RI CPU P0.0-P0.7 4-KB ROM 208-BYTE REGISTER FILE PORT 3 P3.0 - P3.5 / ADC0-ADC5 PORT 1 P1.0 - P1.3 / ZCD,BUZ,T0,CLO P1.0/ ZCD I/O PORT I/O and INTERRUPT CONTROL P2.0-P2.3 / INT0-INT1 / ADC6-ADC7TIMER 0 TIMER 1 ZCD ADC OSC BASIC TIMER ADC0 -ADC7 P1.1/BUZ T0(PWM) X IN X OUT Figure 1 -1 . Block Diagram

PRODUCT OVERVIEW KS86C4004/P4004/C4 104/P4104 1 - 4 PIN ASSIGNMENTS V SS X IN X OUT TEST P0.1 P0.0 RESET P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 A V SS A V ref V DD P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P1.3 / CLO P2.0 / INT0 P2.1 / INT1 P2.2 / ADC6 P2.3 / ADC7 KS86C4004 30-SDIP (Top View) Figure 1 -2 . Pin Assignment Diagram ( 30 -Pin S DIP Package)

KS86C4004/P4004/C4104/P4104 PRODUCT OVERVIEW 1 - 5 V SS X IN X OUT TEST P0.1 P0.0 RESET NC P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 A V SS A V ref V DD P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 NC P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P1.3 / CLO P2.0 / INT0 P2.1 / INT1 P2.2 / ADC6 P2.3 / ADC7 KS86C4004 32-SOP (Top View) Figure 1 -3 . Pin Assignment Diagram ( 32 -Pin SOP Package)

PRODUCT OVERVIEW KS86C4004/P4004/C4 104/P4104 1 - 6 V SS X IN X OUT TEST P0.1 P0.0 RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 V DD P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P2.0 / INT0 A V ref A V SS KS86C4104 24-SDIP (Top View) Figure 1 -4 . Pin Assignment Diagram ( 24 -Pin SDIP Package)

KS86C4004/P4004/C4104/P4104 PRODUCT OVERVIEW 1 - 7 V SS X IN X OUT TEST P0.1 P0.0 RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 V DD P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P2.0 / INT0 AV ref A V SS KS86C4104 24-SOP (Top View) Figure 1 -5 . Pin Assignment Diagram ( 24 -Pin SOP Package)

PRODUCT OVERVIEW KS86C4004/P4004/C4 104/P4104 1 - 8 PIN DESCRIPTIONS Table 1 - 1. KS86C4004/C4104 Pin Descriptions Pin Names Pin Type Pin

Description

P0.0-P0.7 I/O Bit-programmable I/O port for normal input or push-pull, open-drain output. Pull-up resistors are assignable by software. E-2 P1.0-P1.3 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 1 pins can also be used as alternative functions. F D D D ZCD BUZ T0(PWM) CLO P2.0-P2.3 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull , open drain output. Pull up resistors are assignable by software. Port 2 can also be used as external interrupt, A/D input . E E-1 INT0–INT1 ADC6–ADC7 P3.0-P3.5 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 3 pins can also be used as A/D converter input. F ADC0–ADC5 X IN , X OUT – Crystal/ceramic, or RC oscillator signal for system clock. – – INT 0–INT1 I External interrupt input. E P2.0–P2.1 RESET I System RESET signal input pin. B – TEST I Test signal input pin (for factory use only: must be connected to V SS ) – – V DD , V SS – Voltage input pin and ground – – AV REF, A V SS – A/D converter reference voltage input and ground – – ZCD I Zero crossing detector input F P1.0 BUZ O 200 Hz–20 kHz frequency output for buzzer sound D P1.1 T0 I/O Timer 0 capture input or 10-bit PWM output D P1.2 CLO O System clock output port D P1.3 ADC0–ADC7 I A/D converter input F E-1 P3.0–P3.5 P2.2–P2.3

KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA 13 - 1

13 ELECTRICAL DATA

In this section, the following KS86C4004/C4104 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Oscillator characteristics — Oscillation stabilization time — Operating Voltage Range — Schmitt trigger input characteristics — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by a RESET — A/D converter electrical characteristics — Zero-crossing detector — Zero Crossing Waveform Diagram

ELECTRICAL DATA KS86C4004/P4004/C4 104/P4104 13 - 2 Table 1 3- 1. Absolute Maximum Ratings (T A = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – – 0.3 to + 6.5 V Input voltage V I All input ports – 0.3 to V DD + 0.3 V Output v oltage V O All output ports – 0.3 to V DD + 0.3 V Output c urrent I OH One I/O pin active – 18 mA high All I/O pins active – 60 Output current I OL One I/O pin active + 30 mA low Total pin current for ports 1, 2, 3 + 100 Total pin current for ports 0 + 200 Operating temperature T A – – 40 to + 85 °C Storage temperature T STG – – 65 to + 150 °C Table 1 3- 2. DC Electrical Characteristics (T A = – 4 0 °C to + 85 °C, V DD = 2. 7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input high v oltage V IH1 Ports 1,2,3, and RESET V DD = 2.7 to 5.5 V 0. 8 V DD – V DD V V IH2 Port 0 0.7 V DD V IH3 X IN and X OUT V DD –0.1 Input low v oltage V IL1 Ports 1,2,3, and RESET V DD = 2.7 to 5.5 V – – 0.2 V DD V V IL2 Port 0 0.3 V DD V IL3 X IN and X OUT 0.1 Out put high v oltage V OH IOH = – 1 m A ports 0, 1, 2, 3 V DD = 4.5 to 5.5 V V DD – 1.0 – – V Output low v oltage V O L1 IO L = 15 m A port 0 V DD = 4. 5 to 5.5 V – 0.4 2.0 V V O L2 IO L = 4 m A port 1,2,3 V DD = 4. 5 to 5.5 V 0.4 2.0

KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA 13 - 3 Table 1 3- 2. DC Electrical Characteristics (Continued) (T A = – 40 °C to + 85 °C, V DD = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input h igh leakage current ILIH1 All input s except I LIH2 V IN = V DD – – 1 µA ILIH2 X IN , X OUT V IN = V DD 20 Input low leakage current ILIL1 All inputs except ILIL2 and RESET V IN = 0 V – – – 1 µA ILIL2 X IN , X OUT V IN = 0 V – 20 Output h igh leakage c urrent ILOH All outputs V OUT = V DD – – 2 µA Output low leakage c urrent ILOL All outputs V OUT = 0 V – – – 2 µA Pull-up r esistors R P V IN = 0 V Ports 0 – 3 V DD = 5 V 30 47 70 k Ω V DD = 3 V 30 280 350 Supply c urren t IDD1 Run mode

10 MHz CPU clock

V DD = 5 V ± 10% – 7.5 15 mA

8 MHz CPU clock V DD = 3 V ± 10% 3 6

V DD = 5 V ± 10% 2 5 8 MHz CPU clock V DD = 3 V ± 10% 0.7 2.5 IDD3 Stop mode V DD = 5 V ± 10% 0.1 5 µA V DD = 3 V ± 10% NOTE: D.C. electrical values for Supply current (I DD1 to I DD3 ) do not include current drawn through internal pull-up resisters, output port drive current, ZCD and ADC.

ELECTRICAL DATA KS86C4004/P4004/C4 104/P4104 13 - 4 Table 1 3- 3. AC Electrical Characteristics (T A = – 20 °C to + 85 °C, V DD = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Interrupt input high, low width tINTH , tINTL P ort 2 V DD = 5V ± 10% – 200 – ns input low width ZCD noise filter tRSL Input V DD = 5V ± 10% – 1 – µs tNF1L tNF1H

0.8 VDD

0.2 VDD

NOTE: The unit tCPU means one CPU clock period. Figure 13 -1 . Input Timing Measurement Points

KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA 13 - 5 Table 1 3-4 . Oscillator Characteristics Oscillator Clock Circuit Test Condition Min Typ Max Unit Main crystal or ceramic XIN XOUT V DD = 4. 5 to 5.5 V V DD = 2.7 to 4.5 V MHz External clock XIN XOUT V DD = 4. 5 to 5.5 V V DD = 2.7 to 4.5 V RC oscillator R XIN XOUT V DD = 4.75 to 5.25 V R = 8.2K – 4 (P1.3/ CLO) Table 1 3-5 . Oscillation Stabilization Time (T A = – 40 °C to + 85 °C, V DD = 2.7 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Main crystal fOSC > 1.0 MHz – – 20 ms Main ceramic Oscillation stabilization occurs when V DD is equal to the minimum oscillator voltage range. – – 10 External clock (main system) X IN input high and low width (t XH , t XL ) 25 – 500 ns Oscillator stabilization tWAIT when released by a reset (1) – 2 1 6 /f OSC – ms wait time tWAIT when released by an interrupt (2) – – – NOTES : 1 . fOSC is the oscillator frequency. 2 . The duration of the oscillator stabilization wait time, tWAIT , when it is released by an interrupt is dete r mined by the setting s in the basic timer control register, BTCON.

ELECTRICAL DATA KS86C4004/P4004/C4 104/P4104 13 - 6 CPU CLOCK

1 MHz

SUPPLY VOLTAGE (V)

2 MHz

3 MHz

4 MHz

8 MHz

10 MHz

2 3 4 5 6 71 2.7 5.5 Figure 13 -2 . Operating Voltage Range V DD V SS V out A B C D Vin A = 0.2 V DD B = 0.4 V DD C = 0.6 V DD D = 0.8 V DD 0.3 V DD 0.7 V DD Figure 13 -3 . Schmitt Trigger Input Characteristics Diagram

KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA 13 - 7 Table 1 3-6 . Data Retention Supply Voltage in Stop Mode (T A = – 40 °C to + 85 °C , V DD = 2.7 V to 5.5V ) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR Stop mode 2.0 – 5.5 V Data retention supply current IDDDR Stop mode; V DDDR = 2.0 V – 0.1 5 µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. tWAIT V DD RESET EXECUTION OF STOP V DDDR DATA RETENTION MODE STOP MODE INTERNAL RESET IDLE MODE (BASIC TIMER ACTIVE)

0.8 V DD

0.2 V DD

NOTE: tWAIT is the same as 4096 x 16 x 1/f OSC Figure 13 -4 . Stop Mode Release Timing When Initiated by a RESET

ELECTRICAL DATA KS86C4004/P4004/C4 104/P4104 13 - 8 Table 13-7. A/D Converter Electrical Characteristics (KS86C4004) (T A = – 40 °C to + 85 °C , V DD = 2.7 V to 5.5 V, V SS = 0 V ) KS86C4004: 8-bit ADC Parameter Symbol Test Conditions Min Typ Max Unit Total accuracy V DD = 5.12 V – – ± 2 LSB Integral linearity error ILE CPU clock = 10 MHz AV REF = 5.12 V – ± 1.5 Differential linearity error DLE AV SS = 0 V – ± 1 Offset error of top EOT – 1 ± 2 Offset error of bottom EOB – 1 ± 2 Conversion time (1) tCON fcpu = 10 MHz 5 – – µs Analog input voltage V IAN – AV SS – AV REF V Analog input impedance R AN – 2 – – M Ω ADC reference voltage AV REF – 2.5 – V DD V ADC reference ground AV SS – V SS – V SS + 0.3 V Analog input current IADIN AV REF = V DD = 5 V conversion time = 5 µs – – 10 µA ADC block current (2) IADC AV REF = V DD = 5 V conversion time = 5 µs – 1 3 mA AV REF = V DD = 3 V conversion time = 5 µs 0.5 1.5 AV REF = V DD = 5 V Power down mode – 100 500 nA NOTES: 1. “Conversion time” is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion.

KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA 13 - 9 Table 13-8. A/D Converter Electrical Characteristics (KS86C4104) (T A = – 40 °C to + 85 °C , V DD = 2.7 V to 5.5 V, V SS = 0 V ) KS86C4104: 10-bit ADC Parameter Symbol Test Conditions Min Typ Max Unit Resolution – 10 – bit Total accuracy V DD = 5.12 V – – ± 3 LSB Integral linearity error ILE CPU clock = 10 MHz AV REF = 5.12 V – ± 2 Differential linearity error DLE AV SS = 0 V – ± 1 Offset error of top EOT ± 1 ± 3 Offset error of bottom EOB ± 0.5 ± 2 Conversion time (1) tCON 10-bit conversion 50 x 4/ f OSC (3) 20 – – µs Analog input voltage V IAN – AV SS – AV REF V Analog input impedance R AN – 2 – – M Ω Analog reference voltage AV REF – 2.5 – V DD V Analog ground AV SS – V SS – V SS + 0.3 V Analog input current IADIN AV REF = V DD = 5 V conversion time = 20 µs – – 10 µA Analog block current (2) IADC AV REF = V DD = 5 V conversion time = 20 µs 1 3 mA AV REF = V DD = 3 V conversion time = 20 µs 0.5 1.5 mA AV REF = V DD = 5 V when power down mode 100 500 nA NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 3. fOSC is the main oscillator clock.

ELECTRICAL DATA KS86C4004/P4004/C4 104/P4104 13 - 10 Table 13-9. Zero Crossing Detector (T A = – 40 °C to + 85 °C , V DD = 4.5 V to 5.5 V, V SS = 0 V ) Parameter Symbol Test Conditions Min Typ Max Unit Zero-crossing detection input voltage V ZC AC connection c = 0.1 µF 1.0 – 3.0 Vp-p Zero-crossing detection accuracy V AZC fZC = 60 Hz (sine wave) V DD = 5 V fOSC = 10 MHz – – ± 150 mV Zero-crossing detection input frequency fZC – 40 – 200 Hz AC Input ZCINT 1/fZC VAZC VAZ(P-P) Figure 13 -5 . Zero Crossing Waveform Diagram

KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA 13 - 11 2 0 V O L (V) I O L (mA) V DD = 4.5 V V DD = 5.0 V V DD = 5.5 V 4 0 Figure 13 -6 . IOL vs. V OL (P0, TA = 25 °°C)

ELECTRICAL DATA KS86C4004/P4004/C4 104/P4104 13 - 12 2 0 V O L (V) I O L (mA) V DD = 4.5 V V DD = 5.0 V V DD = 5.5 V 4 0 Figure 13 -7 . IOL vs. V OL (P1–P3, TA = 25 °°C)

KS86C4004/P4004/C4104/P4104 ELECTRICAL DATA 13 - 13 − 8 − 36 − 20 − 32 − 28 V O H (V) I O H ( mA) − 4 − 16 − 24 − 12 V DD = 4.5 V V DD = 5.0 V V DD = 5.5 V Figure 13 -8 . IOH vs. V OH (P0, TA = 25 °°C)

ELECTRICAL DATA KS86C4004/P4004/C4 104/P4104 13 - 14 − 8 − 20 V O H (V) I O H ( mA) − 4 − 16 − 24 − 12 V DD = 4.5 V V DD = 5.0 V V DD = 5.5 V Figure 13 -9 . IOH vs. V OH (P1–P3, TA = 25 °°C)

KS86C4004/P4004/C4104/P4104 MECHANICAL DATA 1 4- 1 1 4 MECHANICAL DATA OVERVIEW The KS86C4004/C4104 is available in a 30 -pin S DIP package (Samsung: 30 - S DIP- 4 00) and a 32 -pin SO P package ( 32 - SOP - 450A), a 24-pin SDIP p ackage (24-SDIP-300) and a 24-pin SOP package (24-SOP-375). Package dimensions are shown in Figures 1 4- 1 , 14-2, 14-3, and 1 4-4 . NOTE : Dimensions are in millimeters. 30-SDIP-400 8.94 ± 0.2 #1 #15 #30 #16 0-15 ° 0.25 +0.1 – 0.05 10.16 1.12 ± 0.1 0.51MIN 3.81 ± 0.2 3.30 ± 0.3 5.08MAX (1.30) 0.56 ± 0.1 27.48 ± 0.2

27.88 MAX

1.778 Figure 1 4- 1. 30 -Pin S DIP Package Dimensions

MECHANICAL DATA KS86C4004/P4004/C4104/P4104 1 4- 2 0~8° 0.20 +0.10 - 0.05 8.34 ± 0.2 0.78 ± 0.2 11.43 #1 #16 #32 #17 32-SOP-450A 12.00 ± 0.3 NOTE : Dimensions are in millimeters. 19.90 ± 0.2

0.10 MAX

0.0MIN 2.00 ± 0.2 2.40MAX Figure 1 4- 2. 32 - SOP-450A Package Dimensions

KS86C4004/P4004/C4104/P4104 MECHANICAL DATA 1 4- 3 NOTE : Dimensions are in millimeters. 7.62 0-15 ° 0.25 +0.1 – 0.05 24-SDIP-300 6.40 ± 0.2 #1 #12 #24 #13 0.51MIN 3.25 ± 0.2 3.30 ± 0.3 5.08MAX 22.95 ± 0.2

23.35 MAX

(1.69) 0.89 ± 0.1 0.46 ± 0.1 1.778 Figure 1 4-3 . 24 - SDIP-300 Package Dimensions

MECHANICAL DATA KS86C4004/P4004/C4104/P4104 1 4- 4 NOTE : Dimensions are in millimeters. 7.50 ± 0.2 0-8° 0.85 ±0.20 9.53 0.15 +0.10 - 0.05 0.05MIN 2.30 ± 0.2 2.70MAX 15.34 ± 0.2

15.74 MAX

(0.69) 0.38 ± 0.1 24-SOP-375 10.30 ± 0.3 #1 #12 #24 #13 1.27 Figure 1 4-4 . 24 - SOP-375 Package Dimensions

KS86C4004/P4004/C4104/P4104 KS86P4004/P4104 OTP 1 5- 1

15 KS86P4004/P4104 OTP

The KS86P4004/P4104 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS86C4004/C4104 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS86P4004/P4104 is fully compatible with the KS86C4004/C4104 , both in function and in pin configuration. Because of its simple programming requirements, the KS86P4004/P4104 is ideal for use as an evaluation chip for the KS86C4004/C4104 . VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7 KS86P4004 30-SDIP (Top View) NOTE : The bolds indicate an OTP pin name. RESETRESET/ Figure 1 5-1 . Pin Assignment Diagram ( 30 -Pin S DIP Package)

KS86P4004/P4104 OTP KS86C4004/P4004/C4 104/P4104 15- 2 VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 NC P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 NC P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7 KS86P4004 32-SOP (Top View) NOTE : The bolds indicate an OTP pin name. RESETRESET/ Figure 1 5-2 . Pin Assignment Diagram ( 32 -Pin SOP Package)

KS86C4004/P4004/C4104/P4104 KS86P4004/P4104 OTP 1 5- 3 VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS KS86P4104 24-SDIP (Top View) NOTE : The bolds indicate an OTP pin name. RESETRESET/ Figure 1 5-3 . Pin Assignment Diagram ( 24 -Pin SDIP Package)

KS86P4004/P4104 OTP KS86C4004/P4004/C4104/P4104 15- 4 VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS KS86P4104 24-SOP (Top View) NOTE : The bolds indicate an OTP pin name. RESETRESET/ Figure 1 5-4 . Pin Assignment Diagram ( 24 -Pin SOP Package)

KS86C4004/P4004/C4104/P4104 KS86P4004/P4104 OTP 15- 5 Table 15-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P0.3 SDAT KS86P4004: 28 (30) KS86P4104: 22 (22) I/O Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned P0.2 SCLK KS86P4004: 29 (31) KS86P4104: 23 (23) I/O Serial clock pin (input only pin) TEST V PP (TEST) 4 I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 7 I Chip Initialization V DD /V SS V DD /V SS KS86P4004: 30 (32) / 1 KS86P4104: 24 (24) / 1 I Logic power supply pin. NOTE : ( ) means the SOP OTP pin number. Table 15-2. Comparison of KS86P4004/P4104 and KS86C4004/C4104 Features Characteristic KS86P4004/P4104 KS86C4004/C4104 Program Memory 4-Kbyte EPROM 4-Kbyte mask ROM Operating Voltage (V DD ) 2.7 V to 5.5 V 2.7 V to 5.5 V OTP Programming Mode V DD = 5 V, V PP (TEST) = 12.5 V Pin Configuration 30 SDIP/32 SOP/24 SDIP/24 SOP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the V PP (TEST) pin of the KS86P4004/P4104, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria V DD VPP (TEST) REG/ MEM ADDRESS (A15-A0) R/ W MODE

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE : "0" means Low level; "1" means High level.

KS86P4004/P4104 OTP KS86C4004/P4004/C4104/P4104 15- 6 NOTES