KS8620 SAMSUNG | Alldatasheet

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KS8620 1 Chip CODEC for Digital Answering phone INTRODUCTION The KS8620 consists of on-chip PCM encoders, decoders (PCM CODECs) and PCM line filter. This device provide all the functions required to interface a full- duplex voice telephone circuit, digital answering phone. This device is designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering function in PCM system. Also it is intended to be used at the analog termination of a PCM line / trunk. This device provide the Band pass filtering of the analog signals prior to encoding and after decoding. This combination device performs the encoding and decoding of voice and call progress tones as well as the signaling and supervision information. 16-DIP-300 16-SOP-BD300 - SG

FEATURES

  • Complete CODEC and filtering system
  • Encoding / Decoding : 8 bits µ-law PCM
  • On-chip auto zero, sample and hold, and precision voltage references
  • Low power dissipation : 60mW ( operating ) 3mW ( standby )
  • + 5V operation
  • TTL or CMOS compatible
  • Automatic power down

ORDERING INFORMATION

Device Package Operating Temperature KS8620N KS8620D 16-DIP-300 16-SOP- BD300 - SG 0oC ~ + 70oC

KS8620 1 Chip CODEC for Digital Answering phone Fig 1. Block Diagram Vcc VBB GNDA MCLKx MCLKR / PDN BCLKx BCLKR / CLKSEL FSR FSx Analog In RC Active Filter Switched Capacitor B.P.F Auto-zero logic Sample & Hold DAC A/D Control Logic X’it register DE Receive register CLK Sample & Hold DAC Voltage Reference RC Active Filter Switched Capacitor L.P.F comparator 6Power Amplifier Timing and Control 13 9 8 5 1210 74 1 2 Dx DR /TSx VFRO GSx VFxI+ VFxI- BLOCK DIAGRAM

KS8620 1 Chip CODEC for Digital Answering phone PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS ( Ta = 25 oC) Pin No Symbol Description VBB GNDA VFRO VCC FSR DR BCLKR / CLKSEL MCLKR / PDN MCLKX BCLKX DX FSX TSX GSX VFXI- VFXI+ VBB = -5V + 5% Analog ground Analog output of the receiver filter Vcc = +5V + Receive frame sync pulse. 8KHz pulse train. PCM data input Logic input which selects either 1.536MHz / 1.544MHz or 2.048MHz for master clock in normal operation and BCLKx is used for both TX and RX directions. Alternately direct clock input available, vary from 64KHz to 2.048MHz. When MCLKR is connected continuously high, the device goes powered down . Normally connected continuously low, MCLKx is selected for all DAC timing. Alternately direct 1.536MHz / 1.544MHz or 2.048MHz clock input is available. 1.536MHz / 1.544MHz or 2.048MHz clock input is available May be vary from 64KHz 2.048MHz, but BCLKx is externally tied with MCLKx in normal operation. PCM data output. TX frame sync pulse. 8KHz pulse train. Changed from high to low during the encoder timeslot. Open drain output. Analog output of the TX input amplifier. Used to set gain through external resistor between pin 14 to pin 15. Inverting input stage of the TX analog signal. Non-inverting input stage of the TX analog signal. Characteristic Positive Supply Voltage Negative Supply Voltage Voltage at any Analog Input or Output Voltage at any Digital Input or Output Operating Temperature Range Storage Temperature Range Lead Temperature Range ( soldering , 10 sec ) Symbol Value Unit Vcc VBB V I (A) V I (D) Ta TSTG TLEAD Vcc + 0.3 to VBB - 0.3 Vcc + 0.3 to GNDA - 0.3 0 to 70 -65 to +150 300 V V V V oC oC oC

KS8620 1 Chip CODEC for Digital Answering phone

ELECTRICAL CHARACTERISTICS

(Unless otherwise specified : Ta = 0oC to 70oC , Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V ) Characteristic System Test Conditions Min Typ Max Unit Power Dissipation Power down Current Active Current Digital Interface Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage Output Current in High impedance state ( Tri - state ) Output Resistance Load Resistance Load Capacitance Output DC offset voltage Input Leakage Current Input Resistance Output Resistance Load Resistance Load Capacitance Output Dynamic Range Voltage Gain Unity Gain bandwidth Offset Voltage Common - mode Voltage Common mode rejection ratio Power supply rejection ratio 2.2 -15 -15 2.4 2.4 -15 600 -200 -200 +/-2.8 5,000 -20 -2.5 3.0 1.0 0.6 0.4 0.4 0.4 500 200 200 2.5 I CC ( down ) I BB ( down ) I CC ( A ) I BB ( A ) V IL V IH I IL I IH V OL V OH I OH (HZ) R O R L C L V OO(RX) I LKG R I R O R L C L V OD(TX) G V B W V IO(TX) V CM(TX) CMRR PSRR Analog Interface with Receiver Filter Analog Interface with Transmit input Amp No Load No Load No Load No Load GNDA < VIN < VIL , all digital input VIH < VIN < Vcc DX , IL = 3.2 mA SIGR , IL = 1.0 mA /TSX , IL = 3.2 mA , open drain DX , IH = -3.2 mA SIGR , IH = -1.0 mA DX , GNDA < VO < Vcc pin VFRO VFRO = + / - 2.5V -2.5V< V<+2.5V , VFXI+ or VFXI- -2.5V< V<+2.5V , VFXI+ or VFXI- closed loop , unity gain GSx GSx GSx , RL < 10KΩ VFXI+ to GSx CMRRXA > 60dB DC test DC test 0.5 0.05 6.0 6.0 mA mA V V uA uA V V uA Ω Ω pF mV nA MΩ Ω KΩ pF V V / V MHz mV V dB dB

KS8620 1 Chip CODEC for Digital Answering phone TIMING CHARACTERISTICS (Unless otherwise specified : Ta = 0oC to 70oC, Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V ) Characteristic System Test Conditions Min Typ Max Unit Frequency of Master Clock Rise time of Bit Clock Fall Time of Bit Clock Hold Time for Bit Clock low to Frame sync Hold Time for Bit Clock High to Frame sync Set-up Time from Frame sync to Bit Clock low Delay time from BCLKx High to data valid Delay time to /TSx low Delay time from BCLKx low to data output disable Delay Time to valid data from FSx or BCLKx. Set-up Time from DR valid to BCLK x/R low Hold time from BCLK x/R low to DR invalid Set-up time from FS x/R to BCLK x/R low Width of master clock High Width of master clock Low Rise Time of Master clock Fall Time of Master clock Set-up time from BCLKx High ( FSx in Long Frame Sync mode ) to MCLKx falling edge Period of Bit Clock Width of Bit clock High Width of Bit clock Low Hold time from BCLK x/R to FS x/R low 160 160 485 160 160 100 180 140 165 165 15,725 fMCK tR(BCK) tF(BCK) tH(LFS) tH(HFS) tSU(FBCL) tD(HDV) tD(/TSXL) tD(LDD) tD(VD) tSU(DRBL) tH(BLDR) tSU(FBLS) tW(MCKH) tW(MCKL) tR(MCK) tF(MCK) tSU(BHMF) tCK tW(BCKH) tW(BCKL) tH(BLFL) Depends on the device used and the BCLKR /CLKSEL pin. MCLKx and MCLKR tPB = 488ns tPB = 488ns Long Frame only Short Frame only Long Frame only Load = 150pF + 2 LSTTL loads Load = 150pF + 2 LSTTL loads CL = 0 pF to 150 pF Whichever comes later. Short Frame sync pulse ( 1 or 2 bit clock periods long ) : note1 MCLKx and MCLKR MCLKx and MCLKR MCLKx and MCLKR MCLKx and MCLKR 1\`st bit clock after the leading edge of FSx VIH = 2.2V VIL = 0.6V Short Frame sync pulse ( 1 or 2 bit clock periods long ) : note1 1.536 1.544 2.048 488 MHz nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS

KS8620 1 Chip CODEC for Digital Answering phone TRANSMISSION CHARACTERISTICS (Unless otherwise specified : Ta = 0oC to 70oC, Vcc = 5V +5%, VBB = -5V +5%, GNDA = 0V, f = 1.02KHz Vin = 0dBm0, transmit input amplifier connected for unity-gain, non-inverting ) Characteristic System Test Conditions Min Typ Max Unit Amplitude Response Receive Gain, Absolute Receive Gain, Relative to Gv(RRX) Absolute Receive Gain Variations with temperature Receive Gain Variations with level Receive output drive level Absolute level Max overload level Transmit gain, absolute Transmit gain, relative to GV(ATX) GV(ARX) GV(RRX) Δ GV(ARX) /Δ T Δ GV(RXL) VO(RX) VAL VOL(MAX) GV(ATX) GV(RTX) Ta=25oC,VCC = 5V, VBB = -5V Input = Digital code sequence for 0dBm0 signal at 1020Hz f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz Ta = 0oC to 70oC Sinusoidal test method; reference input PCM code correspond to an ideally encoded -10dBm0 signal PCM level = -40dBm0 to +3dBm0 PCM level = -50dBm0 to -40dBm0 RL = 600Ω Norminal 0dBm0 level is same as 4 dBm ( 600Ω ) Max overload level ( 3.17dBm0) Ta = 25oC,Vcc =5V, VBB = -5V Input at GSx = 0dBm0 at 1020Hz f = 16 Hz f = 50 Hz f = 60 Hz f = 200 Hz f = 300 Hz - 3000Hz f = 3300 Hz f = 3400 Hz f = 4000 Hz f = 4600 Hz and above, mesaure response from 0 Hz to 4 KHz -1.5 -0.6 -0.55 -1.5 -0.4 -0.8 -2.5 -1.5 -0.5 -0.55 -1.5 1.2276 2.501 1.5 0.5 0.5 1.5 0.1 0.4 0.8 2.5 1.5 -35 -25 -21 -0.5 0.5 0.5 -1.5 -10 -25 dB dB dB dB V Vrms VPK dB dB

KS8620 1 Chip CODEC for Digital Answering phone TRANSMISSION CHARACTERISTICS ( Continued ) Characteristic System Test Conditions Min Typ Max Unit Absolute trasmit gain variations with temperature Transmit gain variations with level Δ GV(ATX) /Δ T Δ GV(TXL) Ta = 0oC to 70oC Sinusoldal test method ; Reference level = -10dBm0 VFXI + = -40dBm0 to +3dB0 VFXI + = -50dBm0 to -40dB0 + 0.1 0.4 0.8 -0.4 -0.8 dB dB Envelope Delay Distortion with Frequency Receive Delay, Absolute Receive Delay, Relative to tD (ARX) tD(ARX) tD(RRX) f = 1600Hz f = 500Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz f = 1600Hz f = 500Hz - 600Hz f = 600Hz - 800Hz f = 800Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz -40 -30 200 125 175 315 220 145 105 155 µs µs µs µs Noise tD(ATX) tD(RTX) Transmit Delay, Absolute Transmit Delay, Relative to tD(ATX) Receive Noise, C Message Weighted Transmit Noise, C Message Weighted NRXC NTXC PCM code equals alternating positive and negative zero, KS8620 KS8620 dBrnC0 dBrnC0

KS8620 1 Chip CODEC for Digital Answering phone TRANSMISSION CHARACTERISTICS ( Continued ) Characteristic System Test Conditions Min Typ Max Unit Noise, Single Frequency Positive Power Supply Rejection, Transmit Negative Power Supply Rejection, Transmit Positive Power Supply Rejection, Receive Negative Power Supply Rejection, Receive NSF PSRR(PTX) PSRR(NTX) PSRR(PRX) PSRR(NRX) f = 0KHz to 100KHz, loop around measurement, VFXI+ = 0Vrms VFXI+ = 0 Vrms, Vcc = 5.0 VDC + 100mVms f = 0KHz - 50KHz VFXI+ = 0 Vrms, VBB = -5.0 VDC + 100mVrms f = 0KHz - 50KHz PCM code equals positive zero Vcc = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4KHz - 25KHz PCM code equals positive zero VBB = -5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4KHz - 25KHz dBC dBC dBC dB dBC dB Spurious Out-Band Signals at the Channel Output SOS Loop around measurement, 0dBm0, 300Hz - 3400Hz input PCM applied to DR , Measure individual image signals at VFRO 4600Hz -7600Hz 7600Hz - 100,000Hz Distortion Signal to Total Distortion Transmit or Receive Half-Channel THDTX THDRX Sinusoidal test method ; level = 3.0dBm0 = 0dBm0 to 30dBm0 = -40dBm0 XMT RCV -28 -35 dB dBC -53 dBm0

KS8620 1 Chip CODEC for Digital Answering phone TRANSMISSION CHARACTERISTICS ( Continued ) Note 1. CT(RX-TX) is measured with a -40dBm0 activating signal applied at VFXI+ ENCODING FORMAT AT DX OUTPUT Characteristic System Test Conditions Min Typ Max Unit Single Frequency Disotrtion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion THDSF(TX) THDSF(RX) THDIMD Loop around measurement, VFXI+ = -4dBm0 to -21dBm0, two frequencies in the range 300Hz - 3400Hz -35 -dB Crosstalk Transmit to Receive Crosstalk, 0dBm0 Transmit level Reveive to Transmit Crosstalk, 0dBm0 Receive level CT(TX-RX) CT(RX-TX) f = 300Hz - 3400Hz DR = Steady PCM code f = 300Hz - 3400Hz, VFXI = 0V -90 -90 -75 -70 (note1) dB dB -41 -dB -41 -dB µ -Law PCM : KS8620 VIN ( at GSX ) = + Full Scale VIN ( at GSx ) = 0V VIN ( at GSx ) = - Full Scale 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0