KS84C31

KS84C32 SAMSUNG | Alldatasheet

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4 MBit ORAMs, while the KS84C32 supports 256K,

‘ evenbeniepeniiibaneinenannenienanan 1 MBit, 4 MBit, and 16 MBit DRAMs. lection of various options and features. + Bult In precision delay line Citically tailored to their bus operations. + CMOS technology for low tion Figure 1 shows a block diagram of the chips. Figure 1. KS84C31/32 Block Diagram ™ MCE8090, MCE8040 are registered trademarks of Motorola, Inc. ™ 1486 is a registored trademark of Intel, lnc.

INTRODUCTION The KS84C31/32 DAC offers four refreshing control modes: The KS84C31/32 are Dynamic Ram Controllers (hereat- ter referred to as DRCs) which are built upon the proven 1) Internal automatic retreehing KS84C21/22 architecture with enhancements that im- 2) internal automatic burst retreshing prove memory access time and make it especially sult- - able for cache based memory systems. The DRC con- 5) extemally controlied/burst refreshing tains all of the advanced features of its predecessor 4) refresh request/acknowledge refreshing oC ie Capabiies of address Naiches, rolresn When using intemal automatic refreshing, the DRC’s delay tine, retrestvacosss arbiration logic, high capaci refresh request clock generates intemal refresh requests. tive output drivers and on-chip damping resistors. A The DAC arbitrates between refresh requests and ac- Programmabie system interface allows any manulacturer’s perpen tahetnahaidie bilayer CPU orcache controllerto be interfacedio DRAM arrays -—- Wl assert the refresh in progress signal (RFIP). The re- to 64 Mbytes in size. 2 fresh will start on the next rising clock edge. If an access ” had been in progress, the refresh would be delayed until The incorporation of on-chip page detection logic enables the access is terminated. the DRC to support random accesses within a page for use with page and static column mode DRAMs. A 2-bit Piel riernalinteslenriaielah eaters wrap around column counter may be used during burst ‘age Programmed. recpu accesses. On-chip RAS timeout circuitry enables the DRC Clock has generated the fifth internal refresh request, the to maintain an active RAS signal while EPROM or /O ig DRC will arbitrate between the refresh request and any referenced, greatly improving system performance in accesses in progress. The DRC will assert AFIP and embedded contro! applications and during datatransters Perform a five retresh burst. between memory and /0. To use externally controlled burstirefreshing, the inter- nally requested refreshes are disabled by asserting the cesses are suporied. The special 62030 programmes dsable retresh (DISFASA) signal. A etresh can now be mode supports a burst memory access which doubles the ee Th ied by asearting the refresh (Fi wen) winutue.° = extemal refresh requests, assert RFIP and perform the tefresh. The DRC must be programmed after powerupbetorethe wren ratresh snowledge retreshing is used, sda Archania The ORC Is programmed the DAC broadcasts the intemal refresh request by as- through the address bus. serting the refresh request (RFA) signal. External cir- There are two methods of programming the chip. Thefirst cultry can determine when to enable the refresh by method, Mode Load , is performed by first asserting the asserting RFSH. When RFSH is asserted, the DRC will mode toad (HL) sigral and preserting the programming perform an externally controlied/burst refresh. selection on the row, column, bank and inputs. The programming selection is loaded info the Mode Register __""® ORC supporis two types of reireshing when ML is negated. 1) RAS Only The second method, Fake Access, i performed by fst 2) RAS Only with Error Scrubbing asserting ML, then performing a chip selecied access. =, . FAS onty retresh, all the RAS outputs willbe asserted Tid ws oscansd te lonned tao tre Mode Register: The and negated at once. Error scrubbing Is the same as RAS DRC then asserts the appropriaie control signals to only refresh except that aCAS and column address will be terminate the chip selected access asserted during refresh, allowing the sysiem to run the " data through an error detection/correction chip and write The DRC supports two access modes, synchronous it back to memory if an error has occured. (Access Mode 0) and asynchronous (Access Mode 1). To access the DRAM in Mode 0, the address laich enable (ALE) signal is asserted. RAS will be asseriedon the next rising clock edge. To access the DRAM in Mode 1, the address strobe (ADS) signal is asserted causing HAS to be asserted immediately. Es & SAMSUNG os Electronics

be used in fall through mode, even when the DRC is The Dynamic RamControlleris available in wo packages. 2,30r 4 bank memory array up to 36 bits in width (32 data, DRAMs. The logic symbols are in Figure 3. 4 parity). The CAS enable (ECAS) signals can then be 7 shown in Figure 3. data writes to an incorrect page. Figure 3. Logic Symbol dam wena b> Hj me | Meamobs.

0 Rass P 3 m0 nasoP

Tables 1 and 2 show detailed pin allocations for the KS84C31 and KS84C32, respectively. Table 1. KS84C31 Pin Allocations | 20 [ECASi [Enable Cast - [60 Add Wait State .

30 Enable CAS2 a) Refresh in Progress

Table 2. KS84C32 Pin Allocations

6 C1 ‘Column Address 1 BIN Burst Inhibit

[a7 |o2 ‘Column Address 2 [s7 [— NG. 20 |R4 Row Address 4 _ 60 |GRANT [Access Grant .

25 C6 Column Address 6 | =| EXTORF Extend Refresh

41 ALE/ADS [Address Latch Enable/ 80 [a1 Multiplexed Address 1

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Table 3. Intertace Signal Descriptions . addresses, and initiates the DRAM access. only assert ADS (ALE) during the opening cycle. Mode 14, this input functions as Address Strobe (ADS). AREQ: InSingle Access Mode, this input functions as Access Request Itbrings RAS. and CAS highto terminate the access. In Page Access Mode, AREQonly brings CAS. the MC68030's CBREO signal, it controls the termination of the DRC’s burst access. BIN: When programmed for 68040 Burst Mode, this signal functions as Burst Inhibit. -|DTACK Data Transfer Acknowledge: This output is asserted to terminate the CPU access. WATTIN ‘Wait State Insert: This inputis usedto dynamically add wait states during a bus cycle. 11 RG=0 during programming, WAITIN is used to add one wait state during the access. will not be sampled again, until the next access.

Table 3. Interface Signal Descriptions (Continued) remain asserted until the access RAS is negated. they should be connected to the low order address bits. RO-9,10 Row Address Inputs: Theses address bits are connected to the CPU’s address bus. should be connected to the higher order address bits. automatically added to the access cycle. [on the rising edge of CLK that negates DTACK when the DRC is bursting. 20-9,10 Address Outputs: These outputs are the multiplexed address bits (RO-10, C0-10). tor interleaved operation, this output functions as Refresh Request. When the DRC. Write Enable or Refresh Request. whenever a refresh request has been generated by the internal refresh interval timer. IRFRQ is negated when the retresh begins.

‘error scrubbing, this pin is time multiplexed. to terminate RAS when the DRC is programmed for Page Mode. as Disable Page Mode and does not affect refresh cycles. code or if refreshes are going to be controlled externally. is asserted one clock cycle prior to the start of a refresh cycle. access arbitration and timing. refresh requests are generated at 15 ys or 13 ys intervals.

‘When programmed for Page Mode operation (ECAS2 = choose when to increment the address counter depend- 1), the DRC maintains RAS and GRANT low for 5 internal ing on whether page or static column DRAMs are used. refresh requests (75 us). After the Sth internat refresh The DC's burst access can be terminated early f the request, both signals will be negated when AREO ter- CPU is performing a single access or aborts the burst. minales the access. The DRCwilthenperforma5rettesh Caner burst made may be combined with Page Mode burst. operation to reduce the number of clock cycles required Certain applications may require that, atcertaintimes,the for the opening access of the burst by programming DRAM is precharged prior to an access start. Since itis ECAS2~ 1, Whenprogrammedin combination with Page impossible to ensure that a given access will result in a Mode, CAS will be negated, but RAS will remain asserted page hit, and i the penalty of a page miss is intolerable, _after the last access of the burst. completes. be used to negate RAS when an access IS sp spas asserted during an access, both RAS andCAS 7 are negated when the access is completed. The DRC will If DISPM is asserted when there is no access or refresh continue to function as though it were not programmed for in progress, RAS is negated immediately. lf DISPM is Page Mode (ECAS2 = 0) as long as DISPM is asserted. asserted during an access, AREQ will negate both RAS _ After DISPMis negated, all pending refreshes (up 105) will and CAS when the access is completed. The DRC will _be performed in a burst refresh. Continue to function as though it were programmed for The on-chip address counter is enabled when the ad- Single Access Mode operation as long as DISPM is Gress latches are programmed to latch the address on the asserted. After DISPMis negated, allpendingrefreshes fanrevansre ns ABCA) the lalches ave wennoront {up to 5) will be performed in a burst refresh. the counter is disabled. When the latches are transpar- When the DRC is not programmed to support error ent, external circuitry may be used to provide a new scrubbing, DISPM has no elfecton RAS duringretreshes. column address to the DRC. Pree erg proarammedto support errorscrudbing. tthe on-chip address counter is used, the user needs to is time multiplexed with EXTDRF. EXTDRF will ur r < select when the counter is incremented. i static column causethe refresh RAS tobe extended whenitissampled S04 ; s are used, RG = 0 should be programmed. I page active ong “sing edge of CLK thatwas programmed! mode DRAMS are used, RS = 1 may be programmed. negate RAS. When R6 = 0, the column address will be incremented when CAS is negated. When R6 = 1, the column address Burst Mode Accesses is incremented before the access is completed, on the In order to support high performance CPUs that can CLK edge that asserts DTACK perform up to 4 memory accesses in a ‘single burst, the FAS \\ KS84C31/32 is capable of performing 4 accesses when ___Th® CAS strobe is negated when the DRAM access is AC31/3 completed, even when static column DRAMS are used. OO Or ets Themes, This insures that data is not strobed into the incorrect ‘supports two forms of burst mode operation. When pro- ‘grammed for 68040 Burst Mode, CAS is asserted onthe P90 # a Page miss occurs during a write access. falling edge of CLK and is negated on the rising edge of Since the CAS propagtion delay and precharge time is CLK. This mode should be used when the data is tobe matched to the DRC’s column address increment propa- sampled on the rising edge of CLK such as with the gation delay, there is no performance penalty associated MC68040 and i486 CPUs. To accomodate CPU's that _with bringing CAS high. sample data on the falling edge of CLK, such as the MC68030, 68030 Burst Mode should be used. In 68030 68040 Burst Access Mode Burst Mode, CAS is asserted on the rising edge of CLK , — , d 68040 Burst Mode operation is selected when ECASi, and is negated on the falling edge of CLK. FCASS 201 duro eoennina Colmn DRANsinbutnurstmoses, anorehpsdsrese Whenrograryned or 68040 Burst Mode, TASis aways counter may be used while bursting, desired. The zat Negated Bina Same rising CLI edge that negales sadrene ocunter wraps a round ta support GPU's that OTACK. CAS is atways asserted on the next falling CLK wrap around when filing their cache lines. The user can PdNe Unless The DAC has completed the burst or the ——— & SAMSUNG oe Electronics

of CLK that negates CAS and DTACK, and if asserted, the ‘second access by asserting BIN. During the first access, the DRC is allowed to complete miss. Figure 8. 68040 Burst Mode Access (ECAS2 = 0 Programmed)

1 NORMAL TERMINATION 1 ABORTED ACCESS i]

Figure 9. Burst Mode Access with Page Mode (ECAS2 = 1, R6 = 0 Programmed)

88 EX RETRO

Figure 10. Burst Mode Access with Page Mode (ECAS2 = 1, R6 = 1 Programmed)

68030 Burst Access Mode The DRC’s DTACK output drives the MC68030's STERM

similar to 68040 Burst Mode operation, with only wo Two 68030 Burst Mode accesses are shown in Figure 11. ‘second access by negating CBREQ. Figure 11. 68030 Burst Mode Access (ECAS2 = 0 Programmed)

Figure 12. 68030 Burst Mode with Page Mode (ECAS2 = 1, R6 = 0 Programmed) Figure 13. 68030 Burst Mode with Page Mode (ECAS2 = 1, R6 = 1 Programmed)

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Interleaved Access Modes a) insert the desired number of wait states during the The KS84C31/32 supports. 2 or 4-way interleaved ac- access, cesses between memory banks. By interleaving accesses, b) delay the access until the refresh in progress is performance degradation due to RAS access and complete, or Precharge time is minimized. ¢) delay the access to guarantee RAS precharge time. en ee Nee Te aati neesest The DRC generates two output signals to support the ‘Support address pipelining. When interleaving accesses, —_—ingertion of wait states. GRANT is asserted to inform ex- the DRC supplies the next row address after the column DTACI pitlliters acini neared urn tema logic thatthe DRC has begun an access. DTACK is Boe ete a ena an eee the a8sertedtoterminate the access. Aninput signal, WAITIN, next access Is to a differer memory than isprovidedio allow the user to add wai states dynamically current access. RAS will be asserted for the next access by ALE(ADS). uring the access. GRANT mimics the operation of RAS during an access. Fae OAS cortmoraton ets G4 eens Te the Like RAS, it is asserted synchronous to CLK in Mode 0 bits enable the DRC b intiate an access toone bank wan _ andasynchronus to CLK in Mode 1 and remains active ate ADS) while wa aa iate an access to one bank until RAS is negated. Incase of a page miss, both GRANT TE Te ET eS aon pang afd RAS will remain negated for at least 1 so that winanea. output should not be usedinthis GRANT may be sampled by external circuitry to deter- . mine i a page miss has occured. GRANT is deasserted The ECASnbits shouldbe programmedtorSingle Access during refresh operations. Mode for proper interleaved operation. R8 = 0 should be Wen programmed for Page Mode operation, GRANT will Programmed so that the DRAM controller will drive the remain asserted for two rising edges of CLK after ADS is new row address onto the bus after the column address "or aueatton or me Ra Rooms © Re a hold time for the current access is satisfied. and the 5th intemal refresh request (See Automatic Interleaved Access Mode should not be used in conjune- _/ntemal Burst Refreshing). tionwithpage or burst mode operation. However,theRAS TACK may be programmed (via R7) to be asserted on Oe Tt he. Coa on Cec eeguNe the rising oF falling CLK edge. The number of CLK edges accesses hit different banks. Only one CLK of precharge that DTACK is delayed, is programmable. DTACK is willbe incurred when switching banks. The programmed Corrojed by programming bis Re and R& lor any access number of Pracharge, lock cycles wil be Observed uring which ASisintially asserted e. single accesses, cons access Same memory bank. page misses, etc). Programming bits R4 and RS control Wat State Support DTACK during page hits and while bursting. , , , Figures 15 and 16 show how DTACK behaves in Mode 0 Wait states are required when a relatively slow DRAM is ang 4 accesses during which RAS is initially asserted. operating with a fast CPU. Wait states allow the CPU's Figures 17 and 18 shows how DTACK behaves during bus cycle to be extended by one or more CPU clock hts periods. The KS84C31/32willinsertwaitstatesduringthe Page Nits. CPU's DRAM bus access in order to: au 696 & SAMSUNG Electronics

Figure 14. 2-Way Interleaved Access Mode Operation (ECASO = 1 Programmed) Figure 15. DTACK During Mode 0 Accesses, RAS Figure 17. DTACK During Mode 0 Page Hits Figure 16. DTACK During Mode 1 Accesses, RAS Figure 18. DTACK During Mode 1 Page Hits

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REFRESH OPERATIONS RFRQis usedin the refresh requesvacknowledge mode. DISRFSH and RFSH are used inthe externally controlled/ . asserting RFSH. in Figure 26. Figure 26. RAS Low and Precharge Time

matic intemal refresh as tong as a DRAM access is not internal refresh contro! mode. DISRFSH must be negated to enable automatic intemal _ precharged. Figure 27. Externally Controlied/Burst Refresh

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Figure 28. Refresh Request/Acknowledge Refresh exception of bit C8, which is set) and all internal counters RO By version of the chip is being used. a Li iit if enabled to receive the mode bit inputs. time by asserting RFSH while DISRFSH is high. The DRC supports two types of refreshing: operating modes of the DRC. output enable lines to avoid bus contention if the DRAM _ into the Moad Load Register on the falling edge of AREQ.

Table 4. Programming the Mode Register always latched by the on-chip page detect logic regardless of how B0 is programmed. disabling the automatic column increment. B1 allows the user to specify either synchronous or asynchronous access start and termination modes. minated by the rising edge of AREQ.

Table 4. Programming the Mode Reglster (Continued) These bits controlthe time that RAS is low during refresh operations and also determinethe RAS prochargatine. ‘Access Modes or i a page miss occurs during the opening access when they are combined with Page Mode. on rising oF falling CLK edges. Burst or 68030 Burst Access Modes and Page Mode is used. on rising or falling CLK edges.

be incremented when the DRG is operated in 68040 Burst and 68030 Burst Modes. R7 This bit controls whethor OTACK is asserted (and WAITIN is sampled) on rising or falling CLK edges. R8 determines whether the Q outputs are driven in interleaved or non-interleaved mode. addresses have been held for a sufficient time (25ns minimum) after CAS has gone low. fe | This bit should be programmed = 0. I programmed = 1, Error Scrubbing is not supported. clock is generated. Select the divisor such that the internal refresh clock frequency is approximately 2 MHz.

Table 4. Programming the Mode Register (Continued) ccarresponding ECAS can ge low. BO and Bi aro not used. a ory tonaesby canoe.” [0 | X [FASE.1 wd S6. coresponding ECAS can go low BO and B1 are not used. .

C7 allows the user to specify the minimum guaranteed column address setup time (tasc). 8 allows the user to specify the minimum guaranteed row address hold time (tan). C9 allows the user to delay CAS during write operations that resul in page hits or that occur during a burst cycle. rising CLK edge after RAS is negated.

DC ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Note: Ifthe device is used beyond the maximum rating, permanent damage may occur. Operation should be timited to those conditions specified under DC Electrical Charactorisics. [Svmbot[ Parameter | Conation | min | Typ | Max [Unt | [Yn _[ earn votige | Toaodwiimtosustzaton | 20 | [Veo] v | fil [Wi [Wed iow Votage | Tosod winimiediestpatem [0s] | 08 | v | O and WE Ov a | Vou [@anaWeouputs — [ta-toma || fos | [Mowe | Atenas oxcon GansWE[toie-ima site || Atoupuis excep QandWe [in=ama | Tos |v [tm [input Leakage Curent | Vw=Vecorves | || a0 | | [tum [MC impacuron — [vneves | a0 | a [Tees [Sippy Curent [ps ave nado) || 65 a5 [ma | [cen [mew capsctans warm || 8 | or | AC SWITCHING CHARACTERISTICS Figure 31 shows a typical test circuit, while Figure 32 shows the output drive levels. Figures 34 through 53 provide ‘switching characteristics for a number of typical KS84C31/32 operations: Unless otherwise stated Voc = 4.75V to 5.25V, 0 < Ty < 70°C Load Capacitance: Q0-09, Q10 C. = 380pF We _ C= 500pF RASO-3,CASO-S C= 125pF Allother outputs C= S0pF All minimum and maximum values are measured in nanoseconds. Propagation delay variance vs. load capacitance: RAS, CAS. ‘Sns/100pF rise time ‘3ns/100pF fall time Q0-Q9, Q10 4ns/100pF rise time ‘3ns/100pF fail time eee 709 a SAMSUNG Electronics

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Figure 39. 68030 Burst Access Mode

Figure 40. 68030 Burst Access Mode with Page Mode

Figure 41. Burst Access Mode with Page Mode (68040, 80496)

Figure 42. 68040 Burst Access Mode

Figure 3. ftaodeat DELAY ERS ported Burst Write

Figure 48. Repnest with Extend Refresh

Figure 52. Page Mode — Disable Page Mode and Internal Refresh

Figure 53. Access Cycle Termination

Figure 53. Access Cycle Termination (Continued)

68030 Mode 68040 Burst Mode

Figuee 3. Access Cycle Termination (Continued)

68030 Mode

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68040 Burst Mode

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[ Min [wax | Min | Max | win | Max | [or [ALE minimumiowtime CT | CP to | oT | 02 | CStomccessstatswp ST | CP | Tl | 03 [AccessstattoMASassoted =| | ae || 6 [| 28 | |“ [Srmatrenoneatmonmnecomoracime [8 | fe | fel | setup time [0s | Aédress nol ime tom ALE low whenvsigthe onehipiach | a0 || ao [| ot | a | tran = 12ns, tasc = Ons. 70 70 b [iw tanstusc= tone | a8 | 80 | 48 | 75 | 49 | 75 | . ES a [i= t6ns.uece tons S*d a fs | 8 | 80 | 8 [0 | 7. [ewagermmere Tet fol [el a ‘tran = 12ns b [imistore CC CT OT 70 | [08 [AlEhightoCiKrisingeso dT TT TT || [oo [AtEpusewin Pe | to TT oT [010 | CShoidatteraccessstat | | to TP to | [11 [AREGI0 CLK rising edge setuptime Tt | | Tl || [012 [AREGHomCiKrising edgehoidtime | 2 | | 2 | Uf 2 || [014 | ClKrising edgetoRASdeassortod =| S| 0 || 5 || 28 | [015 | ClKrising edgetoCASdoassortod | 8 «| 27 | 8 | 3 | 8 | 23 | [ore [cixrisingedgetoGRANTdeassered || ee | ft || 20 | [or [AEnegadtoncikisingewe St] Let Let | Mode 0 Page Mode Related Parameters [ean af PT [min | Max | Min | Max | iin | Max | [Fo [feenteesecgrontnvmeranrenens | Tmt tay lay (non-delayed access) [Pe [Rea Siamha ee momen ASwtceren Your] [er] [en] in case of page miss . [Pas [CAS deassoredtomGikrangedge | 8 | 23 | | os | | | [ Poa | Access Stato CASlowipageht | 8 (| 28 |G | 25 | 6 | 25 | | Pos | GRANThigh tom access stantincaseofpagemis || as || 22 || 22 | [Pos | RAShigh trom accassstanincase ofapayemss | @ | as | 5 | 30 | 5 | 30 | [Po7 | Row and bank address set upto assure apagemissis recognized | | 6 | | é | | 6 | [Poe [Row andbarkeddresshoWtromaccesssan | | ao | | ao || 0 | [Poe [WNowsetpiracesssiancaen) Te | Te | Te || [Peto |WNiowholltimetomaccessstat(o-m) To | [ot Te [| [Poit | DISPMhigh setuptoCiKrising edge | || to || 8 | [pore | DisPMassertedtoaccessstat | S| CT to Tf oT | [rr [semen ereowmeemcine Pet Tey ty | address setup time 730 && SAMSUNG Electronics

| came fae |e a he tt femusesanmmn dal [wl [: [espeseeueimemeeren tal tel Ld [12 [CStoaccessstansowp Ta Tt | 13 [Access stato RAS assorted Tos {feet oe | [14 | Addross sotup to accass star to guarantee Ons row address setuptine | 10 | [ro | | io | | |_15__| Address hold tne rom access startwhen using the on chipiatcn | 20 | [20 [ [10 | | amen olalelnleln) BM tran = 12ns, tasc = Ons 75 70 70 2 [teas ans.tasc= tons fas La | a0 [78 YT a9 [75 | [tenn= TOns. tase = Ong fas [a0 [49 | 78 | a9 | 75 | Pai tne. use fons «dws [a | 0 | a8 | 00 | i a ero [Ts| [eT [70 | [18 | 'AREG rising edge to CLK rising edge to be recognized as 1T of RAS procharge| 20 [ [17 [ [1a || [19 | AOS puise wih Pe To PPro TT | 110 |CShoWatoreccesssiat fo To [fof | [111 |AREGdeassonedtoRASdeassened Ts | fo | 30 | [112 [AREGdeasseredtoGASdeassoned taf 2 | to | 28 | | 28 | | 113 _| GRANT deassonodtromAREGhigh Pas Tf ca | 20 | [114 [AREGassenog fo fe Pe TT [15 [AREGpusewion ee To [Po fT [116 | REG rising eogeroaccnsastan R= Frontera) | 5 | fo] fo [| Mode 1 Page Mode Related Parameters [_-2 [| -s3 [ -0 | | ein [ax [Mn [Max in [Ma Sa a a a precharge in case of page miss [Pit [Access stant (ADS tating odge)oGRANTiow | ao | [te | | 18 | ad aie ss | pis [Access stantoCASiowipagenit | [2a | 6 | 2s | 6 | 25] | Fis | GRANT igh rom ADS tating o6ge tpage minnie dmecied || 20 | [20 || 20| | P16 | RAShigh tom access startin caseofapagemiss Sd —*dt 8s | |_| 30] | _P17_[ Row and bank address setupto assure apage missis recognized [10 |__| vo | [vot | | Pia [Rowand bank address holdtromaccessstan Pao [20 || 10 | | Pio [Willow setupio sccosssten(coety) Pe Te Tat | | Pio | Witliow hoidtime trom access stant(oa='my) TTT fet | [| pri | oispMassonedtoaccessstat fs tof a [_pi1a [Address setup to aconnn stato guarantee ons column address sewptine | 1o[ [so [so | | ~ 731

Pee Ls [= [= —— Sepa eae fse| [ee [RGhpuiecoupa sf mo P| Row address hold time exceed] [el | See al tal al [wmngnowengn ds | tao | | | [Ww e Wie fe fp eecomnnrime io | fof [ ol | tasc = Ons “een det Pe te [C6 | Column address hold time (Iinterteaveony) «| 25 | 60 | 25 | 60 | 25 | 60 | [er | cues ope oS enonod ater dneyntaaons | [et [es] [2s] Oo, [keere emer sewretacee a | 5 | o| | |r| a | tran= 12n8, tase = Ons. 75 49 | 70 b [tw=t2nstsc= ins SSC A | 80 | 49 | 75 | 49 | 75 | © [iqustene.iges ow fo fo Pee fs [9 P| &_[inwt= thn seston | as [@]oota [oo [cs —T tk tang ogo GAS doassorad inode Gb=7)———~d~C*dt | tf] [ecasnnwomsin ss fas fe [wo || [EekSior wSine to Pas fem [| [cr [oxo | ——Ssd a | fat [asst] [eis expense os | [Cote | wrcun gp ie te fe [eis [recikew ee | fg Ye | a Cova Od a | tran= 12ns. See ee ‘Common Page Mode Related Parameters [ 25 | -3 | -0 | | Min [ax | Min | Max | Min | Max [Pi] GRANT ow om aceas can Gtordaccnsy ———SSSSSS*dCid ssf fat [cre [SPU ing doe o RAS rogaied SSS ds [fs |_| {psoas geo GRANT ropand | [| [= | T| [ra —[oisPtigh puse waif pst ol | & SAMSUNG = Electronics

‘Common Wait State Parameters Ems fi ie | [min [ax | win [Max | Mn [Max | lcxinoseomrnw wv |e |i s | sm TaKiow a=) [oof | a] | 18] fmmusecraneunvanr mvam lel [el [al | [WAT eine CikisingeteoaeT —@sv.nr-n fret fet tet] [wirmresinetoncesiingee eorerrem || |s| |s| | WAITIN hold time from clock falling edge (RG = 0", R7 = '1") [s{ [s{ [s{ | 2 [Semmes eh fo | fof [ol CLK rising edge (R7=0) [ciktaingeage SST SSC«d oT Po] Ol ta CLK rising edge (R7=0) [ciktaing wpe en ft ts "(sie rh 2 CLK rising edge (A7 = 0) CLK falling edge (R7='1) fe[ tel [st | [we [etkrisin edgeto TACK deassored burtmode) | @ | 20 | @ | v0 | @ | 7] Mode 0 Walt State Parameters a ae [win [Max | win [Max | win [ ax [Wor [tkrising edgetoDTAGKhigh dT Lf | te | | 18 | [_wo2 | WAITINiow setuptoaccessstat R= ty Et TTT TT [wis | WATWiow tine om soonean 5-1) ‘two | trol le] _| [ wos [CLK rng age to DTACK assoned during pagent (Toewranmed) | 6 || ¢ [eo] [20] Mode 1 Wait State Parameters ee [win [max] tin [| mn [ax [wir] AOStating edge toOTACKassonos | ee to | 8 | [wie | AREG ring edge io DTACK deassoned ———SSCS~S~S Sf ww ww | a | [wis [WatWowssoptsconssan eam stot pot fet | [wis [WATWiownoWtine tonsconesar mse) Ste | fat fel | & SAMSUNG " Electronics

[2 [a [0] eee [wi [Weseetessoupine SSS Ts |_| A | M3 |MCassonedtoAREGassotod tf to] [to | [4 [cS ssonedio BEG antenes SSS s | ts | sf | Me [Nese aeress oidtine tom AEGansenes ——~—SSSCSCSC~*d ao | zo | | - [ie [nese asresssoupsine wo ARESansores Ss | ts} fs] [m7 [ARC essoradio DTACK aeenes tm Tf] [we [ARE or WC deassred iw DTACKawened | ts | fs [fs | [we [ipisewin SSSC«*d OT fT [Wo [6S tote ton ARECTaing pe fortakowwess) «dt wo | wf fof | Burst Mode Parameters [ss [a [naam aft i [wi [ening ope AS aeansores EAST) ie fas fo | ml 0 || coss-1) fe lastelaole |e [ns [o1Ktatng eget CAS deasoned —_€CASI-1) ita [as fol ale |a| [a [otk sg ope 2 HS estones ___—_€caST=v) |e fase [aol e [ao a EIRNEIERES SS a came pete e tats fe] [a7 [Wiiowsetwiecikineede w= tes] fot fal | [No | Wiiow itive fon GuK sig ogo 02-1) ‘ts {fst fal _| [Wo | BREG sep io CLK rig edge at nogaie DTAGK vo | Pe | + | [110 | CHRECH ot ne tor CLK rig ope tatregaes TREK se | Pet al [it [eWseupiocixringeye | [fo [Wiz [an hoidine ton cukisng eto SSC 2 | Pe |e ny 734 SAMSUNG Electronics

Refresh Related Parameters Esau i [tn [ax] nn [a tn [a NS [Ra | RFSHiowhoktine ton CuK ang edge SSS | ts | ts | | | RS___| FSH pulse wicthorresoting etreshcountor tS | fs Ts || [Re [DISAFSHiowsotuptoctKrisngedge to | Po | tof | [Rs [DISAFSH iow holdtimetrom cKrisingedge ST OT | ts [| [ns [DSAFSHiowpuscewan Cs Ts | fs || [a7 [ctkrisingedgetoRFPassoned Tot ft | I 5 | [he cuKrising edge FFF deassoned ———SCS*~S~S~S~SCid | ds || 2 [Cho [cuxrsing edgetoRFRGassoned —_———SSSCS~S~S~S Sto] to || [Tio [ctkrising edge toRFAGdeassened | fe | vo | [1 | [Art [ux ring ge torereh PAS assered ——————SSSCS~sSCid as | fe || [ara [eux ring ogo tortrsh PAS deassoned ————S—S~~SCi 0 | er | far] [RIS [EXTDAFseuptoCiKrsingedge tt TP to Ts | [Ri4 [ExtDAFhodimetomciKrsingee te | Cf | fa | [Rts [EXrDArFiowseuptociKrsngege ——SSSSSCSSCi | tt std ry 735, & SAMSUNG Electronics

ORDERING INFORMATION AND PRODUCT CODE Ks B4CXX xX x x SAMSUNG Packaging SEMICONDUCTOR L — Plastic Leaded Chip Carrier (PLCC) Part Number 84C31

84032 Temperature

C — Commercial (0°C to +70°C) 2 Speed 25 25MHz -33 33.33MHz 40 40MHz SAMSUNG products are designated by a Product Code. Whon ordering, please refer to products by their full code. For unusual, andlor specific packaging or processing requirements not covered by the standard product line, please contact the SAMSUNG MOS Product Group. SAMSUNG SEMICONDUCTOR, INCORPORATED SALES OFFICES NORTHEAST NORTH CENTRAL SOUTHWEST SOUTHWEST 20 Mall Road 901 Warrenville Road 22837 Ventura Blvd ‘Airport Exec. Suites Suite 410 Suita 120 Suito 305 2102 Business Contor Dr. Burlington, MA 01803 Lisle, IL 60532-1359 Woodland Hills, CA 91367 ‘Suite 169 617/273-4888 708/852-2011 816/046-6416 Irvine, CA 92715 FAX 617/273-9363 FAX 708/852-9096 FAX 816/346-6621 (714) 283-6796 FAX (714) 252-8842 NORTHWEST ‘SOUTH CENTRAL SOUTHEAST 2700 Augustine Drive 15851 Dallas Parkway 204 Battleground Corp. Park Suite 198 Suite 840 $3859 Battloground Ave. Santa Clara, CA 95054 Dallas, TX 75248-9307 Greensboro, NC 27410 408/727-7433 214/770-7970 919/282-0665 FAX 408/727-5071 FAX 214/770-7971 FAX 919/282-0784 Ciruit diagrams utizing SAMSUNG and/or SAMSUNG ELECTRONICS products ae included as ameansofitustrang pial eeminconductor applications; consequent, complete information auficient for consiructon purposes ie not necessarily given. The information has been careluly checked andis bekeved io be entrely fable. However, 10 responsBilly is assumed for naccuraces, Furhermore, auch information dows not corwey othe purchaser ofthe semiconductor devices described herein any Lcanse under te patan rights of SAMSUNG andor SAMSUNG ELECTRONS, or others. SAMSUNG ane SAMGUNG ELECTRONS, rosorve the ight chenge device specicasons LUFE SUPPORT APPLICATIONS SAMSUNG wor SAMSUNG ELECTRONS products ave not signed for usin ite support applications, devices, o systems where maituntion of a SAMSUNG product can reasonably be expected to resutin a personal injury. SAMSUNG andor SANSUNGELECTRONICS customers using or seing SAMSUNG andr SAMSUNGELECTRONICS products for use in such applications 6040 a hei own risk and agree 1 uly indemrily SAMSUNG andr SAMSUNG ELECTRONIGS for any damages resuling in such Improper use olsale, ry +] 737 SAMSUNG Electronics