KS82C54

KS82C54 SAMSUNG | Alldatasheet

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FEATURES/BENEFITS DESCRIPTION « Ahigh performance device featuring pin and functional The KS82C54 is a countedtimer device that includes compatibility with the industry standard 8254 complete pin and functional compatibility with the industry standard 6254. Designed for fast 10MHz oper- « High Speed — 8AiHz and 10MHz versions ation, it has three independently programmable 16 bit * Low power CMOS implementation counters and six programmable counter modes. Counting «TTL input/output compatibility can be performed in both binary and BCD formats. The KS82C54 offers a very flexible, hardware solution to * Compatible with 8080/85, 8086/88, 80286/386 and the generation of accurate time delays in microprocessor G2OXGuP tamites systems. A general purpose, multi-timing element itcan © Fully static operation be used to implement event counters, elapsed time indicators, waveform generators plus a host of other © Three independent 16 bit counters functions. © Str programmable counter modes The low power consumption of the KS82C54 makes it * Status read-back command ideally sulted to portable systems or those with low power standby modes. It is manufactured using proven © Binary or BCD counting CMOS process technology to produce a solid, reliable product. mcc Tor vaew — seat fhe - ° j " if: our ode aba od? apm ogee nDba SG npav aoe »apPorn ecg = Doce we a Reee eT m= A cuKt eSsaerse - “toure () carey gee tees + our: - Figure ta: Plastic Leaded Chip Carrier ody ™ Pvc A= F a ooo ones = Hae 2h REGISTER me sBn > ou ~ P= Heal com Cis «Dare ours Cj sPox Gares Con «Dome: ‘ss Cle spon Figure 2: KS82C54 Block Diagram Figure 1b: 24-Pin Configuration eee eee eee SAMSUNG oo

KS82C54 PROGRAMMABLE INTERVAL TIMER rane Table 1a: 28-Pin PLCC Pin Assignment ‘Table 1b: 24-Pin DIP Pin Assignment [pina | vo [Pin Namel ein #[ vO [Pin Name] [Pin # | VO [Pin Name] Pin # | VO. [Pin Neme] [+1 [= [re fw | = fro | fs [vo fo [| o fours | [2 [vo for [| o four | [| 2 [vo foe [ w | 4 [carer | [3 [vo fos fw [i Joares | [3 [vo fos fos | ouxs | [4 [wo fos [we [ot fo | [4 | vo fo |e | 1 foarer | [5 [vo fo | [1 foaree | [| s [vo lm | w | o joure | [6 [vo jo | | o four | | 6 [vo [om | | joe | Lz [vo foe fa [it foe | [7 [vo ff [it || 2 pe [vo fo ja [s le | [8 [vo jo [ao] ia | Le [vo foo fat [a | [9 ft feuxo [a | fes | jo [ot feo fa fo jes | | | o fouro [a [1 [ao | Lu [= jrc [es [= [nc | [mw | i foareo [cs [1 [wa | [2 | 0 fouro | a ft fro | [we | = Wes fm [= Wee | | 3 [1 [eareo [a7 [ t [wr | Table 2: Pin Descriptions [Smmbor[Wwe[ SSSSSCS*C*‘UN me and Function | Ao, Ar Address: These two address pins are used to select the Control Word Register (for read or write operations), or one of the three counters. They are normally connected to the system address bus. [ar | Ao [Selec | [eo | [comers | [eo [2 [eames | [ro [+ [comers | [11+ [eon word Reaistr_| : | Seana signals. If CS is not LOW, RD and WR are ignored. [ecko | 1 [etock &: Clockinput of Gouri [ert | 1 | eteck t Clockinput of Comter. [eure | 1 | eteck 2 CiockinputofGouner@ [care [1 [ete Gateimput of Comer SSSCSC~* [caver | 1 [Gate Gateinput oor SSSSC*d SAMSUNG co Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER Table 2: Pin Descriptions (Continued) [Smo [tee [Nm Fon GaTe2 | 1 _| Gate 2: Gate input of Counter 2. [outo | © _| Output o: Output of Counter 0. [out: | © _| Output 4: Output of Counter 1. ouT2 |__| Output 2 Output of Counter 2. Read Controk: Active LOW control signal used to enable the KS82C54 for read operations by the CPU. ae Write Control: Active LOW control signal used to enable the KS82C54 to be written to by the CPU. [Vcc | —_| Power: SV + 10% DC Supply. [vss | = _| Ground: ov. FUNCTIONAL DESCRIPTION The KS82C54 is a versatile programmable interval timer/ Control Word Register counter designed for use in high speed 8, 16 and 32-bit Th n ‘ “ i‘ y e Control Word Register is a write only register that is microprocessor systems. It provides a means of gener- Selected by the read/write logic block when Ay and A, = ating accurate time delays in hardware that is fully sadly ; 1. When CS and WR are LOW, data is written into the software configurable. It can be treated as an array of /O. KS82C54 Control Word Regi ft he CPU he rts, with minimal software overhead. nro legister from 1 vial Ports, data bus buffer. Control word data is interpreted as a The internal structure of the KS82CS4 isillustratedinthe number of different commands which are used to block diagram of Figure 2. Major functional blocks program the various device functions. For example, include a data bus butfer, read/write logic, control word status information is available with the Read-Back register, and three programmable counters. Command, These are discussed further in the section on programming. Data bus Buffer Block The 8-bit, 3-state data bus buffer provides controllable, Counter Blocks bidirectional interface between the KS82C54 and the The KS82C54 contains three identical, independent microprocessor system bus. counter blocks. Each counter provides the same func- tions, but can be programmed to operate in different Read/Write Logic Block nodes relative to each other. A typical KS82C54 counter os q is illustrated in Figure 3, and contains the following The read/write logic block generates internal control functional elements: control logic, counter, output ‘signals for the different functional blocks using address latches, count isters and status ister. and contro! information obtained from the system. The a regi register. active LOW signals: CS, RD and WR are used to select The Control Logic provides the interface between the the KS82C54 for operation, readacounter,andwritetoa Counter Element, the program instructions contained in counter (or the control word register) respectively. CS_—_the Control Word Register and the external signals ‘must be LOW for RD or WR to be recognized. Note that CLKn, GATEn and OUTn. It also keeps the Status RD and WR must not be active at the same time. Register information current, controls the access of OL. The inputs Agand A; are used to select the Control Word an Re invert data bus, and the loading of CE Register, or one of the three counters that is to be written registers. to or read from (see Table 4). Agand A; connect directly The Counter Element (shown in the Figure 3 as CE, for to the corresponding signals of the microprocessor Counting Element) is a 16-bit presettable synchronous address bus, while CS is derived from the address bus. down counter. using either a linear select method, or an address decoder device. & SAMSUNG 208 Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER ‘The Output Latches (shown as OLyandOL,) providea programming, both CR bytes will be initialized to a mechanism whereby the CPU can read the current known zero state. This is important in the case where contents of the CE. These two §-bit latches (M for most one byte counts are programmed (either most significant significant byte and L for least significant byte) together or least significant byte,, co that the unused byte is form a 16-bit latch capable of holding the complete always zero, and won't Lo. up: the initial count value content of the CE. Note that this arrangement is also loaded into CE. used for communicating 16-bit values over the B-bit The status Register and Status Latch is used to hold the ‘al data bus. current contents of the Control Wort Register and the During normal operation, the contents of OL track with _status of the output and null count flag (see section on the contents of CE. When a Counter Latch Command is Programming). The contents of the Stztus Register must issued by the CPU toa particular counter, its OL latches _be latched to become available to the data bus, where the current value of CE so that it can be read by the CPU they can be read by the CPU. {the CE cannot be read directly). OL then returns to Note that the Control Word Registeris also shown in the 2 tracking with CE. Note that only one latch (OLwfollowed Counter block diagram. While not a part of the Counter by OL;)atatimeis enabled by thecounterscontrollogic. Element, its contents determine the functional operation ‘The Count Registers (shown as CRy and CR.) behave _of the counter, including mode selection programmed. as input latches to the CE, and provide a mechanism whereby the initial count value can be downloaded from OPERATIONAL DESCRIPTION the CPU to the CE. Similar in operation to OL, CR is controlled by the counter control logic. Whenatwo byte __The following operations are common to all modes. initial count is to be downloaded, it is transferred one - . Control Word: When a Control Word is written to a byte at a time across the internal KS82C54 data bus t0 Counter, all Control Logicis Reset, and OUT is initialized the appropriate register (CRy if the most significant to a known state. No CLK pulses are needed. byte, CR, otherwise). CE is loaded by transferring both bytes simultaneously from CR. Note that CR is the Gate: The GATE input is always sampled on the rising interface between CE and thedata bus, since CE cannot _edge of CLK. In modes 0, 2, 3, and 4 the GATE input is be accessed directly. level sensitive, and the logic level is sampled on the . rising edge of CLK. In modes 1, 2, 3, and 5 the GATE Both CRy and CR, are cleared automatically when the input is nising-edge sensitive. In these modes, a rising counter is programmed and a new initial countis tobe Jue of GATE (trigger) sets an edge sensitive flip-flop in written. Thus, regardless of the counters previous the Counter. This flip-flop is sampled on the next rising 7 edge of CLK, then is immediately reset. In this way, a Figure 3: Block Diagram of a Counter trigger will be detected no matter when it occurs and a high logic level does not have to be maintained until the next CLK pulse. A summary is given in Table 5. I Note that in Modes 2 and 3, the GATE input is both [eee] edge-and level-sensitive. if a CLK source other than the system clock is used in modes 2 and 3, GATE should be im pulsed immediately after the WR for a new count valve. [= ] Le | Counter: New Counts are loaded, with the largest a [| [| possible initial COUNT being 0; (equivalent to 2'6 for -— binary counting and 10 for BCD counting, as in Table3) Conon EL} reer enamel Counters decremented on the falling edge of CLK do not r | & stop when they reach zero. In Modes 0, 1, 4, and 5 the EAI Counters wrap around to the highest count (either FFFF hex for binary counting or 9999 for BCD counting), then. [ a | continue counting. Modes 2 and 3 are periodic; the ome Counters reload themselves with the initial count, then continue counting from there. cm om a a & SAMSUNG cor Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER a Table 3: MIN and MAX Initial Counts If both the Count and Status Registers of a counter are latched, the first read operation of that counter will Minimum return the latched status, regardless of which was Mode Count latched first. The next one or two reads (the counter can > 7 0 be programmed for one or two type counts) will return 1 the latched count. Subsequent reads will return an 1 ° unlatched count. Read and write operations are sum- marized in Table 4. 2 9 pos fe | PROGRAMMING THE Ksszcs4 | 4 | 1 o The KS82C54 is programmed by writing a Control Word 5 1 ° into the Control Word Register (selected by Ao, At, 1’) “ojsagunatonitozwior bie “prior bop coun and an initial count to the Counter to be written into. Ag Gis equivalent o 2 for binary counting and 10 for BCD counting. and A; are used to select the appropriate Counter. The “ble 4: Reid/Vitie Operations Summary format of the count depends on the Control Word used. [es Tao [wal a, | A Write Operation ‘As mentioned previously, programming of the KS82C54 [0 | + | 0 [0 | 0 write into Counter © | S pertormed in two steps: [0 | 1 | 0 | 4 | 0 [white into Counter 2 initial count can be written into the selected Counter. Peeacere 1 |Write Control Word © The initial count must follow the convention in the Control Word for the particular Counter; ie., LSB or fo}if[ol 0 [Read from Counter 0 MSB only or LSB and then MSB. [0 | o | 1 | 0 | 1 [Read trom Counter 1 The instruction sequence has to be followed as shown [0 | 0 | 1 | 1 | © |Read trom Counter 2 above, however, the sequence of programming the - Counter can be random, since every Counter has its 10 | 0 | 1 | 1 | 1 |No-Operation -state)| — Secciated Control Word Register. A new initial count fa [x|[x|x |x| No-Operation (3-Statey| may be written to the Counter without rewriting the Fo [1 [1 1x [x [No-Opertion (@-Sate)| ComMtolWord or that Counter. Ofcourse. thenew count or must follow the programmed count format. Table 5: Gate Pin Operations Summary Signal Status Modes Low, or Going Low Rising 1 + Initiates counting + Resets output after next clock 2 * Disables counting + Initiates counting + Enables counting + Sets output immediately high 3 + Disables counting + Initiates counting + Enables counting + Sets output immediately high [4 _ | « Disables counting = + Enables counting a & SAMSUNG eos Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER ee After a Control Word and intial count have been written, If a new count is written to the Counter during a one- the Counters armed. A trigger causestheCountertobe _shot pulse, the current one-shot is not affected unless. loaded and OUT to be set low on the next CLK pulse, _the Counter is retriggered. In this case, the new count starting the one-shot pulse. An initial count of N results is loaded into the Counter and the one-shot pulse in a one-shot pulse N CLK cycles long. Since the one- continues for the duration of the count. shotis retriggerable, OUT remains low for N CLK pulses after any trigger. The one-shot pulse can be repeated + Mode 2: Rate Generator nas no ofl on piraie Count into the counter.GATE This mode functions like a divide-by-N counter and is on OUT. typically used for generating Real Time Clock Interrupts. . OUT is initially high. When the initial count has decre- Figure 8 Mode 0 Timing mented to 1, OUT goes low for one CLK pulse, then high again. The Counter reloads the initial count and cw-1 .sB-4 the process is repeated. Mode 2 is periodic, with the Fon Ot on Ol same sequence repeated indefinitely. For an initial 2 count of N, the sequence repeats every N CLK cycles. o ANNAN GATE= 1 enables counting; GATE = 0 disables counting $$$ $$$ If GATE goes low during an output pulse, OUT is set our Sos ee high immediately. A trigger reloads the initial count into the Counter on the next CLK pulse; OUT goes low Jmletelmis[sletelslelal N CLK pulses after the trigger. Thus the GATE input can be used to synchronize the Counter. eww us83 wo Figure 9: Mode 1 Timing oo A ow use i a ln nO or Sp on AAU AU AU AU AU AU AUAUAuauy Inluledostelsietsts tal care ee cw-w tse-3tse-2 Cin OO Oe os eledmlmdedslelstslel sist ox DIN owe Leesa oa9— Cn our 1 I ok ANNAN Jmimim[mfsfolslsels tal gare Donon re ro py ww 7-— — Notes: These conventions apply to all mode timing diagrams. Iefutedede|otsledsieiedsl 1. Counters are programmed for binary (not BCD) counting and for syzirtatatrte reading/writing least significant byte (LSB) only 2. The counter is always selected (CS always low). Oe te Usa 2: GWatandsforContraWord; GW YOmeansaconialworaotxa, | LJ Jf hex is written to the counter 4. LSB is the Least Significant Byte of count. ox TON 5. Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the most significant oare TE byte. Since the counter is programmed to read/write only, the ‘most significant byte cannot be read. our Df 7a 1 6. N stands for an undefined count. Vertical tines show transitions between count valves Je[eiutulefole[slatal sisi < SAMSUNG on Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER a After a Control Word and intial count have been written, GATE = 1 enables counting; GATE = O disables counting. the Counter is loaded on the next CLK pulse. OUT goes If GATE goes low while OUT is low, OUT is set high low N CLK pulses after the initial count is written, which immediately (no CLK pulse is needed). A trigger reloads allows the Counter to be synchronized by software. the Counter with the initial count on the next CLK pulse. Writing a new count while counting does not affect the Thus the GATE input can be used to synchronize the a ‘ ounter. current counting sequence. Ifa trigger is received attera new count is written but before the end of the current The Counter is loaded on the next CLK pulse after a period, the Counter is loaded with the new count on the Control Word and initial count have been written. This next CLK pulse and counting continues from the new allows the Counter to be synchronized by software. count. Otherwise, the new count is loaded at the end of the 7 ne Writing a new count while counting does not affect the current counting cycle. In Mode2,a COUNT of lisillegal, ont Count ing sequence. Ita trigger is received after writing a new count but before the end of the current Mode 3 Square Wave Mode half-cycle of the square wave, the Counter is loaded with Mode 3is typically used for Baud rate generation, andis the new count on the next CLK pulse and counting similar to Mode 2 except for the duty cycle of OUT. OUT continues from the new count. Otherwise, the new count is initially high. When half the initial count has expired, is loaded at the end of the current half-cycle. OUT goes low for the remainder of the count. Mode 3 is also periodic, with the sequence above repeated indefi- wrote implemented 3s follows according towhether nitely. An initial count of N results in a square wave witha ever period of N CLK cycles. Figure 10: Mode 2 Timing Figure 11: Mode 3 Timing WR cw LSBs Ly we eo PUL Ca aUaUalaUabalaualaualauaual on mi ure our 7 letedmde[s dated sieysts | Jelmiefededeledslelsiersns ig] coew umes ews uss i eS ine Oe ex ANIA aU alaUabalalalaualaalaualal Gare een Gl ee ae a a, an anaes Va a our 7 LT ojojole oyoyoyo [mimdmfml eps isrsisiersreisisl lnluledmdsisfelstetelst ews nes owe LSBs isos ion ie on ae TT Sen Oe on Oe oO oe DP ex FU i ome our (mfulvfuleletetsistsieiststs| lwlululwefelsielelels ist Note: A gate transition should not occur one clock cycle prior to Note: A gate transition should not occur one clock cycle prior to reaching the terminal court (1). reaching the terminal count (TC) SAMSUNG ox Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER ee Even counts: OUT is initially high. The initial count is Mode 4: Software Triggered Strobe loaded on one CLK pulse and then decremented bytwo Gui initially high. When the initial count expires, OUT on succeeding CLK pulses. When the count expires, goes low for one CLK pulse and then goes high again OUT goes low and the counter is reloaded with the initial le tris a pers re The counting sequence is triggered by writing the initial count. The above process is repeated indefinitely. count, Odd counts: OUT is initially high. The initial count minus . 7 one (to"given an even number) is loaded on one CLK CATE pac napa counting: GATE = Odisables counting. pulse and then decremented by two on succeeding CLK pulses. One CLK pulse after the count expires, OUT The Counter is loaded on the next CLK pulse after a goes low and the Counter is reloaded with the initial Control Word and initial count have been written. This count minus one. Succeeding CLK pulses decrement CLK pulse does not decrement the count, so foran initial the count by two. When the count expires, OUT goes count of N, OUT does not strobe low until N+ 1 CLK high again and the Counter is reloaded with the initial pulses after the initial count is written. 2 count minus one. The above process is repeated indefi- a ae ae If a new count is written during counting, it is loaded on nitely. So for odd counts, OUT is high for (N + 1)/2 the noxt CLK pulse and courting onvinues from the Sounts and low for (N - 1)/2 counts. new count. If a two-byte count is written, the following events occur: Figure 12; Mode 4 Timing Figure 13: Mode § Timing ewan cw: ta_tsn +3 = LSS —_ in Ce ne oe SU ox DANN owe mi 7 _. our LS |e | lwledstelels Polo le edn ds ie] 81a Las Iselste[t]e 11818 | cwsts_sa- len oO ow ta tse in oe a UU ax UU nr GATE ee EY EEE | GATE a a Oa on wlelels}elelele [mda lodele leds deqsteterene) | Ue Pete tetstst stated ste ewe ase: tase ox PUAN ANN ra aWaUaalaealalalalala gare LITT myn ayynsonn oat on CON our LS Jmlefmtuim [si sles |mleigie| leleletelsieleisdelstal & SAMSUNG e9 Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER eee 1. Writing the first byte has no effect on counting, So, given an initial count of N, OUT does not strobe low 2. Writing the second byte allows the new count to be Util N + 1 CLK pulses after a trigger. loaded on the next CLK pulse. A trigger causes the Counter to be loaded with the initial This allows the sequence to be retriggered by software. Cownton she next cur pure. re iii hreurasliedi OUT strobes lowN+1CLK pulsesafterthenewcountof — etriggerable, so OUT will not go low unt Qean pulses after any trigger. GATE has no effect on OUT. Mode 5: If a new count is written during counting, the current : ; counting sequence will not be affected. If a trigger HARDWARE TRIGGERED strobe (Retriggerable). occurs after the new count is written, but before the OUT is initially high. Counting is triggered by a rising _ current count expires, the Counter will be loaded with edge of GATE. When the initial count has expired, OUT —_the new count on the next CLK pulse and counting will goes low for one CLK pulse, then goes high again. continue from there. After a Control Word and initial count has been written, the counter is loaded on the first CLK pulse following a trigger. This CLK puise does not decrement the count, Se TEE & SAMSUNG on Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER a Table 6: Recommended Operating Conditions Oe Spy Van peri Tempus Fane Powe Table 7: Absolute Maximum Ratings DG Supply Voltage Input, Output or /O Voltage Applied Vsg - 0.5V to Voc + 0.5V. Storage Temperature Range “65°C to 150°C. Maximum Package Power Dissipation re | 2 Note: Stresses beyond those listed above may cause permanent damage tothe device. These ae stress ratings only. and functional operation of the device at these or any other conditions beyond those indicated inthe operational sections of this specification fs not implied. Exposure to maximum rating conditions for extended periods may atfect device reliability Table 8 Capacitance (Ta = 25°C, Voc = OV, Vin = *5V oF Vss) [_symbot [Parameter [Test Conditions |p| Unt | [Co | [vO Capacitance | Capacitance FREQ | 20 | pF | | Gw | Input Capacitance | Snmeasured [oF | Cv__| Input Capacitance Unmeasured Pins Returned to Vsg [oor ea a Table 8: DC Characteristics (Tx = 0°C to 70°C, Voc = SV + 10%, Vsg = OV) [tee | vocSenyGuen [et ond curt [Wa Weg wo | oe] [oe TowpatPeat etage [r= Wee 0857 |= [0 [| [Vie Piet gh ete ane | [ve [inet ow ge fs] Output High Voltage Tow = —400uA lou = -2.5mA [Yor [output tow vonage tu sama | = Te P| ee & SAMSUNG os Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER NOTE Table 10: AC Characteristics (Tx = 0°C to 70°C, Voc = SV + 10%, Vsg = OV) Bus Parameters? ~ ~ Limits (@MHz) | Limits (10MHz) | mee | Parameter Test Conditions | min | Max | Min | Max | Units [uo | a yf os ep pee pe fe [tan _ | Address stable before RO! _ 4 [| — | 9 | — | ns | tw _ | Address stable before WR o | —|[o | =F 1s [rs [96 | son | 00 | we [tow | data sown time betore war || wo | | | | os [Te [ctocktantime | es fs | [as eis we ator co [www me [tau [Gatewatniow Pw | fs [Ces ene soup ne oe ae a a a a yr [Cem [tow pas wan [aw | = P| a [Tiana i are = Te [pose gg a a [Cow [6S soe pote ware ee | a [Ce [eucay arg oe [Cie | bast te ate Wa et ise [6a oy ersanaig | pp [ise | OUT aay to ae ie | Soe Lie [Wipe wer @[—-[e t-te Notes: 1. AC timings measured at Voy = 2.0V, Voy = 0.8V. 2. Inmodes 1 and, riggers are sampled on each rising clockedge. A second rigger within 120ns ofthe rising clock edge may not be detected (70ns for KS82C54-10). 3. Low-going glitches that violate tpn pwn. may Cause errors requting counter reprogramming, ee & SAMSUNG ore Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER Figure 14: Timing Diagrams 7: a) Write Timing = = as a i : oy b) Read Timing OS . nf + -t» "5 c) Recover Timing _ FR d) Clock and Gate Timing moe coum = = LS ow we pe cx fom} hae / al ee ee two foo “LAST BYTE OF COUNT BEING WRITTEN: & SAMSUNG e7 Electronics

KS82C54 PROGRAMMABLE INTERVAL TIMER eee PACKAGE DIMENSIONS Units: Inches om 1s 3a [ae oe 3 &——— 22/3 . - a TAT Ba 2 aig pS) Sete ine - 4 | Pood oe 100 - a3 so: oma lhe & oe yy Figure 15: Plastic Package Figure 16: PLCC Package ORDERING INFORMATION & PRODUCT CODE KS 82054 x X X SAMSUNG Packaging SEMICONDUCTOR P — Plastic DIP L — Plastic Leaded Chip Carrier (PLCC) Part Number Speed Temperature -8 8MHz C — Commercial (0°C to +70°C) -10 10MHz 1 — Industrial (-40°C to +85°C) packaging or processing requirements not covered by the standard product line, please contact the SAMSUNG MOS Products Group. ee & SAMSUNG ste Electronics