KS7212 SAMSUNG | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD GENERAL DESCRIPTION The KS7212 is a CMOS integrated circuit designed for making various timing pulses for B/W CCD camera.
FEATURES
- Compatible with both EIA and CCIR mode (EIA : KC73125(U)-M, CCIR : KC73129(U)-M) - Built in auto iris function (Electronic Exposure) - Mirror mode timing generation - Field interlace mode only - Timing and sync one chip IC - Oscillation frequency EIA : 19.06992MHz, CCIR : 18.93750MHz APPLICATION - B/W CCD Camera BLOCK DIAGRAM Device Package Operating Temperature KS7212 48-QFP-0707 -20~75°C High/Low Control 2 3 41 127 8 9 10 11 Shutter Speed ROM Shutter Speed Count Shutter Speed Control or Horizontal ROM F/F GATE2 Vertical ROM F/F GATE11/2 38 37 36 35 30 29 28 27 26 25 2433 CL TS1 TS0 PWR TS2 ϕH4 ϕH3 ϕH1 ϕH2 RG XSUB XV2 XV1 XSG1 XV3 XV4 XSG3 SHP SHD CLP1 CLP2 CLP3 DFDO CLEN WIN MD2 MD1 EE1 EE2 FLD PBLK CSYNC CBLK VD HD 48-QFP-0707
ORDERING INFORMATION
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD PIN DESCRIPTIONS No Symbol I/O Description Remark
1 MD2 I CCIR/EIA mode selection * Information (1)
2 MD1 I NORMAL/MIRROR mode selection * Information (1)
3 EE1 I EE mode control input 1 * Information (2)
4 EE2 I EE mode control input 2 * Information (2)
5 VSS1 - Ground
6 VDD1 - +5V
7 FLD O Field separation pulse
8 PBLK O Pre - blanking pulse
9 CSYNC O Composite Sync.pulse
10 CBLK O Composite Blanking pulse
11 VD O Vertical driving pulse
12 HD O Horizontal driving pulse
13 WIN O Window pulse
14 CLEN O 1/2 HD frequency pulse
15 DFDO O 1/2 VD frequency pulse
16 CLP3 O Clamp pulse 3 (Dummy black level)
17 CLP2 O Clamp pulse 2 (Optical black level)
18 CLP1 O Clamp pulse 1 (Optical black level)
19 VSS2 - Ground
20 VDD2 - +5V
21 SHD O Data Sample & Hold pulse
22 SHP O Pre - Charge Sample & Hold pulse
23 VSS3 - Ground
24 XV4 O Vertical transfer clock 4
25 XSG3 O Read out Pulse 3
26 V3 O Vertical transfer clock 3
27 XSG1 O Read out Pulse 1
28 XV1 O Vertical transfer clock 1
29 XV2 O Vertical transfer clock 2
30 XSUB O Shutter speed control for auto Iris
31 VDD3 - +5V
32 VSS4 - Ground
33 ϕRG O Reset gate pulse
34 VDD4 - +5V
35 ϕH2 O Horizontal transfer pulse 2 ( Mirror mode) 36 ϕH1 O Horizontal transfer pulse 1 ( Normal mode’H’) 37 ϕH3 O Horizontal transfer pulse 3 ( Normal mode’H2’) 38 ϕH4 O Horizontal transfer pulse 4 ( Mirror mode )
39 VSS5 - Ground
40 X1 I Oscillation clock Input EIA : 19,069928MIHz
CCIR : 18.93750MHz
41 X2 O Oscillation clock Output
42 VDD5 O +5V
43 CL O 1/2 Oscillation clock EIA : 9.953496Mhz CCIR : 9.46875MHz
44 VSS6 - Ground
45 TS2 I Test Input 2
46 TS1 I Test Input 1
47 TS0 I Test Input 0
48 PWR - Power On Reset
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD Information 1) MD2 and MD1 mode selection ( Pull - down ) Information 2 ) EE2 and EE1 shutter speed mode selection ( Pull- up ) ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD=5V, Ta=25°C, unless otherwise specified) MD2 MD1 MODE L EIA NORMAL H EIA MIRROR L CCIR NORMAL H CCIR MIRROR EE2 EE1 MODE L SHUTTER SPEED STOP H SHUTTER SPEED UP L SHUTTER SPEED DOWN H SHUTTER SPEED STOP Characteristics Symbol Value Unit Supply Voltage VCC 7 V Input Voltage VI VSS-0.5 ~ VDD+0.5 V Output Voltage VO VSS-0.5 ~ VDD+0.5 V Operating Temperature TOPR -20 ~ +75 °C Storage Temperature TSTG -55 ~ +150 °C Characteristics Symbol Test Condition Min Typ Max Unit Supply Voltage VDD - 4.75 5.0 5.25 V VIH - 0.7VDD - - V VIL - - - 0.3VDD V VOH1 IOH1=-2mA VDD-0.5 - - V VOL1 ICL1=4mA - - 0.4 V Output Voltage 2 VOH2 ICH2=-4mA VDD-0.5 - - V (CL, RG, SHP, SHD) VOL2 IOL2=3mA - - 0.4 V Output Voltage 3 VOH3 ICH3=-8mA VDD-0.5 - - V (H1, H2, H3, H4) VOL3 ICL3=8mA - - 0.4 V L L H H Input Voltage Output Voltage 1
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD AC CHARACTERISTICS twh tr tf twl 0.9VDD 0.1VDD10% 90% Unit twh twl tr tf XSG1 , XSG3 XV1 , XV2 , XV3 , XV4 H1 , H2 , H3 , H4 RG XSUB SHP , SHD , CLP1 , CLP2 , CLP3 , DFD0 , CLEN , WIN , HD , VD , CBLK , CSYNC , FLD us us ns ns us ns 2.3 1.5 2.5 2.0 26 32 0.5 0.015 0.5 16 13 0.5 0.5 0.24 PULSES
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD OPERATING PRINCIPLES & METHOD POWER ON RESET KS7212 has two reset methods. The one is power on reset and the other is normal reset. When user wants to use power on reset , which generates automatical reset signal that is needed to initialize the KS7212 internal system when power is on, user should be connect 1000pF capacitor at PWR ( pin 48 ) termial. Power on reset system has internal 100Kohm pull up resister. So , user can control reset signal timing when user changes value of capacitor , which is connected to PWR terminal. When user wants to use normal reset , user should be remove capacitor from PWR terminal , and supplies reset signal to PWR terminal. When use u-Com system , reset signal can be supplied three times and times of 1 signal should be larger than four times of CL clock. 48 48 840ns 1000pF RESET SIGNAL Fig. 1 POWER ON RESET Fig. 2 NORMAL RESET 2.4 ~ 2.6 V KS7212KS7212
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD APPLICATION CIRCUIT ( EIA , NORMAL mode ) VDD VDD TO CCD TO VERTICAL DRIVER X-tal 19.0699MHz TO SIGNAL PROCESSOR KS7212 252627282930313233343536 1 2 3 4 5 6 7 8 9 10 11 12 TIMING & SYNC GEN * Application circuit for normal mode EIA : 19.06992MHz CCIR : 18.93750MHz
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD HIGH SPEED TIMING RELATIONSHIP PG CCD OUT SHP SHD
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD 1.1uS 2.0uS 2.5uS39.5uS 2.5uS43.5uS HD XSG1 XSG2 ODD EVEN UNIT : mS CCD VERTICAL DRIVING PULSE TIMING DIAGRAM
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD 1/2H 6.36 10.76 4.89 1.47 2.45 26.89 4.86 UNIT uS HD HBLK HSYNC EQSYNC VSYNC ODD VD EVEN VD FLD
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD 1/2H 6.41 11.70 4.93 1.48 2.47 27.07 4.93 UNIT uS HD HBLK HSYNC EQSYNC VSYNC ODD VD EVEN VD FLD HORIZONTAL TIMING CHART FOR CCIR
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD 1/2H 6.36 10.76 4.89 2.45 26.89 4.86 UNIT uS HD HBLK HSYNC EQSYNC VSYNC ODD VD 2.724 CLP1 CLP2 CLP3 HORIZONTAL TIMING CHART FOR MIRROR EIA MODE
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD 1/2H 6.41 11.70 4.93 2.47 27.07 4.93 UNIT uS HD HBLK HSYNC EQSYNC VSYNC ODD VD 2.745 CLP1 CLP2 CLP3 HORIZONTAL TIMING CHART FOR MIRROR CCIR MODE
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD H1, H2, H3, H4, PG, SHP, SHD TIMING CHART AT MIRROR MODE OF CCIR OSC1 PG SHP SHD
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD EIA VERTICAL TIMING CHART FIELD E FIELD O 20H 80H HD VD CSYNC CBLK FLD WIN FIELD O FIELD E 20H 80.5H HD VD CSYNC CBLK FLD WIN
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD CCIR VERTICAL TIMING CHART FIELD E FIELD O 7.5H 25H 97H HD VD CSYNC CBLK FLD WIN FIELD O FIELD E 7.5H 25H 96.5H HD VD CSYNC CBLK FLD WIN
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD 520 525 260 265 270 275 280 285 290 491 492 492 493 FLD VD BLK HD XSG1 XSG2 CCD OUT CLP1 CLP2 CLP3 PBLK VERTICAL TIMING CHART FOR EIA 4 6 42 6 8 3 5 1 3 5 742 42 6 53 1 3 5
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD 620 625 310 315 320 325 330 340 582 581 582 583 FLD VD BLK HD XSG1 XSG2 CCD OUT CLP1 1 3 5 1 3 5 7 CLP2 CLP3 PBLK VERTICAL TIMING CHART FOR CCIR 335 1 3 5 42 6 42 6 1 3 5 4 6 42 6 8
KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD PACKAGE DIMENSION 0~8 0.13 + 0.10 - 0.05 0.10 MAX0.50 + 0.20
0.00 MIN
1.40 + 0.10
1.60 MAX
7.00 + 0.20 ( 0.75 ) 0.18 + 0.10
0.10 MAX
0.50 # 48 # 1 7.00 + 0.20 9.00 + 0.30 9.00 + 0.30 48-QFP-0707 unit : mm