KS5514B-XX SAMSUNG | Alldatasheet

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SAMSUNG ELECTRONICS CO. SPECIFICATION for KS5514B-XX JAN. 1998

The information in this publication has been carefully checked and is believed to be accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsun g reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such chan ges. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsun g makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any liability, including without limitation any consequence or incidental damages. *Typical* parameters can and do vary in different applications. All operating parameters, including *Typicals,* must be validated for each customer application by the customer*s technical experts. Samsun g products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsun g product could cause personal injury or death. Should the buyer purchase or use a Samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold Samsun g and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alle ges that Samsung was negligent regarding the design or manufacture or manufacture of said product.

  • ABSOLUTE MAXIMUM RATINGS --
  • ELECTRICAL CHARACTERISTICS -

CONTENTS

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 398-05-14 ON SCREEN DISPLAY PROCESSOR The KS5514B is a BICMOS LSI with on screen display function, sync. separator & expander function. 24 - SDIP - 300 FUNCTIONS

  • On screen display
  • Sync separator and sync detector
  • General expander

FEATURES

  • Character capacity : 240 ( 24 column /GD8 10 row )
  • Construction of character : 12 /GD8 18 dots
  • 128 kinds of character
  • Display position : 62 horizontal position : 64 vertical position
  • Character size : 4 /GD8 4 times of normal
  • Blinking : character unit
  • Background coloring : 8 colors
  • Synchronous ways : automatic selection internal or external synchronization via MICOM control
  • General output : 3 ports ( by serial data )
  • Built-in sync separator & sync detector
  • NTSC / PAL / SECAM mode
  • Clamp circuit BLOCK DIAGRAM

ORDERING INFORMATION

Device Package Operating Temprature KS5514B-XX 24-SDIP-300 - 20 ~ + 70 /GCE 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 OSD ROM OSD RAM DATA REGISTER ADDR REGISTER INPUT CONTROL DISPLAY OSC CLAMPSYNC DETECT VSYNC DET4FSC DISPLAY CONTROL BLUE BACK GENERATOR SHIFT REGISTERCONTROL REGISTER INTERNAL BIAS CKT SYNC SEP CLAMP VIDEO MIXER AFC DVDD P3 P2 SYD AFCR FSC AVDD CVOUT SCCR CVIN DGND SCK ACB OSCIN OSCOUT CSB SIN P1 CLAMPIN AGND LPF AFCFIL XT INXT OUT OPTION CODE INFORMATION Code No. Remark - 02 - 03 - 06 - 07 - 09 - 10 - 12 - 13 - 14 - 15 - 16 English English, Russian English Korean Korean, English English, German English, Arabic English Korean, English English, Chinese English, Russian, Arabic

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 498-05-14 PIN DESCRIPTION Pin No. Symbol I/O Function DGND SCK ACB OSCIN OSCOUT CSB SIN CLAMPIN AGND LPF AFCFIL CVIN SCCR CVOUT AVDD FSC AFCR SYD I I I O I I O I I I O I I O Digital Ground Serial clock input. When CSB pin is \L\ then serial data is inputted by micom. Hysteresis input. Auto clear pin. If \L\, then all circuit is reset. Built-in pull up resistor. Hysteresis input. LC oscillation pin. Standard frequency is 7MHz & the horizontal start position is controlled by the clock of oscillation block. While pin 6 is low, serial data input is active. Built - in pull up resistor Serial data input pin. Built-in pull up resistor General output port 1 Clamp input pin of composite video signal Analog ground Low pass filter AFC filter output Composite video signal input SECAM chroma input Composite video output : 2 Vp-p Analog VDD FSC input (Not use) VCO oscillation frequency control When sync signal is inputted, then SYD is high.

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 598-05-14 XT IN XT OUT DVDD I O O O PIN DESCRIPTION ( Continued ) X-TAL X-TAL General output port 2 General output port 3 Digital VDD ABSOLUTE MAXIMUM RATINGS ( Ta = 25/GCE ) Characteristics Symbol Value Unit Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature V DD V IN Pd Topr Tstg - 0.3 ~ 6.0 V SS - 0.3 /GF5 VIN /GF5 VDD + 0.3 300 - 20 ~ + 70 - 40 ~ + 125 V V mW /GCE /GCE Pin No. Symbol I/O Function

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 698-05-14 ELECTRICAL CHARACTERISTICS ( Ta = 25/GCE , AVDD = DV DD = 5V ) Characteristics Symbol Unit Operating Voltage Operating Voltage Operating Current Pin 12 DC Voltage Pin 13 DC Voltage AFC Freerun Frequency AFC Pulse Width AFC Delay Time AFC Lock Range H AFC Lock Rnage L AFC Capture Range H AFC Capture Rrange L SYNC DET. Lock Range H SYNC DET. Lock Range L SYNC DET. Capture Range H SYNC DET. Capture Range L V - SYNC Delay Time DV DD AV DD Icc Vpi2 Vpi3 Ffr twd td Falh Fall Fach Fac1 Flh Fll Fch Fc1 tvd Min Typ Max 3.5 4.5 2.3 1.3 15.5 3.7 1.0 +600 +400 143 6.7 100 14.3 5.0 5.0 2.5 1.45 15.7 4.0 2.5 153 7.7 107 15.3 5.5 5.5 2.7 1.6 15.9 4.3 4.0 -900 -700 163 8.7 114 16.3 V V mA V V KHz usec usec Hz Hz Hz Hz KHz KHz KHz KHz Oscillation Level Oscillation Frequency Blueback Sync Tip Level Blueback Pedestal Level Blueback Color Burst Level H Blueback Color Level H Vosc Fosc Vbst Vbpd Vbbh Vbch 4.0 6.3 1.85 2.5 2.75 3.1 4.5 7.0 2.05 2.7 2.95 3.3 5.0 7.7 2.25 2.9 3.15 3.5 usec Vpp MHz V V V V

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 798-05-14 OPERATION DESCRIPTION MEMORY STRUCTURE After KS5514B records, in DATA RAM and CONTROL REGISTER, the serial DATA that is inputted from MICOM, in recording to the V-SYNC and H-SYNC signal, mix the COMPOSITE VIDEO signal and the font ROM data that is mapped to data RAM. In case that there is no composite video signal that is inputted to KS5514B, the SYNC detector becomes low, KS5514B makes the blue back signal in dividing the 4fsc signal and the blue back signal is outputted. The following table is the data structure that is inputted from MICOM.

  • Memory address consists of 16 bit
  • The data of address 0 ~ 239 are character data which are display on the screen.
  • The address 240 ~ 244 are the control registers.
  • Don\`t care bit : the upper 8 bits (DA8 ~ DAF) in address 0 ~ address 239, the upper 5bits (DAB ~ DAF) in address 240 ~ address 244 Bit Addr 239 240 241 242 243 244 DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 * * * * * * * * B L I C 6C 5 C 4C 3C 2C 1 C 0 BLI INT/ NON HSZ HSZ HSZ HSZ HP5 HP4 HP3 HP2 HP1 HP0 BLI2 VSZ VSZ VSZ VSZ VP5 VP4 VP3 VP2 VP1 VP0 DSP DSP DSP RAM ERS TEST TC LEV LEV PH2 PH1 PH0 -L E BK LE CHA DSP ON BLK BLK BLI BLI EX YM BCO SECAM NT/ PAL - PD3 PD2 - PD0 PC3 PC2 PC1 PC0 C6 C5 C4 C3 C2 C1 C0 (Font ROM Address)

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 898-05-14 CONTROL REGISTER 1) Register 240 DA0 ~ DAA Register State Content Function A HP0 HP1 HP2 HP3 HP4 HP5 HSZ10 HSZ11 HSZ20 HSZ21 INT/ NON HS is horizontal display start position Tc : osc. period ( 1 / 7MHz = 143 nsec ) HSZ11 HSZ21 HSZ10 HSZ20 N 1st line 1X 2X 3X 4X 2nd ~ 10 th line 1X 2X 3X 4X Interlace Mode Non-interlace Mode Remark Horizontal Start Position 1st line character size control to horizontal- direction 2nd ~ 10th line character size con- trol to horizontal- direction HS = Tc * /G5E 4 * /GEA ( HPn * 2 ) + N /G60 n=o n HSZ10 HSZ11 HSZ20 HSZ21

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 998-05-14 2) Register 241 Register State Content Function A VP0 VP1 VP2 VP3 VP4 VP5 VSZ10 VSZ11 VSZ20 VSZ21 BLI2 VS is vertical start position H : horizontal synchronous pulse time 1X 2X 3X 4X Remark Vertical Start Position 1st line character size control to vertical direction 2nd ~ 10th line character size con- trol to vertical direction VSZ10VSZ11 1X 2X 3X 4X VSZ20VSZ21 V - SYNC 64 divide ( = 1 sec ) V - SYNC 32 divide ( = 0.5 sec ) HS VSV-SYNC H-SYNC VS = H * /G5E 4 * /GEA ( VPn * 2 ) + 3 /G60 n=o n Control the blink period DA0 ~ DAA

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 1098-05-14 Register State Content Function A PH0 PH1 PH2 LEVEL0 LEVEL1 TC TEST RAM ERS DSP1 DSP2 DSP3 Remark 3) Register 242 P2 P1 P0 NTSC PAL /G45 /2 7/G45 /4 /G45 3/G45 /4 3/G45 /2 5/G45 /4 /G45 /4 /G45 /2 -/G45 /4 /GB2 /G45 3/G45 /4 3/G45 /2 5 /G45 /4 level 0 level 1 Internal bias 1 Internal bias 2 Internal bias 3 1H = 454Tc 1H = 455Tc Tc = 2 / fosc Active mode Test mode RAM no erase RAM erase Display method of the 1st is fixed by BLK0 & BLK1 Display method of the 1st is variable Display method of 2nd - 9th is fixed by BLK0 & BLK1 Display method of 2nd - 9th is variable Display method of 10th is fixed by BLK0 & BLK1 Display method of 10th is variable Back ground color control bit Color level control 0 1 111 DA0 ~ DAA /G45 /4

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 1198-05-14 Register State Content Function A BCO YM EX BLI0 BLI1 BLK0 BLK1 DSP ON LECHA LEBLK Remark 4) Register 243 BLI1 BLI0 OFF DUTY 50% DUTY 25% DUTY 75% Blinking mode control BLK1 BLK0 OFF O C R Blanking mode control Display off Display on Character luminance level 1 Character luminance level 2 Blank luminance level 1 Blank luminance level 2 Blanking area coloring Full TV screen coloring The same luminance level character and back ground Variable background luminance level available External mode available Internal mode available Determined by BLK0 & BLK1 Determined by BCO, BLK0 & BLK1 Blinking duty control C : character O : outline R : raster DA0 ~ DAA

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 1298-05-14 Register State Content Function A Remark 5) Register 244 01PC0PC1 Port(PD0) output Character1 output 01PC2PC3 Hsync(pin22) & Vsync(pin23) output Port(PD2/PD3) output Character2, BLK2 output Test mode L output H output L output H output L output H output NTSC mode PAL mode NTSC or PAL mode SECAM mode Pin 8 output mode setting Pin 22/23 output mode setting Pin 8 output data setting Pin 22 output data setting Pin 23 output data setting Hsync+Vsync output - PC0 PC1 PC2 PC3 PD0 PD2 PD3 NT/ PAL SECAM DA0 ~ DAA

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 1398-05-14 TEST CIRCUIT DV DD VSYNC IN/OUT HSYNC IN/OUT SYD FSC AV DD CV OUT 1/GD3 100K CV IN D GND SCK ACB OSC IN OSC OUT 56p68p A SW1 B 10uH CSB SIN P1 CLAMP IN A GND LPF AFCFIL 4.7/GD3 + 200K 100p 104 0.47/GD3 AFCRXT INXT OUT 12K 0.82K0.82K 0.82K 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 OSD ROM OSD RAM DATA REGISTER ADDR REGISTER INPUT CONTROL

4 FSC

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 1498-05-14 APPLICATION CIRCUIT (APP-082) The circuit drawn above is for Demo Board.

  • Y101 (4fsc X-TAL ) /GE2 NTSC : 14.31818MHz PAL : 17.734475MHz
  • C139 / C140 : The load CAP of X-TAL Y101 has a difference each according to its manufacturer. SYD D GND SCK ACB OSC IN OSC OUT 82p68p 10uH CSB SIN P1 CLAMPIN A GND LPF AFCFIL 4.7/GD3 200K 100p 122 1K 0.33/GD3 P3 P2 AFCR 104 FSC + 100/GD3 1/GD3 100K CV IN 1/GD3 + XT INXT OUT 100 1N4148 CR104 CR105 100uH VIDEO OUT 430 +220/GD3 A733 R100 C138 DC 2.5V Vin : 2Vpp Vsync: > 0.3Vpp KA78T05 100uH SECAM VIDEO IN L105 DV DD C139 C140 C152 203 R175 12K C143 C144 L104 Q116 R176 Q116 C153 R177 R172 R174 C150 C149C148R173C137C141 L106 C142 C147 CVOUT Y101 D GND A GND 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 OSD ROM OSD RAM DATA REGISTER ADDR REGISTER INPUT CONTROL

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 1598-05-14 APPLICATION CIRCUIT (APP-306) * Control Program : osd-3.exe The circuit drawn above is for Demo Board.

  • Y102 (4fsc X-TAL ) /GE2 NTSC : 14.31818MHz Y103 (4fsc X-TAL ) /GE2 PAL : 17.734475MHz SYD D GND SCK ACB OSC IN OSC OUT 82p68p 10uH CSB SIN CLAMPIN A GND LPF AFCFL 4.7/GD3 200K 100p 122 1K 0.33/GD3 P3 P2 AFCR 203 FSC 100/GD3 1/GD3 100K CV IN 1/GD3 + XT INXT OUT 100 1N4148 100uH 12K VIDEO OUT 430 +220/GD3 A733 R100 C138 DC 2.5V Vin : 2Vpp Vsync: > 0.3Vpp KA7805 100uH SECAM VIDEO IN L105 DV DD C152 R175 C144 L104 Q116 R176 Q115 C153 R177 R172 R174 C150 C149C148R173C137C141 L106 C142 C147 CVOUT Y102 14.31818MHz Y103 17.734475MHz C154 15pF C155 47pF KSR1001 KSR2001 C157 47pF To Pin 20 ( XT IN ) To Pin 21 ( XT OUT ) R101 CR104 CR105 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 OSD ROM OSD RAM DATA REGISTER ADDR REGISTER INPUT CONTROL

KS5514B -XX ON SCREEN DISPLAY PROCESSOR SPECIFICATION 1698-05-14 PACKAGE DIMENSIONS 24-SDIP-300 Dimensions in Milimeters/Inches

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