KS51850

KS51850 SAMSUNG | Alldatasheet

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2 KS51850

KS51850, a 4-bit single-chip CMOS microcontroller, consists of the reliable SMCS-51 CPU core with on-chip ROM and RAM. Eight input pins and 11 output pins provide the flexibility for various I/O requirements. Auto reset circuit generates reset pulse every certain period, and every halt mode termination time. The KS51850 microcontroller has been designed for use in small system control applications that require a low-power, cost - sensitive design solution. In addition, the KS51850 has been optimized for remote control transmitter and has built-in Transistor for I.R.LED drive.

FEATURES

• 1,024 bytes RAM Size
• • 32 nibbles Instruction Set
• • 39 instructions Instruction Cycle Time
• • 13.2 µsec at fxx = 455 kHz Input Ports
• • Two 4-bit po rts (24 pins)/one 4-bit, Five1-bit ports (20 pins) Output Ports
• • One 4-bit, Seven 1-bit ports (24pins)/One 4-bit, Five 1-bit ports (20 pins) Built-in Oscillator
• • Crystal/Ceramic resonator Built-in Reset Circuit
• Power-on reset and auto reset circuit for generating reset pulse every 13.1072/fxx (288 ms at fxx = 455 kHz) Four Transmission Frequencies
• • fxx/12 (1/4 duty), fxx/12 (1/3 duty), fxx/8 (1/2 duty), and no-carrier frequency Built-in Transistor for I.R.LED Drive
• IOL1 : 210 ma (typical) at V DD = 3V and V O = 0.4V Supply Voltage
• • 1.8 V-3.6 V (250 kHz ≤ f OSC ≤ 3.9 MHz) 2.2 V-3.6 V (3.9 MHz < f OSC ≤ 6 MHz) Power Consumption
• • Halt mode: 1 µA ( maxium)
• • Normal mode: 0.5 mA (typical) Operating temperature Package Type
• • 24 SOP, 20 DIP, 20 SOP Oscillator Frequency divide select
• • Mask Option = fxx f OSC or f OSC /8

P1.0 - P1.3 P0.0 - P0.3 P3.0 - P3.3 P3 Output Register (PR) ALU & A H RAM

16 X 2 X 4bits L Decoder

Internal P2.9 and P2.10 Internal P2.13 Internal P2.0 P2.1 - P2.6 fXX /8 (1/2) fXX /12 (1/3) fXX /12 (1/4) No Carrier Internal P2.12 P2.0/REM HALT DIV OSC X I X O Auto Reset MUX PB SF PA PC

64 X 16 X 8 bits

Figure 2-1. Block diagram

PIN CONFIGURATION (24 SOP) KS51850 (Top View) V SS X I X O P2.6 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 V DD P2.0/REM TEST P2.1 P2.2 P2.3 P2.4 P2.5 P3.0 P3.1 P3.2 P3.3 Figure 2-2. Pin Configuration (24 SOP) Table 2-1. PIN Description for 24 PINS Pin Name Pin Number Pin Type Description I/O Circuit Type P0.0-P0.3 5, 6, 7, 8 Input 4-bit input port when P2.13 is low A P1.0-P1.3 9, 10, 11, 12 Input 4-bit input port when P2.13 is high A P2.0 REM 23 Output 1-bit individual output for remote carrier frequency (1) B P2.2-P2.5 20, 19, 18, 17 Output 1-bit individual output port C P2.1, P2.6 21, 4 D P3.0-P3.3 16, 15, 14, 13 Output 4-bit parallel output port C TEST 22 Input Input pin for test (Normally connected to V SS ) – X I 2 Input Oscillation clock input – X O 3 Output Oscillation clock output – V DD 24 – Power supply – V SS 1 – Ground – NOTES: 1. The carrier can be selected by software as fxx/12 (1/3 duty), fxx/12 (1/4 duty), fxx/8 (1/2 duty), or no-carrier frequency. 2. Package type can be selected as 24 SOP in the ordering sheet.

PIN CONFIGURATION (20 DIP, 20 SOP) V SS X I X O P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P3.3 KS51850 (Top View) V DD P2.0/REM TEST P2.1 P2.2 P2.3 P2.4 P3.0 P3.1 P3.2 Figrue 2-3. Pin Configuration (20 DIP, 20 SOP) Table 2-2. Pin Description for 20 Pins Pin Name Pin Number Pin Type Description I/O Circuit Type P0.0-P0.3 4, 5, 6, 7 Input 4-bit input port when P2.13 is low A P1.0-P1.1 8, 9 Input 2-bit input port when P2.13 is high A P2.0/REM 19 Output 1-bit individual output for remote carrier frequency (1) B P2.2-P2.4 16, 15, 14 Output 1-bit individual output port C P2.1 17 D P3.0-P3.3 13, 12, 11, 10 Output 4-bit parallel output port C TEST 18 Input Input pin for test (Normally connected to V SS ) – X I 2 Input Oscillation clock input – X O 3 Output Oscillation clock output – V DD 20 – Power supply – V SS 1 – Ground – NOTES: 1. The carrier can be selected by sofrware as fxx/12 (1/3 duty), fxx/12 (1/4 duty), fxx/8 (1/2 duty), or no-carrier frequency. 2 Package type can be selected as 20 DIP, or 20 SOP in the ordering sheet.

Table 2-3. Absolute Maximum Ratings Parameters Symbols Ratings Units Supply Voltage V DD - 0.3 to 6 V Input Voltage V I - 0.3 to V DD + 0.3 V Output Voltage V O - 0.3 to V DD + 0.3 V Soldering Temperature T SLD 260 (10 sec) °C Storage Temperature T STG - 55 to 125 °C Table 2-4. DC Characteristics (V DD = 3 V, TA = 25 °°c) Parameters Symbols Test Conditions Min Typ Max Units Supply Voltage V DD 250kHz ≤ f OSC ≤3.9MHz 1.8 3.0 3.6 V 3.9MHz< f OSC ≤6MHz 2.2 3.0 3.6 Operating Temperature T A – -20 – 85 °C High-Level Input Voltage V IH1 All input pins except X IN

0.7 V DD – V DD V

V IH2 X IN V DD -0.3 – V DD V Low-Level Input Voltage V IL1 All input pins except X IN 0 – 0.3 V DD V V IL2 X IN 0 – 0.3 V Low-Level Output Current P2.0 IOL1 V O = 0.4 V 180 210 240 mA V O = 0.5 V 220 260 300 Low-Level P3 Output IOL2 V O = 0.4 V 0.5 1.0 2.0 mA

Table 2-4. DC Characteristics (V DD = 3 V, TA = 25 °°c) (Continued) Parameters Symbols Test Conditions Min Typ Max Units High-Level Input Leakage Current ILIH1 V I = V DD – – 3 uA All input pins except X IN ILIH2 X IN – 3 10 Low-level Input Leakage Current ILIL1 X IN -0.6 -3 -10 High-level Output Leakag Current ILOH V O = V DD – – 1 uA All output pins Port 2,3 Pull-up Resistance of Input Port R V DD = 3 V 30 70 150 K Ω V I = 0 V Average Supply Current IDD V DD = 3 V – 0.5 1.0 mA Crystal/Resonator Non-divide option f OSC = 1 MHz Dvide-8 option f OSC = 6 MHz HALT Current IDDH f OSC = 0 – – 1.0 uA Clock Frequency fxx Crystal/Ceramic 250 – 1000 kHz Oscillator Frequency f OSC Crystal/Ceramic 250 – 1000 Non-divide option Crystal/Ceramic 2000 6000 Divide-8 option

The 10-bit register points one of 1024 bytes at addresses 0000H to 0F3FH. After reset, it points to 0FXXH for execution in the first instruction cycle. it then becomes 0F00H in the next instruction cycle. ROM Address 000 03F 100 13F 200 300 23F 33F 400 43F 500 53F 600 0F00 0F3F 0FFF RESET Address : Not built-in chip Page 0 Page 1 Page 4 Page 3 Page 2 Page 15 Page 5 Figure 2-10. KS51840 Program Memory Map

DATA MEMORY (RAM) The KS51850’s data memory consists of a 32-nibble RAM which is organized into two files of 16 nibbles each (See Figure 2-12). RAM addressing is implemented by a 7-bit register, HL. It’s upper 3-bit register (H) selects one of two files and its lower 4-bit register (L) selects one of 16 nibbles in the selected file. Instructions which manipulate the H and L registers are as follow: Select a file : MOV H,#n ; H ← #n, where n must be 0,4 NOT H ; Complement MSB of H register Select a nibble in a selected file : MOV L,A ; L ← A MOV L,@HL ; L ← M(H,L) MOV L,#n ; L ← #n, where 0 ≤ n ≤ 0FH INCS L ; L ← L + 1 DECS L ; L ← L - 1 RAM Address File 4 File 0 : Not built-in chip 3-bit 4-bit L The 7-bit HL register pair points to one of the 32 nibbles. H register selects one of two files; 0, 4 L register selects one of 16 nibbles; 0 to 0FH After reset, the HL register pair becomes to unknown state. H Figure 2-11. KS51840 Data Memory Map

Arithmetic Logic Unit (ALU), Accumulator (A) The SMCS-51 CPU contains an ALU and its own 4-bit register (accumulator) which is the source and destination register for most I/O, arithmetic, logic, and data memory access operations. Arithmetic functions and logical operations will set the status flag (SF) to “0” or “1” Status Latch (SL) The Status latch (SL) flag is an 1-bit flip-flop register. Only the “CPNE L,A” instruction can change the value of SL. If the result of a “CPNE L,A” instruction is true, the SL is set to “1”; If not true, to “0”. Status Flag : SF The Status Flag (SF) is a 1-bit flip-flop register which enables programs to conditionally skip an instruction. All instructions, including JP and CALL, are executed when SF is “1”. But if SF is “0”, the program executes NOP instruction instead of JP or CALL and resets SF to “1”. Then, program execution proceeds. The following instructions set the SF to “0”:

• • Arithmetic Instr uctions ADDS A,#n ; if no carry ADDS A,@HL ; if no carry INCS A,@HL ; if no carry INCS A ; if no carry INCS L ; if no carry SUBS A,@HL ; if borrow DECS A,@HL ; if borrow DECS A ; f borrow DECS L ; if borrow
• • Compare Instructions CPNE @HL,A ; if M(H,L) = (A) CPNZ @HL ; if M(H,L) = 0 CPNE L,#n ; if (L) = #n CPNE L,A ; if (L) = (A) CPNE A,@HL ; if (A) > M (H,L) CPNZ P0 ; if (P0) = 0 CPBT @ HL.b ; if M( H,L,b) ≠ 1
• • Data Transfer Instructions MOV @HL+,A ; if no carry MOV @HL- ,A ; if borrow
• • Logical Instructions NOTI A ; if (A) ≠ 0 after operation

INPUT PORTS : P0, P1 The P0 and P1 input ports have internal pull-up 30-150 K Ω resistors, (See I/O circuit type A), each multiplexed to a common bus (See Figure 2-15). If the P2.13 pin is programmed to low, then port 0 is selected as the input port. Otherwise, if the P2.13 pin high, port 1 is selected. Common BusMUX P0.0-P0.3 P2.13 (Internal) P1.0-P1.3 Figure 2-14. KS51850 Input Port OUTPUT PORTS : P2, P3 The P2 and P3 output ports can be configured as N-CH. Transistor (P2.0/REM only) and open drain (P2.1-P2.6, P3.0-P3.3) as follows: (see I/O Circuit Type B). P2.0/REM becomes floating state in halt mode.

• • N-channel open drain : An N-channel transistor to ground, compatible with CMOS and TTL. (see I/O Circuit Type C and D).
• • SETB P2.(L) : Set port 2 bits to correspond to L-register contents.
• CLRB P2.(L) : Clear port 2 bits to correspond to L-register contents. P3 output pins P3.0-P3.3 are parallel output pins. For the KS51850, only the 4-bit accumulator outputs its value to the P3 port by the output instruction “OUT P3, @SL+ A” (the value of the Status Latch (SL) does not matter).

TRANSMISSION CARRIER FREQUENCY One of four carrier frequencies can be selected and transmitted through the P2.0/REM pin by programming the internal P2.9, P2.10 and P2.0 pins (See Table 2-5). Figure 2-16 shows a simplified diagram of the various transmission circuits. Table 2-5. Carrier Frequency Selection Table P2.10 P2.9 Carrier Frequency of P2.0/REM Pin 0 0 fxx/12, 1/3 duty 0 1 fxx/8, 1/2 duty 1 0 fxx/12, 1/4 duty 1 1 No carrier

Internal P2.9 fXX /8, 1/2 Duty fXX /12, 1/3 Duty fXX /12, 1/4 Duty V DD (No Carry) Internal P2.10 Internal P2.0 P2.0/REM I.R.LED Drive Transistor *P2.0 System Clock Frequency Internal P2.0 *P2.0 (f XX /12, 1/3 duty) *P2.0 (f XX /8, 1/2 duty) *P2.0 (No carry) *P2.0 (f XX /12, 1/4 duty) Figure 2-15. Diagram of Transmission Circuits

All reset operations are internal in the KS51850. It has an internal power-on reset circuit consisting of a 7 pF capacitor and a 1 M Ω resistor (See Figure 2-19). The controller also contains an auto-reset circuit that resets the chip every 131,072 oscillator clock cycles (288 ms at a fxx = 455KHz clock frequency). The auto-reset counter is cleared by the rising edge of a internal P2.0 pin, by HALT, or by the power-on reset pulse (See Figure 2-20). Therefore, no clocks are sent to the counter and the time-out is suspended in HALT mode. When a reset occurs during program execution, a transient condition occurs. The PA register is immediately initialized to 0FH. The PC, however, is not reset to 0H until one instruction cycle later. For example, if PC is 1AH when a reset pulse is generated, the instruction at 0F1AH is executed, followed by the instruction at 0F00H. After a reset, approximately 13 msec is needed before program execution proceeds (assuming fxx = 455 KHz ceramic oscillation). Upon initialization, registers are set as follows:

• • PC register to 0 in next instruction cycle
• • PA and PB registers to 0FH (15th page)
• • SF and SL registers to 1
• • HL registers to unknown state low.

1 M Ω

Figure 2-18. KS51850’s Power-on Reset Circuit

2.30 ± 0.2

2.70 MAX

( )0.69

15.74 MAX

15.34 ± 0.2

0.05 MIN

NOTE : Dimensions are in millimeters. 1.270.38 ± 0.1 #24 #12 #13 10.30± 0.30 7.50 ± 0.2 0-8 0.85 ± 0.2 9.53 0.15 +0.10 0.05_

0.10 MAX

Figure 2-21. 24 SOP-375

2.30 ± 0.2

13.14 MAX

12.74 ± 0.2 NOTE : Dimensions are in millimeters. #20 10.30± 0.30 7.50 ± 0.2 0-8 0.85 ± 0.2 9.53 0.20 +0.10 0.05_#10 #11 Figure 2-22. 20 SOP-375

NOTE : Dimensions are in millimeters. 1.70 ± 0.2 1.14

14.10 MAX

13.70 ± 0.2 5.40 ± 0.2 0-8 0.60 ± 0.2 7.62 0.20 +0.10 0.05_ 7.80 ± 0.30 #20 #11 #1 #10 Figure 2-23. 20 SOP-300

#20 6.40 ± 0.2 7.62 #10 #11 0.25 +0.1 0.05_ 0-15 3.25 ± 0.2

5.08 MAX

26.80 MAX

26.40 ± 0.2

0.51 MIN

NOTE : Dimensions are in millimeters. 1.27 3.30 ± 0.3 1.52 ± 0.1 0.46 ± 0.1 ( )1.77 Figure 2-24. 20 DIP-300A

V O (Volt) V DD = 1.8 V V DD = 2.2 V V DD = 3.0 V IOL1 (mA) Ta = 25 c Figure 2-25. I OL1 vs V O (Port 2.0)

V O (Volt) V DD = 3.0 V IOL1 (mA) Ta = 25 c Figure 2-26.I OL1 vs V O (Port 2.1-2.3)

V O (Volt) V DD = 3.0 V IOL1 (mA) Ta = 25 c Figure 2-27. I OL1 vs V O (Port 3.0-3.3)

3 INSTRUCTION SET

Abbreviations and symbols table specifies internal architecture, instruction operand and operational symbols. As mentioned before, JP and CALL instructions are executed normally only when SF is high. If SF is low, the program executes NOP instruction instead of them and sets SF to high. And then, the program executes a next instruction. In addition, JPL and CALL are long jump and long call instructions which consists of PAGE and JP/CALL instructions. Table 3-1. Abbreviations and Symbols Symbol Description Symbol Description L L register (4 bits) SF Status Flag A Accumulator (4 bits) P3 P3-output (L) The contents of the L register P0 P0 input (4 bits) (A) The contents of the accumulator D Any binary number SL Status latch (1 bit) DST Destination operand PB Page buffer register (4 bits) C Carry Flag PA Page address register (4bits) SRC Source operand P2 P2-output REG Register PC Program counter ← Transfer SR Stack register + Addition or increment by 1 H H register ≤ Equal or less than M RAM addressed by H and L registers ( ) The complement of the contents (H) The contents of the H register @ Indirect register address prefix M (H,L) The contents of the RAM addressed by H,L #n Constant n (immediate 3or 4-bit data) b Bit address of the RAM [(H,L)] addressed by H,L ↔ Is exchanged with ≠ Not equal to − Subtract or decrement by 1

Table 3-2. Instruction Set Summary Mnemonic Operand Description MOV Instructions MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVZ XCH PAGE L,A A,L @HL,A A,@HL L,@HL @HL+,A @HL-,A L,#n H,#n @ HL+,#n @HL,A @HL,A Move A to register L Move L register to A Move A to indirect data memory Move indirect data memory to A Move indirect data memory to register L Move A to indirect data memory and increment register L Move A to indirect data memory and decrement register L Move immediate data to register L Move immediate data to register H Move immediate data to indirect data memory and increment register L Move A to indirect data memory and clear A Exchange A with indirect data memory Set PB register to n Program Control Instructions CPNE CPNZ CPNE CPNE CPLE CPNZ CPBT JP CALL RET @HL,A @HL L,A L,#n A,@HL @ HL,b dst dst Compare A to indirect data memory and set SF if not equal Set SF if indirect data memory Compare A to register L, set SF and SL if not equal Compare immediate data to register L and set SF if not equal Set SF if A is less than or equal to indirect data memory Set SF if A is less than or equal to indirect data memory Test indirect data memory bit and set SF if indirect bit is one Jump if SF flag is set Call subroutine if SF is set Return from subroutine I/O Instructions SETB CLRB IN OUT P2.(L) P2.(L) A,P0 P3,@SL+A Set bit Clear bit Input P0 to A Output A to P3-PLA output port Logical Instructions NOTI NOT CLR A H A Complement A and increment A Complement MSB of H register Clear Arithmetic Instructions ADDS ADDS SUBS INCS INCS INCS DECS DECS DECS A,@HL A,#n A,@HL A,@HL L A A A,@HL L Add indirect data memory to A Add immediate data to A Subtract A from indirect data memory Increment indirect data memory and load the result in A Increment register L Increment A Decrement A Decrement indirect data memory and load the result in A Decrement register L Bit Manipulation Instruction SETB CLRB @ HL.b @ HL.b Set indirect data memory bit Clear indirect data memory bit

Lower Nibble (Hex)Upper Nibble (Hex) CPNE @HL,A CPLE A,@HL CPNE L,A XCH @HL,A DECS L INCS L ADDS A,@HL DECS A,@HL IN A,P0 NOT H OUT P3,@SL+A CLRB P2.(L) SETB P2.(L) CPNZ RET PAGE MOV L,A MOV A,@HL MOV L,@HL MOV A,L MOV @HL-,A MOV @HL+,A MOVZ @HL,A MOV @HL,A MOV H,#n SETB @HL.b CLRB @HL.b CPBT @HL.b MOV L,#n MOV @HL+#N INCS A JP JP JP JP CALL CALL CALL CALL CPNE L,#n SUBS A,@HL NOTI A INCS A,@HL CPNZ @HL ADDS A,#n DECS A ADDS A,#n CLR A 0 1 3 4 5 62 8 9 A B C D E F7 A B C D E F Figure3-1. KS51 Opcode Map

MOV L,A Binary Code: 0 0 1 0 0 0 0 0 Description: The contents of the accumulator are moved to register L. The contents of the source operand are not affected. Operation: (L) ← (A) Flags: SF : Set to one SL : Unaffected Example: CLR A ; Clear the contents of A MOV L,A ; Move 0H to REG L MOV A,L Binary Code: 0 0 1 0 0 0 1 1 Description: The contents of register L are moved to the accumulator. The contents of the source operand are not affected. Operation: (A) ← (L) Flags: SF : Set to one SL : Unaffected Example: MOV L,#3H ; Move 3H to REG L MOV A,L ; Move 0H to A MOV @HL,A Binary Code: 0 0 1 0 0 1 1 1 Description: The contents of the accumulator are moved to the data memory whose address is specified by registers H and L. The contents of the source operand are not affected. Operation: M [(H,L)] ← (A) Flags: SF : Set to one SL : Unaffected Example: CLR A ; Clear the contents of A MOV H,#0H ; Move 0H to REG H MOV L,#3H ; Move 3H to REG L MOV @HL,A ; Move 0H to RAM address 03H

MOV A,@HL Binary Code: 0 0 1 0 0 0 0 1 Description: The contents of the data memory addressed by registers H and L are moved to accumulator. The contents of the source operand are not affected. Operation: (A) ← M [(H,L)] Flags: SF : Set to one SL : Unaffected Example: Assume HL contains 04H MOV A,@HL ; Move contents of RAM addressed 04H to A MOV L,@HL Binary Code: 0 0 1 0 0 0 1 0 Description: The contents of the data memory addressed by registers H and L are moved to register L. The contents of the source operand are not affected. Operation: (L) ← M [(H,L)] Flags: SF : Set to one SL : Unaffected Example: Assume Hl contains 04H MOV L,@HL ; Move contents of RAM address 4H to REG L CPNE L,#5H ; Compare 5H to REG L values JP XX ; jump to XX if REG L value is not 5H JP YY ; Jump to YY if REG L value is 5H MOV @HL+,A Binary Code: 0 0 1 0 0 1 0 1 Description: The contents of the accumulator are moved to the data memory addressed by registers H,L; L register contents are incremented by one. The contents of the source operand are not affected. Operation: M [(H,L)] ← (A), L ← L + 1 Flags: SF : Set if carry occurs; cleared otherwise SL : Unaffected Example: MOV H,#0H MOV L,#0FH CLR A MOV @HL+A ; Move 0H to RAM address 0FH and increment REG L value by one JP PRT ; jump to PRT, since there is a carry from increment

MOV @HL-A Binary Code: 0 0 1 0 0 1 0 0 Description: The contents of accumulator are moved to the data memory addressed by registers H,L; L register contents are decremented by one. The contents of the source operand are not affected. Operation: M [(H,L)] ← (A), L ← L - 1 Flags: SF : Set if no borrow; cleared otherwise SL : Unaffected Example: MOV H,#0H MOV L,#3H CLR A MOV @HL-,A JP ABC MOV L,#N Binary Code: 0 1 0 0 d d d d Description: The 4-bit value specified by n (data) is loaded into register L. The contents of the source operand are not affected. Operation: (L) ← #n Flags: SF : Set to one SL : Unaffected Example: MOV L,#8H ; 8H is moved to REG L MOV H,#n Binary Code: 0 0 1 0 1 d d d Description: The 3-bit value specified by n (data) is moved to register H. The contents of the source operand are not affected. Operation: (H) ← #n Flags: SF : Set to one SL : Unaffected Example: MOV H,#4H ; 4H is moved into REG H

MOV @ HL+,#n Binary Code: 0 1 1 0 d d d d Description: The 4-bit value specified by n (data) is moved to data memory addressed by registers H,L; L register contents are incremented by one. The contents of the source operand are not affected. Operation: M [(H,L)] ← #n, L ← L + 1 Flags: SF : Set to one SL : Unaffected Example: MOV H,#0H MOV L,#7H MOV @HL+,#9H ; Move 9H to RAM address 07H and increment REG L value by one, then REG L contains 8H MOVZ @HL,A Binary Code: 0 0 1 0 0 1 1 0 Description: The contents of the accumulator are moved to the data memory addressed by registers H,L; accumulator contents are cleared to zero. Operation: M [(H,L)] ← (A), (A) ← 0 Flags: SF : Set to one SL : Unaffected Example: MOV L,#3H MOV A,L MOVZ @HL,A ; Move 3H to indirect RAM and clear A to zero MOV L,A ; Move 0H to REG L SETB P2.(L) ; Set P2.0 to 1 XCH @HL,A Binary Code: 0 0 0 0 0 0 1 1 Description: This instruction exchanges the contents of the data memory addressed by registers H and L with the accumulator contents. Operation: M [(H,L)] ↔ (A) Flags: SF : Set to one SL : Unaffected Example: MOV H,#0H MOV L,#6H CLR A ; Clear A to zero ADDS A,#5H ; Add 5H to A XCH @HL,A ; Exchange 5H with contents of RAM address 06H

PAGE #n Binary Code: 0 0 0 1 d d d d Description: The immediate 4-bit value specified by n (data) is loaded into the PB register. Operation: (PB) ← #n Flags: SF : Set to one SL : Unaffected Example: PAGE #3H ; Move 3H to page buffer JP AN ; Jump to label AN located at page 3 if SF is one; otherwise, it is skipped CPNE @HL,A Binary Code: 0 0 0 0 0 0 0 0 Description: The contents of accumulator are compared to the contents of indirect data memory; an appropriate flag is set if their values are not equal. The contents of both operands are unaffected by the comparison. Operation: M [(H,L)] ≠ (A) Flags: SF : Set if not equal, cleared otherwise SL : Unaffected Example: CLR A ADDS A,#3H MOV H,#0H MOV L,#6H CPNE @HL,A ; Acc value 3H is compared to contents of RAM address 06H JP OA ; Jump to OA if values of RAM address 06H are not 3h JP OB ; Jump to OB if values of RAM address 06H are 3H

CPNZ @HL Binary Code: 0 0 1 1 1 1 1 1 Description: This instruction compares the magnitude of indirect data memory with zero, and the appropriate flag is set if their values are not equal, i.e., if the contents of indirect data memory are not zero. The contents of operand are unaffected by the comparison. Operation: M [(H,L)] ≠ 0 Flags: SF : Set if not zero, cleared otherwise SL : Unaffected Example: Assume the contents of RAM address are 4H CPNZ @HL ; Compare 4H with zero JP EQ ; Jump to EQ because the result is not equal JP WAIT CPNE L,A Binary Code: 0 0 0 0 0 0 1 0 Description: The contents of the accumulator are compared to the contents of register L; the appropriate flags are set if their values are not equal. The contents of both operands are unaffected by the comparison. Operation: (L) ≠ (A) Flags: SF : Set if not equal, cleared otherwise SL : Set if not equal, cleared otherwise Example: Assume REG L contains 5H, A contains 4H CPNE L,A ; Compare A to REG L values JP K1 ; Jump to K1 because the result is not equal JP K2

CPNE L,#n Binary Code: 0 1 0 1 d d d d Description: This instruction compare the immediate 4 bit data n with the contents of register L, and sets an appropriate flag if their values are not equal. The contents of both operands are unaffected by the comparison. Operation: (L) ≠ #n Flags: SF : Set if not equal, cleared otherwise SL : Unaffected Example: CLR A ADDS A,#4H MOV L,A CPNE L,#5H ; Compare immediate data 5H to REG L values JP K3 ; Jump to K3 because the result is not equal CPNE A,@HL Binary Code: 0 0 0 0 0 0 0 1 Description: The contents of indirect data memory are compared to the contents of the accumulator. Appropriate flags are set if the contents of the accumulator are less than or equal to the contents of indirect data memory. The contents of both operands are unaffected by the comparison. Operation: (A) ≤ M [(H,L)] Flags: SF : Set if less than or equal to, cleared otherwise SL : Unaffected Example: Assume RAM address holds 8H CPLE A,@HL ; Compare 8H to A values JP MAR ; Jump to MAR if 0H ≤ A ≤ 8H JP BPR ; Jump to BPR if 9H ≤ A ≤ 0FH

Binary Code: 0 0 0 0 1 1 1 0 Description: The instruction compares the contents of Port 0 with zero. Appropriate flags are set if their values are not equal, i.e., if the contents of Port 0 are not zero. The contents of the operand are unaffected by the comparison. Operation: (P0) ≠ 0 Flags: SF : Set if not zero, cleared otherwise SL : Unaffected Example: MOV L,#0DH CLRB P2.(L) ; Clear P2.13, i.e., select P0 input CPNZ P0 ; Compare P0 to zero JP KEYIN ; Jump to KEYIN if P0 ≠ 0 JP NOKEY ; Jump to NOKEY if P0 = 0 CPBT @ HL,b Binary Code: 0 0 1 1 1 0 d d Description: CPBT tests indirect data memory bit and sets appropriate flags if the bit value is one. The contents of operand are unaffected by the test. Operation: M [(H,L)] = 1 Flags: SF : Set if one, cleared otherwise SL : Unaffected Example: MOV H,#0H MOV L,#0BH CPBT @HL,3 ; Test RAM address 0BH bit 3 JP Q1 ; Jump to Q1 if RAM address bit 3 is 1 JP Q2 ; Jump to Q2 if RAM address bit 3 is 0

Binary Code: 1 0 d d d d d d Description: The JP transfers program control to the destination address if the SF is one. The conditional jump replaces the contents of the program counter with the address indicated and transfers control to that location. Had the SF flag not been set, control would have proceeded with the next instruction. Operation: If SF = 1 ; PC ← (W), PA ← PB Flags: SF : Set to one SL : Unaffected Example: JP SUTIN1 ; This instruction will cause program execution to branch to the instruction at label SUTIN; SUTIN1 must be within the current page CALL dst Binary Code: 1 1 d d d d d d Description: If the SF flag is set to 1, this instruction calls a subroutine located at the indicated address, and then pushes the current contents of the program counter to the top of the stack. The program counter value used is the address of the first instruction following the CALL ins. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure, the return (RET) instruction can be used to return to the original program flow. Operation: If SF = 1 ; SRi ← PC + 1, PSRi ← PA PC ← I (W), PA ← PB Flags: SF : Set to one SL : Unaffected Example: CALL ACD1 ; CALL subroutine located at the label ACD1 where ACD1 must be within the current page RET Binary Code: 0 0 0 0 1 1 1 1 Description: This instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement executed is that addressed by the new contents of the program counter. Operation: PC ← Sri, PB ← PSRi PA ← PB Flags: SF : Set to one SL : Unaffected Example: RET ; Return from subroutine

SETB P2.(L) Binary Code: 0 0 0 0 1 1 0 1 Description: This instruction sets the Port 2 bit addressed by register L without affecting any other bits in the destination. Operation: P2.(L) ← 1 Flags: SF : Set to one SL : Unaffected Example: MOV L,#0H SETB P2.(L) ; Set P2.0 to 1 CLRB P2.(L) Binary Code: 0 0 0 0 1 1 0 0 Description: This instruction clears the Port 2 bit addressed by register L without affecting any other bits in the destination. Operation: P2.(L) ← 0 Flags: SF : Set to one SL : Unaffected Example: MOV L,#0H CLRB P2.(L) ; Clear P2.0 to 0 IN A,P0 Binary Code: 0 0 0 0 1 0 0 0 Description: Data present on Port n is transferred (read) to the accumulator. Operation: (A) ← ( Pn) (n = 0,1) Flags: SF : Set to one SL : Unaffected Example: IN A,P0 ; Input port 0 data to Acc MOV L,A CPNE L,#3H JP OX ; Jump to OX if port 0 data ≠ 3H JP QP ; Jump to QP if port 0 data = 3H

OUT P3,@SL+A Binary Code: 0 0 0 0 1 0 1 0 Description: The contents of the accumulator and SL are transferred to the P3 Output register. Operation: (P3 Output register) ← (A) + (SL) Flags: SF : Set to one SL : Unaffected Example: CLR A OUT P3,@SL+A ; Zero output on port 3 NOTI A Binary Code: 0 0 1 1 1 1 0 1 Description: The contents of the accumulator are complemented; all 1 bits are changed to 0, and vice- versa, and then incremented by one. Operation: (A) ← (A), (A) ← (A) +1 Flags: SF : Set if the result is zero, cleared otherwise SL : Unaffected Example: CLR A ADDS A,#7H NOTI A ; Complement 7H (0111B) and increment the result by one; the instruction NOTI A then leaves 9H (1001B) in A

Binary Code: 0 0 0 0 1 0 0 1 Description: The MSB of register H is complemented, Operation: (H) ← (H) Flags: SF : Set to one SL : Unaffected Example: MOV H,#4H NOT H ; Complement 4H (100B), then it leaves 00H (000B) in REG H CLR A Binary Code: 0 1 1 1 1 1 1 1 Description: The contents of the accumulator are cleared to zero (all bits set on zero). Operation: (A) ← 0 Flags: SF : Set to one SL : Unaffected Example: CLR A ; A value are cleared to zero ADDS A,@HL Binary Code: 0 0 0 0 0 1 1 0 Description: ADDS adds the contents of indirect data memory to accumulator, leaving the result in the accumulator. The contents of the source operand are unaffected. Operation: (A) ← M [(H,L)] + (A) Flags: SF : Set if a carry occurred, cleared otherwise SL : Unaffected Example: Assume RAM address holds 5H CLR A ; Clear A to zero ADDS A,@HL ; This instruction will leaves 5H in A

ADDS A,#n Binary Code: 0 1 1 1 d d d d Description: The specified 4-bit data n is added to the accumulator and the sum is stored in the accumulator. Operation: (A) ← (A) + #n Flags: SF : Set if a carry occurred, cleared otherwise SL : Unaffected Example: CLR A ; Clear A to zero ADDS A,#4H ; Add 4H to A, it leaves 4H in A SUBS A,@HL Binary Code: 0 0 1 1 1 1 0 0 Description: SUBS subtracts the contents of accumulator from the contents of indirect data memory, leaving the result in the accumulator. The contents of source operand are unaffected. Operation: (A) ← M [(H,L)] - (A) Flags: SF : Set if no borrow occurred, cleared otherwise SL : Unaffected Example: Assume RAM address holds 0CH MOV L,#8H MOV A,L SUBS A,@HL ; Subtract A from 0CH; it will leave 4H in A INCS A,@HL Binary Code: 0 0 1 1 1 1 1 0 Description: The contents of indirect data memory are incremented by one and the result is loaded into the accumulator. The contents of indirect data memory are unaffected. Operation: (A) ← M [(H,L)] + 1 Flags: SF : Set if a carry occurred, cleared otherwise SL : Unaffected Example: Assume RAM address holds 6H CLR A ; Clear A to zero INCS A,@HL ; Increment 6H by one and leave 7H in A

Binary Code: 0 0 0 0 0 1 0 1 Description: The contents of the L register are incremented by one. Operation: (L) ← (L) + 1 Flags: SF : Set if a carry occurred, cleared otherwise SL : Unaffected Example: MOV L,#5H INCS L ; Increment REG L value 5H by one INCS A Binary Code: 0 1 1 1 0 0 0 0 Description: The contents of the accumulator are incremented by one. Operation: (A) ← (A) + 1 Flags: SF : Set if no borrow occurred, cleared otherwise SL : Unaffected Example: MOV L,#5H MOV A,L INCS A ; Increment 5H by one DECS A Binary Code: 0 1 1 1 0 1 1 1 Description: The contents of the accumulator are decremented by one. Operation: (A) ← (A) - 1 Flags: SF : Set if a carry occurred, cleared otherwise SL : Unaffected Example: MOV L,#0BH MOV A,L DECS A ; The instruction leaves the value 0AH in A

DECS A,@HL Binary Code: 0 0 0 0 0 1 1 1 Description: The contents of the data memory addressed by the H and L registers are decremented by one and the result is loaded in the accumulator. But the contents of data memory are not affected. Operation: (A) ← M [(H,L)] - 1 Flags: SF : Set if a carry occurred, cleared otherwise SL : Unaffected Example: Assume RAM address holds 5h MOV L,#0AH MOV A,L DECS A,@HL ; Decrement the value 5H by one, and the result value 4H is loaded in A DECS L Binary Code: 0 0 0 0 0 1 0 0 Description: The contents of the L register are decremented by one. Operation: (L) ← (L) - 1 Flags: SF : Set if no borrow occurred, cleared otherwise SL : Unaffected Example: MOV L,#3H DECS L ; This instruction leaves the value 2H in REG L SETB @ HL,b Binary Code: 0 0 1 1 0 0 d d Description: This instruction sets indirect data memory bit addressed by registers H and L without affecting any other bits in the destination. Operation: b ← 1 (b = 0,1,2,3) Flags: SF : Set to one SL : Unaffected Example: MOV H,#0H MOV L,#5H SETB @HL.2 ; Set RAM address 05H bit 2 to 1

DECS A,@HL Binary Code: 0 0 1 1 0 1 d d Description: This instruction clears the indirect data memory bit addressed by registers H and L without affecting any other bits in the destination. Operation: b ← 1 (b = 0,1,2,3) Flags: SF : Set to one SL : Unaffected Example: MOV H,#0H MOV L,#5H CLRB @HL.3 ; Clear RAM address 05H bit 3 to zero

KS51840/51850 MICROCONTROLLER DEVELOPME NT TOOLS 4- 1

4 DEVELOPMENT TOOLS

The Samsung Microcontroller Development System, SMDS ,is a complete PC-based development environment for KS51840 microcontroller. The SMDS is powerful, reliable, and portable. The SMDS tool set includes a versatile debugging utility, trace with built-in logic analyzer, and performance measurement applications. Its window-oriented program development structure makes SMDS easy to use. SMDS has three components: — IBM PC- compatible SMDS software, all device-specific development files, and the SAMA assembler. — Development system kit including main board, personality board, SMDS manual, and target board adapter, if required. — Device-specific target board. SMDS PRODUCT VERSIONS As of the date of this publication, two versions of the SMDS are being supported: — SMDS Version 4.8 (S/W) and SMDS Version 3.6 (H/W); last release: January, 1994. — SMDS2 Version 5.3 (S/W) and SMDS2 Version 1.3 (H/W); last release: November, 1995. The new SMDS2 Version 1.3 is intended to replace the older Version 3.6 SMDS. The SMDS2 contains many enhancements to both hardware and software. These development systems are also supported by the personality boards of Samsung’s microcontroller series: KS56, KS57, and KS88. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Compiled program code includes the object code that is used for ROM data and required SMDS program control data. To compile programs, SAMA requires a source file and an auxiliary definition (DEF) file with device-specific information. TARGET BOARDS AND PIGGYBACKS Target boards are available for KS51840/51850 microcontroller. All required target system cables and adapters are included with the device-specific target board. Piggyback chips are provided to customers in limited quantities for KS51840/51850 microcontroller. The KS51840/51850 piggyback chips, PB51840/51850-20 and PB51850-24 are now available.

DEVELOPMENT TOOLS K S51840/51850 MICROCONTROLLER 4- 2 PB51840/51850-20 is 20 DIP piggyback chip for 20 DIP, 20 SOP package device of KS51840/51850 microcontroller. PB51840/51850-24 is 24DIP piggyback chip for 24 SOP package device of KS51850 microcontroller. IBM-PC or Compatiable Internal Bus 5-Volt Power Supply Main Board Personality Board Front Panel Board RS-232C SMDS2 POD Target Board Target Application System Target Cable Figure 4-1. SMDS Product Configuration (SMDS2)

KS51840/51850 MICROCONTROLLER DEVELOPME NT TOOLS 4- 3 TB51840/51850A TARGET BOARD The TB51840/51850A target board is used for the KS51840/51850 microcontroller. It is supported by the SMDS2 development system only. TB51840/51850A SM1243A CN1 To User_Vcc Off On Reset 1 U5 U4 GND V CC 1 64

64 SDIP

+ + + P2.6 P2.5 P2.4 + + ++ P2.3 P2.2 P2.1 P2.0 Figure 4-2. TB51840/51850A Target Board Configuration

DEVELOPMENT TOOLS K S51840/51850 MICROCONTROLLER 4- 4 Table 4-1. Power Selection Settings for TB51840/51950A 'To User_Vcc' Settings Operating Mode Comments To User_Vcc ONOFF Target System SMDS2 TB51840/ 51850A V CC V SS V CC The SMDS2 supplies V CC to the target board (evaluation chip) and the target system. To User_Vcc ONOFF Target System SMDS2 TB51840/ 51850A V CC V SS V CC External The SMDS2 supplies V CC only to the target board (evaluation chip). The target system must have its own power supply. LED 2.0-LED 2.6: These LEDs are used to display value of the P2.0-P2.6. It will be turn on, if the value is Low. P2 OPTION SWITCH: Switch ON: You can see the port value using the LED display. Switch OFF: You can’t see the port value. That is, the LED won’t be turn ON by the port value.

KS51840/51850 MICROCONTROLLER DEVELOPME NT TOOLS 4- 5 J101 24-DIP SOCKET V SS X IN X OUT P2.6 P0.0 P0.1 P0.2 P0.3 P1.0 P1.2 P1.3 P1.1 V SS X IN X OUT P0.0 P0.1 P0.2 P0.3 P1.0 P1.2 P1.3 P1.1 P2.6 Figue 4-3. 24 DIP Socket for TB51840 (KS51840, 24 SOP) Target Board24-DIP SOCKET Target System J101 Target Cable for 24 DIP Package Part Name: AS24D Order Code: SM6303 1 24 12 13 1 24 12 13 Figure 4-4. TB51840/51850A Cable for 24 DIP Package

REMOTE CONTROL TX. 5- 1 5 REMOTE CONTROL TX. OVERVIEW The KS51840/51850 4-bit single-chip CMOS microcontroller is designed using the reliable SMCS-51 CPU core with on-chip ROM and RAM. An auto-reset circuit generates a RESET pulse in regular intervals, and can be used to initiate a Halt mode release. The KS51840/51850 microcontroller is intended for use in small system control applications that require a low-power and cost-sensitive design solution. In addition, the KS51840/51850 has been optimized for remote control transmitters. A difference between the KS51840 and KS51850 is that KS51850 has N-channel transistor for I.R.LED drive. Table 5-1. KS51840/51850 Features Feature KS51840 KS51850 ROM 1024 bytes 1024 bytes RAM 32 x 4 bits 32 x 4 bits Carrier frequency fxx /12, fxx /8, no carrier fxx /12, fxx /8, no carrier Operating voltage 250 kHz ≤ f OSC ≤ 3.9 MHz 1.8 V to 3.6 V,

3.9 MHz < f OSC < 6 MHz

2.2 V to 3.6 V 250 kHz ≤ f OSC ≤ 3.9 MHz 1.8 V to 3.6 V, 2.2 V to 3.6 V Package 24 SOP, 20 SOP/DIP 24 SOP, 20 SOP/DIP Tr. for I.R.LED drive x Built-in Table 5-2. KS51840/51850 Package Types Item 24 pins 20 pins Package 24 SOP-375 20 DIP-300A

20 SOP-300

20 SOP-375

REMOTE CONTROL TX. 5- 2 Table 5-3. KS51840/51850 Functions

Description

Automatic reset by Halt mode release When Halt mode is released, the chip is reset after an oscillator stabilization interval of 9 ms. (fxx = 455 kHz) Output pin state retention function When the system enters Halt Mode, state in KS51850. Auto-reset With oscillation on and with no change to the IP2.0 output pin, a reset is activated every 288 ms at fxx = 455 kHz. Osc. Stabilization time CPU instructions are executed after oscillation stabilization time has elapsed. Power-on reset circuit resister: 1 M Ω , capacitor value: 7 pF. Other functions Carrier frequency generator. Halt wake-up function. RESET The KS51840/51850 has three kinds of reset operations: — POR (Power-On Reset) — Auto-reset — Automatic reset by Halt release Power-On Reset Circuits 7 pF

0.3 V DD

2.2 V V DD RESET Reset Time Figure 5-1. Power-On Reset Circuits

REMOTE CONTROL TX. 5- 3 Auto-Reset The auto-reset function resets the CPV every 131,072 oscillator cycles (288 ms at fxx = 455 kHz). The auto-reset counter is cleared when a rising edge is detected at IP2.0, or by a HALT or RESET pulse. Normal Mode Halt Halt Release Signal IP2.12 = 1, Non-Active Input Pin Normal Mode: After a reset, the program restarts from 0F00H after one instruction in 0FxxH is executed.('F' is page number and 'xx' is the next instruction of HALT instruction.) fXX = 455 kHz Osc. Stabilization Time (9 ms) Osc. Circuit Wait Time (3-4 ms) X O Osc. Stabilization counter starts Auto-reset counter Chip restarts and auto-reset counter is incremented. Chip holds it's internal status. Upon entering Halt mode, the auto-reset counter is cleared to zero. Systerm reset occurs when the auto-reset counter overflows. The program restarts from 0F00hH Overflow IP2.0 IP2.0 Figure 5-2. Auto-Reset Counter Function

REMOTE CONTROL TX. 5- 4 Automatic Reset by Halt Mode Release This function resets the CPV by releasing Halt mode. The CPV is reset to its initial operating status and program execution starts from the reset address. Halt Mode and Automatic Reset by Halt Release Halt mode is used to reduce power consumption by stopping the oscillation and holding the internal state. Halt mode can be entered by forcing IP2.12 to high level (remaining input pins are non-active). Before entering Halt mode, programmer should pre-set all key strobe output pins to active state even though Halt mode causes some pins to remain active. are sent low. Forcing any key input port to active state causes the clock oscillation logic to start system initialization. At this time, the system is reset after the oscillation stabilization time elapses. A system reset causes program execution to start from address 0F00H. Normal Mode: After a reset, the program restarts from 0F00H after one instruction in 0FxxH is executed.('F' is page number and 'xx' is the instruction immediately following the HALT instruction.) Osc. Stabilization Timer Start IP2.12 = 1, Non-Active Input Pin fXX = 455 kHzOsc. Stabilization Timer (9 ms) Osc. Circuit Wait Time (3-4 ms) Halt Release Signal Halt Normal Mode X O Figure 5-3. Reset Timing Diagram

REMOTE CONTROL TX. 5- 5 HALT mode programming The KS51840/51850 can enter Halt mode by setting the IP2.12 pin to high level and forcing P0 and P1 input to a normal state. If IP 2.12 is high and any input is active, the chip cannot enter Halt mode. Therefore, the next instruction is executed, which must be a clear command for IP2.12. MOV L, #5 KEYOLO CLRB P2.(L) ; P2.5,4,3,2, ← Low DECS L CPNE L,#1 JP KEYOLO CLR A ; A CC . ← #0h OUT P3,@SL+A ; P3.0,1,2,3, ← Low MOV L,#0DH CLRB P2.(L) ; Select the P0 input IN A,P0 INCS A ; P0 input check JP .+2 JP KEYCHK ; If any key pressed in P0, jump to KEYCHK routine SETB P2.(L) ; Select the P1 input IN A,P0 INCS A ; P1 input check JP + 2 JP KEYCHK ; If any key pressed in P1, jump to KEYCHK routine MOV L,#0CH ; No key pressed SETB P2.(L) ; Halt mode ; When no key is pressed, the chip enters Halt mode. Pressing any key while in Halt mode causes the chip to be initialized and restarted from the reset address. ; If any key is pressed between timea and timeb, the following instruction is executed. MOV L,#0CH ; These two instructions remove the condition of re-entering CLRB P2,(L) ; Halt mode.

REMOTE CONTROL TX. 5- 7 Table 5-4. Strobe Output Option Pin usage Key Output LED Drive Option Selection P3.0-P3.3 P2.2-P2.5

00 X X

P2.1 0 00 0 P2.6 0 0 00 NOTE: X = not allowed 0 = good 00 = better Output Pin Circuit Type P2.1, P2.6 P2.6: For option pin or key-out P2.1: For LED drive pin or key-out DATA X 0 0 X 1 H-Z Halt Data Port DATA HALT P3.0-P3.3, P2.2-P2.5 Low output retention function in Halt mode is used for key strobe output only 0 0 0 0 1 H-Z

0 X 0

Figure 5-6. Output Pin Circuits

REMOTE CONTROL TX. 5- 8 Soft Ware Delay Routine To obtain a constant time value, the KS51840/51850 use a software delay routine (there is not an internal timer interrupt). One instruction cycle is six oscillator clocks. Using a ceramic resonator with a constant frequency, you can calculate the time delay as follows: t = 6/fxx Number of Instructions Where t: Elapsed time and fxx: System clock. Programming Tip To program a 1-ms delay: 1 ms = 6/455 kHz x n, where fxx = 455 kHz Therefore, n = 75.8 = 76 instructions DLY1MS CLR A ADDS A,#0BH ; Two instructions DLY MOV H,#0 ; Dummy instruction MOV H,#0 ; Dummy instruction MOV H,#0 ; Dummy instruction MOV H,#0 ; Dummy instruction DECS A JP DLY ; DLY loop: 6 instructions ;2 + (ACC + 1) x instructions in loop = 2 + (11 + 1) x 6 = 74 CLR A CLR A ; Two instructions. ; Total number of instructions for DLY1MS is 76. NOTE In order to lengthen the delay time, you can use an arithmetic instruction combination of L register and Accumulator. The L register causes the address lower pointer to access RAM spce and the output port pointer to control the P2 (individual/serial output) port status. — RAM manipulation instruction: RAM address pointer. MOV A,@HL CPNE @HL,A ADDS A,@HL SETB @ HL.b — P2 output control instruction: P2 pointer. SETB P2.(L) CLRB P2.(L)

REMOTE CONTROL TX. 5- 9 PROGRAMMING GUIDELINES When programming KS51840/51850 microcontroller, please follow the guidelines presented in this subsection. PCB Artwork For remote control applications, turning the I.R.LED on and off may cause variations in transmission current ranging from a few hundred µA to a few hundred mA. This current variation generates overshoot and undershoot noise on the power line, causing a system malfunction. Remocon Signal V DD To reduce noise and to stabilize the chip’s operation, we recommend that the application designer reduce overshooting of the I.R.LED drive current and design PCB for the remote controller as follows: (The noise level should be limited to around 0.5 Vp-p, where Vp-p is the peak-to-peak voltage) — Oscillation circuit should be located as near as possible to the chip. — PCB pattern for V DD /V SS should be as wide and short as possible. — Power supply battery and power capacitor should be located as near as possible to the chip. — The ground pattern of the TEST pin (TEST pin I.R.LED drive TR) and V SS pin should be separated and connected directly with the battery terminal. — The ceramic capacitor (0.1 uFor 0.01uF) is recommended to use noise filter.

REMOTE CONTROL TX. 5- 10 SMDS When a breakpoint or single-step instruction is executed in area of PAGE and JP or CALL instruction, the JP or CALL may jump to the wrong address, We therefore recommend using a JPL or CALL instruction (instead or PAGE and JP or PAGE and CALL) to avoid this problems. Note that JP and CALL are 2-byte instructions. Programming Guidelines for Reset Subroutine 1. We recommend that you initialize a H register to either “0” or “4” 2. Do not write the instructions CALLL (PAGE + CALL) or JPL (PAGE + JP) to the reset address 0F00H. In other words, do not use a PAGE instruction at 0F00H. 3. Turn off the LED output pin. 4. To reduce current consumption, do not set the option output pin to active state. 5. Pre-set the remocon carrier frequency (to fxx/12, fxx /8, and so on) before remocon signal transmission. 6. Because the program is initialized by an auto-reset or Halt mode release, even in normal operating state, do not pre-set all RAM data. If necessary, pre-set only the RAM area you need. 7. Be careful to control output pin status because some pins are automatically changed to active state. 8. To enter Halt mode, the internal port, IP2.12, should be set to high level and all of the input pins should be set to normal state. 9. To release Halt mode, an active level signal is supplied to input pins. If pulse width is less than 9 ms at fxx = 455 kHz, nothing happens and program re-enters Halt mode. That is, the external circuit should maintain the input pulse over a 9-ms interval in order to release Halt mode. After Halt mode is released, the hardware is reset. The hardware reset sends all internal and external output pins low (except P2.0 in KS51850) and clears the stack to zero. However, H,L and A registers retain their previous status. 10. If a rising edge is not generated at IP2.0, reset signal occurs every 288 ms at fxx = 455 kHz. To prevent an auto-reset, IP2.0 should be forced low and then high at regular intervals (within 288 ms at fxx = 455 kHz).

REMOTE CONTROL TX. 5- 11 V DD P2.0/ REM SAMSUNG KS51840-xx C2C1 C4C3 C6C5 C8C7 C2 C3 K8 K24K16 K40K32 K56K48 K9K1 K25K17 K41K33 K57K49 K10K2 K26K18 K42K34 K58K50 K11K3 K27K19 K43K35 K59K51 K12K4 K28K20 K44K36 K60K52 K13K5 K29K21 K45K37 K61K53 K14K6 K30K22 K46K38 K62K54 K15K7 K31K23 K47K39 K63K55 C4 C1 +3 V V DD R1: 1-0.45 Ω R2: 100 Ω C1: 4.7 µF/6.3 V C2, C3: 100 pF C4: 0.1 µF D1: I.R.LED D2: INDICATOR LED Resonator: 455 kHz K C OR Figure 5-7. KS51840 Applicatrion Circuit Example

REMOTE CONTROL TX. 5- 12 V DD P2.0/ REM SAMSUNG KS51850-xx C2C1 C4C3 C6C5 C8C7 C2 C3 K8 K24K16 K40K32 K56K48 K9K1 K25K17 K41K33 K57K49 K10K2 K26K18 K42K34 K58K50 K11K3 K27K19 K43K35 K59K51 K12K4 K28K20 K44K36 K60K52 K13K5 K29K21 K45K37 K61K53 K14K6 K30K22 K46K38 K62K54 K15K7 K31K23 K47K39 K63K55 R C4 C1 +3 V V DD R: 100 Ω C1: 4.7 µF/6.3 V C2,C3: 100 pF C4: 0.1 µF D1: I.R.LED D2: INDICATOR LED Resonator: 455 kHz K C OR Figure 5-8. KS51850 Application Circuit Example

REMOTE CONTROL TX. 5- 13 Program Flowchart One key input? RESET DEBOUNCE TIME All key strobe output pins are active TRANSMIT TWO WAVEFORMS TRANSMIT TWO WAVEFORMS Only one key strobe pin is active Debounce Time = 0? DATA & CUSTOM CODE GENERATION Continous key? MAIN Yes No Yes No No Yes DOUBLE KEY & NO KEY RESET MAIN KEYSCAN DATCUS SIGNAL Tx. No Yes Any key input? All key strobe output pins are active HALT START Figure 5-9. Program Flowchart 1

REMOTE CONTROL TX. 5- 14 KS51840/51850 KEYSCAN FUNCTION This program has an 8 x 9 key matrix, which consists of input P0 and P1 and output P2 and P3. Because pull-up resistors are connected, the normal state for all input pins is high level. The operating method for the keyscan function is as follows: — All output pins remain active state ( = low). — If key is pressed, set all output pins to non-active state and rotate the pins to set only a pin to active state during debounce time. — If key is pressed more than one or if no key is pressed, go to reset label. — IF a new key is pressed, reset debounce time, continous fl ag, and key-in flag. RAM Assignment O_INP0 N_INP0 O_INP1 N_INP1 O_OUTP I_TWICEN_OUTP DEBOCNT CONKEY KFLG 05H 09H H register selects #0 01HHL 00H O_INP0: he old value of P0 N_INP0: The new value of P0 O_INP1: The old value of P1 N_INP1: The new value of P1 O_OUTP: The old value of output port N_OUTP: The new value of output port I_TWICE: Double number increment DEBOCNT: Debounce time CONKEY: Continous key flag KFLG: key input flag

REMOTE CONTROL TX. 5- 15 Program Flowchart 518KSCAN O_INP0, O_INP1, O_OUTP #0FH DEBOCNT, CONKEY #0 H #0 RESET MAIN STROBE P2.1 & 2.6 HIGH PORT3, P2.2-P2.5 LOW PORT0 = #0FH PORT1 = #0FH PORT3, P2.2-P2.5 HIGH P2.2-P2.5 LOW P2.5 HIGH PORT3 LOW N_OUTP.2 = #1 Yes N_OUTP, KFLG #0, I_TWICE #1 A No No No ; Close indicator LED & option pin ; Active strobe output pins ; Initial variable ; Check port0 input ; Check port1 input ; Halt mode & Halt mode release ; H register selects #0 ; Non-active strobe output pins ; Only one output pin is low level ; PARALLSTROBE Figure 5-10. Program Flowchart 2

REMOTE CONTROL TX. 5- 16 A RESET PORT0 = #0FH N_INP0 PORT0 N_INP1 #0FH L N_INP0 PORT1 = #0FH A A + #1 OVERFLOW? A A - #1 N_INP0 A N_OUTP O_OUTP N_OUTP = O_INP0 N_INP0 O_INP0 N_INP0 = O_INP0 N_INP1 O_INP1 N_INP1 = O_INP1 DEBOCNT #2 CONKEY #0 KFLG #1 PORT1= #0FH N_INP0 #0FH N_INP1 PORT1 L N_INP1 A A + #1 OVERFLOW? A A - #1 N_INP1 A a NORMAL RESET KEYIN: PORT0: ; DOUBLE KEY DBCOMP: ;Key input setting SETKEY: ;New key & debounce time setting ;Compare old data to new data ; DOUBLE KEY ; NO KEY PORT 1: ; Check the end of debounce time INCS N_OUTP a N_OUTP = #8 KFLG = #1 P3.3 HIGH DECS DEBOCNT DEBOCNT = #0 RET RESET MAIN STROBENORMAL: NO KEY Yes YesNo Yes No Yes No No No Yes No Yes No No Yes No Yes No No Yes KEYCHEK KEYCHEK Figure 5-11. Program Flowchart 3

REMOTE CONTROL TX. 5- 17 KS51840/51850 Keycheck Subroutine L= #07H No No No L = #0DH KEYCHEK A #0EH L = #0FH A A + #1 L = #0BH A A + #2 A A + #3 A A + #4 RET No Figure 5-12. Ks51840/51850 Keycheck Subroutine

REMOTE CONTROL TX. 5- 18 ORG 0F00H ; If reset occurs, PA register is immediately initialized to #0FH RESET MOV L,#1 ; close indicator LED SETB P2.(L) ; MOV L,#6 ; non-select P2.6 SETB P2.(L) ; PRTCLR CLR A : OUT P3,@SL + A ; low all the output ports MOV L,#5 ; (except P2.0, P2.1, P2.6) CLRB P2.(L) ; DECS L ; CPNE L,#1 ; JP .-3 ; ;;; → input ports are connected with pull-up resistor ;;; → Therefore, normal state → high MOV H,#0 ; H register selects file #0 MOV L,#O_INP0 ; port0 is #0fh MOV @HL+,#0FH MOV L, #O_INP1 ; port1 is #0fh MOV @HL +,#0FH MOV L, #O_OUTP ; the strobe out is #0fh MOV @HL+,#0FH MOV L,#DEBOCNT ; debounce count is #0 MOV @HL+,#0 MOV L,#CONKEY ; continuous key is #0 MOV @HL+,#0 MOV L,#0DH ; check port0 CLRB P2.(L) ; IN A,P0 ; MOV L,A ; CPNE L,#0FH ; JP DELAYP0 ; MOV L,#0DH ; check port1 SETB P2.(L) ; IN A,P0 ; MOV L,A ; CPNE L,#0FH ; JP J_MAIN ;

REMOTE CONTROL TX. 5- 19 MOV L,#0CH SETB P2.(L) ; halt mode CLRB P2.(L) ; halt mode release JP RESET PRTSET CLR A ; ADDS A,#0FH ; OUT P3,@SL+A ; MOV L,#5 ; SETB P2.(L) ; DECS L ; CPNE L,#1 ; If P2.0 is high, data Tx. JP .- 3 ; and auto reset counter clear RET DELAYP0 MOV H #0 ; for the match of delay time MOV H #0 ; MOV H #0 ; M OV H #0 ; MOV H #0 ; MOV H #0 ; J_MAIN JPL MAIN ORG 0000H JPL RESET MAIN MOV H,#0 ; H regisster selects file #0 ; useful when continous pulse Tx. CALLL PRTSET ; high all the output ports MOV L,#N_OUTP ; N_OUTP ← #0 MOV @HL+,#0 ; MOV L,#1_TWICE ; I_TWICE (double increment) ← #1 MOV @HL+,#1 ; MOV L,#KFLG ; KF LG ← #0 (input key flag) MOV @HL+,#0 ;

REMOTE CONTROL TX. 5- 20 STROBE MOV L,#N_OUTP CPBT @HL.2 ; If N_OUTP.2 is set, go to parall (parallel port) JP PARALL ; otherwise, go to serial (serial port) SERIAL MOV L,@HL ; INCS L ; SETB P2.(L) ; INCS L ; CLRB P2.(L) ; JPL KEYIN PARALL MOV L,#5 ; high P2.5 SETB P2.(L) ; ;;; A ← #0h ;;; A ← A-1_TWICE ;;; output P3 ;;; I_TWICE ← I_TWICE + I_TWICE CLR A ; A ← #0FH ADDS A, #0FH ; MOV L, #1_TWICE ; XCH @HL,A ; A ← A-I_TWICE SUBS A,@HL ; OUT P3,@SL+A ; low port3 SUBS A,@HL ; MOV @HL,A ; recover I_TWICE ADDS A,@HL ; MOVZ @HL,A ; I_TWICE ← I_TWICE + I_TWICE JPL KEYIN ;; check double key at each port ;; if a key pressed, do adds instruction ;; otherwise, induce overflow occurrence KEYCHEK CLR A ADDS A,#0FH ; A ← #0fh CPNE L,#0EH JP .+2 ADDS A,#1 ; A ← #0 CPNE L,#0DH JP .+2 ADDS A,#2 ; A ← #1

REMOTE CONTROL TX. 5- 21 CPNE L,#0BH JP .+2 ADDS A,#3 ; A ← #2 CPNE L,#7 JP .+2 ADDS A,#4 ; A ← #3 RET ORG 0100H JPL RESET KEYIN MOV L,#0DH CLRB P2.(L) IN A, P0 MOV L,A CPNE L,#0FH ; is key pressed in port0 ? JP PORT0 JP PORT1 PORT0 MOV L,#N_INP0 ; setting at N_INP0 MOV @HL,A ; MOV L,#ODH ; SETB P2.(L) ; IN A,P0 ; MOV L,A ; CPNE L,#0FH ; JP DBKEY ; If also port1 input a key, ; it is double key MOV L,#N_INP1 ; Only N_INP0 input MOV @HL+,#0FH ; MOV L,#N_INP0 ; MOV L,@HL ; CALLL KEYCHEK ; ADDS A,#1 ; JP DBKEY ; if overflow occurs, it is double key DECS A ; because input value ranges MOV L,#N_INP0 ; from #0 to #3 MOVZ @HL,A ; N_INP0 ← A JPL DBCOMP

REMOTE CONTROL TX. 5- 22 PORT1 MOV L,#0DH SETB P2.(L) IN A,P0 MOV L,A CPNE L,#0FH ; is key pressed in port 1? JP .+3 JPL NORMAL ; no key, go to NORMAL MOV L,#N_INP0 ; setting N_INP0 to #0fh MOV @HL+,#0FH ; Only N_INP1 input MOV L,#N_INP1 ; MOV @HL,A ; MOV L,A ; L ← N_INP1 CALLL KEYCHEK ADDS A,#1 ; if overflow occurs, go to double key JP DBKEY ; DECS A ; because input value ranges from #0 to #3 MOV L,#N_INP1 ; N_INP1 ← A MOVZ @HL,A JPL DBCOMP DBKEY JPL RESET ORG 0200H JPL RESET DBCOMP MOV H,#N_OUTP ; compare N_OUTP to O_OUTP MOV A,@HL MOV L,#O_OUTP XCH @HL,A JP FSTKEY MOV L,#N_INP0 ; compare N_INP0 to O_INP0 MOV A,@HL MOV L,#O_INP0 XCH @HL,A CPNE @HL,A JP FSTDLY MOV L,#N_INP1 ; compare N_INP1 to O_INP1 MOV A,@HL MOV L,#O_INP1

REMOTE CONTROL TX. 5- 23 XCH @HL,A CPNE @HL,A JP FSTKEY JP SETKEY FSTDLY MOV H,#0 ; for match of delay time MOV H,#0 MOV H,#0 MOV H,#0 MOV H,#0 FSTKEY MOV L,#DEBOCNT ; DEBOCNT ← #2 MOV @HL+,#2 MOV L,#CONKEY ; CONKEY ← #0 MOV @HL+,#0 SETKEY MOV L,#KFLG ; KFLG ← #1 MOV @HL+,#1 ;;; increase N_OUTP ;;; check N_OUTP is equal to #8 ;;; check no key (= DEBOCNT) NORMAL MOV L,#N_OUTP ; increase N_OUTP INCS A,@HL MOVZ @HL,A ADDS A,#8 ; A ← #8 C PNE @HL,A ; compare N_OUTP to A JP J_STRO ; go to stroble label MOV L,#KFLG ; CPBT @HL.0 ; check key flag JP ONKEY JPL RESET ; no key ONKEY CLR A ADDS A,#0FH OUT P3,@SL + A ; set port3 to ‘1’ MOV L,#DEBOCNT ; decrease DEBOCNT DECS A,@HL XCH @HL,A CPNZ @HL ; compare DEBOCNT TO #0 JP J1_MAIN JPL KEYSCAN J1_MAIN JPL MAIN J_STRO JPL STROBE

REMOTE CONTROL TX. 5- 24 PROBEKS51840/51850 CODE GENERATION This program generates data code and custom code. The custom code is determined according to diodes between input ports and output pin (P2.6). The data code is as follows: D0 D1 D2 D4 D5D3 D6 D7 KEY1 KEY0 KEY33 KEY32 KEY31 KEY63 0 00 0 0 0 0 0 00000001 1 1 1 1 0 0 0000 0 0 0 1 1 1 1 10 0 D0 D1 D2 D4 D5D3 D6 D7 KEY1 KEY0 KEY33 KEY32 KEY31 KEY63 0 00 0 0 0 0 0 00000001 1 1 1 1 0 0 0000 0 0 0 1 1 1 1 01 0 RAM DAT0 (D0-D3), DAT1_0 (D4-D7)RAM DAT0 (D0-D3), DAT1 (D4-D7) RAM Assingment CUS0 CUS1 CUS2 CUS3 DAT0 DAT2DAT1 DAT3 DAT1_0 DAT3_0 45H 49H H register selects #4 41HHL 40H CUS0; Custom code (c0-c3) CUS1: Custom code (c4-c7) CUS2: The complement of CUS0 CUS3: The complement of CUS1 DAT0: Data code (d0-d3)] DAT1: Data code (d4-d7) : → 32 key: 00000010, 63 key: 1111010 DAT2: The complement of DAT0 DAT3: The complement of DAT1 DAT1_0 Data code (d4-d7) : → 32 key: 00000100, 63 key: 1111100 DAT3_0 The complement of DAT1_0

REMOTE CONTROL TX. 5- 25 Program Flowchrt H #4 P2.6 LOW P2.13 LOW ; Select option pin ; Custom code productionPRODUCE CUS0 & CUS2 P2.13 HIGH PRODUCE CUS1 & CUS3 518CODE P2.6 HIGH DAT0 O_INP0 L DAT0 DAT1 #4 DAT1_0 #2 DAT0 O_INP1 P2.1 LOW DAT0 = #0FH ; Close option pin ; Indicator LED DAT1 #0 DAT1_0 #0 DAT _P0:DAT _P1: R_SHIFT: DAT0 shifts three times to left CARRY? DAT0 DAT0 + O_OUTP INCS DAT1 & DAT1_0 DAT2 the com- plement of DAT0 DAT3 the com- plement of DAT1 DAT1_0 the compl- ement of DATA 3.0 ; Check the end of debounce time S_CARRY: A_OUTP: Yes No No Yes RET Figure 5-13. Program Flowchart 4

REMOTE CONTROL TX. 5- 26 ORG 0300H JPL RESET KEYSCAN MOV H,#4 MOV L,#6 ; P2.6 ← low CLRB P2.(L) ; check custom code MOV L,#0DH ; CLRB P2.(L) ; IN A,P0 ; MOV L,#CUS2 ; CUS2 is the complement of CUS0 MOV @HL,A ; NOTI A ; DECS A ; MOV L,#CUS0 ; MOV @HL,A ; MOV L,#0DH SETB P2.(L) ; CUS3 is the complemen t of CUS1 IN A,P0 ; MOV L,#CUS3 ; MOV @HL,A ; NOTI A ; DECS A ; MOV L,#CUS1 ; MOVZ @HL,A ; MOV L,#6 ; high P2.6 SETB P2.(L) MOV L,#1 ; the indicator LED of a key input CLRB P2.(L)

REMOTE CONTROL TX. 5- 27 MOV H,#0 MOV L,#O_INP0 ; DAT0 ← O_INP0 MOV A,@HL MOV H,#4 MOV L,#DAT0 MOVZ @HL,A ADDS A,#0FH ; A ← #0fh CPNE @HL,A ; does input key exist in port0? JP DAT_P0 DAT_P1 MOV L,#DAT1 ; input key exists in port1 MOV @HL+,#04H ; DAT1 ← DAT1 + #4 MOV L,#DAT1_0 MOV @HL+,#02H ; DAT1_0 ← DAT1_0 + #2 MOV H,#0 ; DAT0 ← O_INP1 MOV L,#O_INP1 ; MOV A,@HL ; MOV H,#4 ; MOV L,#DAT0 ; MOVZ @HL,A ; JPL R_SHIFT ; DAT_P0 MOV L,#DAT1 ; clear DAT1 & DAT1_0 MOV @HL+,#0 MOV L,#DAT1_0 MOV @HL+,#0 MOV L,#DAT0 MOV H,#4 ; delay time MOV H,#4 ; MOV H,#4 ; MOV H,#4 ; MOV H,#4 ; JPL R_SHIFT

REMOTE CONTROL TX. 5- 28 ORG 0400H JPL RESET R_SHIFT MOV A,@HL ; DAT0 shifts thre e times to the left ADDS A,@HL ; MOV @HL,A ; ADDS A,@HL ; MOV @HL,A ; JP S_CARRY JP N_CARRY S_CARRY MOV L,#DAT1 ;if carry occurs, increase DAT1 & DAT1_0 XCH @HL,A ; INCS A ; XCH @HL,A ; MOV L,#DAT1_0 ; XCH @HL,A ; INCS A ; XCH @HL,A ; JP A_OUTP N_CARRY MOV H,#0 ; if carry doesn’t occur, delay time MOV H,#0 ; MOV H,#0 ; MOV H,#0 ; MOV H,#0 ; MOV H,#0 ; MOV H,#0 ; MOV H,#0 ;

REMOTE CONTROL TX. 5- 29 A_OUTP MOV H,#0 MOV L,#O_OUTP ; DAT0 ← DAT0 + O_OUTP ADDS A,@HL ; MOV H,#4 ; MOV L,#DAT0 MOV @HL,A ; NOT I A DECS A ; DAT2 ← complement of DAT0 MOV L,#DAT2 MOVz @HL,A MOV L,#DAT1 MOV A,@HL NOTI A ; DAT3 ← complement of DAT1 DECS A MOV L,#DAT3 MOVZ @HL,A MOV L,#DAT1_0 MOV A,@HL NOTI A DECS A MOV L,#DAT3_0 ; DAT3_0 ← complement of DAT 1_0 MOV @HL,A JPL TX

REMOTE CONTROL TX. 5- 30 KS51840/51850 SIGNAL TRANSMISSION This program is for signal transmissions in SAMSUNG standard format. If one key is pressed, two frames are transmitted consecutively. The repeat pulse is transmitted until key-off. The frame interval is 60 ms. Each frame consists of leader code, custom code, and data code: — Leader code (high level for 4.5 ms and low level for 4.5 ms) — 12-bit custom code — 8-bit data code Transmission Waveform 60 ms Frame Waveform Leader code 4.5 ms 4.5 ms 60 ms60 ms custom code (c0-c11) data code (d0-d7) Data Pulse 0.56 ms 1.125 ms data '0' 2.25 ms 0.56 ms data '1' Figure 5-14. Transmission Waveforms RAM Assignment This part is the same as for keyscan and code generation.

REMOTE CONTROL TX. 5- 31 KS51840/51850 Program Flowchart P2.9 & 2.10 LOW CONKEY + #0 518SAMTX CUS4 #0 P2.0 HIGH for 4.5 msec P2.0 LOW for 4.5 msec P2.0 HIGH for .56 msec P2.0 LOW delay as many as low number OUTPUT CUSTOM & DATA CODE DEBOCNT #1 CONKEY #1 delay for 60 msec ; select carrier frequency ; c8 #0 MAIN delay for 60 msec ; repeat waveform transmission ; until key off Figure 5-14. Ks51840/51850 Program Flowchart 5

REMOTE CONTROL TX. 5- 32 ORG 0500H JPL RESET TX MOV L,#9 ; select farrier frequency CLRB P2.(L) ; 37.9 kHz, 1/3 duty MOV L,#0AH ; clear P2.9 & 2.10 CLRB P2.(L) SIGOUT MOV L,#CUS4 ; custom code (c8-c11) ← #0 MOB @HL+,#0 ; if device is KS51910, c8 ← #1 MOV L,#0 ; high for delay time 4.5 msec SETB P2.(L) CALLL D4_5 MOV L,#0 CLRB P2.(L) ; low for delay time 4.5 msec CALLL D4_5D ;;; output custom code (c0-c11) & data code (d0-d7) MOV L,#CUS0 ; custom code (c0-c3) CALLL DATGEN MOV L,#CUS1 ; custom code (c4-c7) CALLL DATGEN MOV L,#CUS4 ; custom code (c8-c11) CALLL DATGEN MOV L,#DAT0 ; data code (d0-d3) CALLL DATGEN MOV L,#DAT1_0 ; data code (d4-d7) CALLL DATGEN MOV L,#1 DECS L JP .-1 MOV L,#0 ; EOB (end of bit) SETB P2.(L) ; high for .56msec CALLL D_560F MOV L,#0 CLRB P2.(L) JPL LOWCHEK

REMOTE CONTROL TX. 5- 33 ORG 0600H JPL RESET LOWCHEK MOV L,#CUS0 ; custom code (c0-c3) CALL LCHEK MOV L,#CUS1 ; custom code (c4-c7) CALL LCHEK MOV L,#CUS4 ; custom code (c8-c11) CALL LCHEK MOV L,#DAT0 ; data code (d0-d3) CALL LCHEK MOV L,#DAT1_01 ; the maximum value of upper bit is #3 MOV A,L ; data code (d4-d7) CALL LCHEK_1 ; check from the second bit ; If value of DAT1_0 is greater than #3, programmer must change instruction ; CALLLCHEK_1 to other instruction such as CALLCHECK_2 or CALL ; LCHEK. And you must check the fram interval (= 60 msec) SETDBT MOV H,#0 MOV L,#DEBOCNT ; DEBOCNT ← #1 MOV @HL+,#1 ;;; If conkey flag isn’t ‘0’, transmit repeat pulse ;;; otherwise, after setting, transmit again (two frames) CONCHEK MOV H,#0 MOV L,#CONKEY ; CONKEY == #0? CPNZ @HL ; If CONKEY is #0, CONKEY ← #1 JP LJ_MAIN ; transmit frame again MOV @HL+,#1 CALLL D4_5D ; time is 60 msec per frame CALLL D2_25 CALLL D1_125 MOV L,#0CH MOV H,#4 MOV H,#4 DECS L JP .-3 JPL SIGOUT

REMOTE CONTROL TX. 5- 34 LJ_MAIN CALL D1_125 JPL MAIN LCHEK MOV A,L CPBT @HL,3 ; if @hl.3 is low, call d2_25d. JP LCHEK_2 CALLL D2_25D LCHEK_2 MOV L,A CPBT @HL.2 ; if @hl.2 is low, call d2_25d. JP LCHEK_1 CALLL D2_25D LCHEK_1 MOV L,A CPBT @HL.1 ; if @hl.1 is low, call d2_25d. JP LCHEK_0 CALLL D2_25D LCHEK_0 MOV L,A CPBT @HL.0 ; if @hl. 0 is low, call d2_25d. JP LCHEK_R CALLL D2_25D LCHEK_R RET OR G 0700H JPL RESET DATGEN MOV A,L CALL D_560 ; high for .56 msec CPBT @HL.0 ; if @hl.0 is high, low for 2.25 msec. CALL D2_25 ; otherwise, low for 1.125 msec. CALL D1_125

REMOTE CONTROL TX. 5- 35 CALL D_560 ; high for .56 msec CPBT @HL.1 ; if @hl.1 is high, low for 2.25 msec. CALL D2_25 ; otherwise, low for 1.125 msec. CALL D1_125 CALL D_560 ; high for .56 msec CPBT @HL.2 ; if @hl.2 is high, low for 2.25 msec. CALL D2_25 ; otherwise, low for 1.125 msec. CALL D1_125 CALL D_560 ; high for .56 msec CPBT @HL.3 ; if @hl.3 is high, low for 2.25 msec. CALL D2_25 ; otherwise, low for 1.125 msec. CALL D1_125D RET D_560 MOV L,#0 SETB P2,(L) MOV L,#0CH MOV H,#4 DECS L JP .-2 MOV H,#4 MOV L,#0 CLRB P2.(L) MOV L,A RET D4_5D MOV L,#02H ; delay time 4.5 msec JP .+2 D4_5 MOV L,#06H DECS L JP -1 MOV L,#05H CLR A ADD S A,#0BH MOV H,#4 D_A DECS A JP .-2 DECS L JP .-6

REMOTE CONTROL TX. 5- 36 D2_25D MOV L,#0EH JP .+2 D2_25 MOV L,#0FH MOV H,#4 DECS L JP .-2 D1_125 MOV L,#0AH JP .+6 D1_125D MOV L,#08H JP .+8 D_560F MOV L,#0BH ; delay time .56 msec (for EOB) MOV H,#4 MOV H,#4 DECS L JP .-2 RET org 0800h jpl reset org 0900h jpl reset org oaooh jpl reset org obooh jpl reset org ocooh jpl reset org odooh jpl reset org oeooh jpl reset

REMOTE CONTROL TX. 5- 37 STROBE MOV L, #N_OUTP CPBT @HL.2 ; If N_OUTP.2 is set, go to parall (parallel port) JP PARALL ; otherwise, go to serial (serial port) SERIAL MOV L, @HL ; INCS L ; SETB P2.(L)

MENU menu.src 11/27/1997 1 of 1 pp. ;/// If you want to use the following files, run only after //// ;/// removing the comments(;) in the first column. You can //// ;/// modify these files, but be sure to verify the ROM address //// ;/// of transmit files. Also you must reset debounce time //// ;/// (=DEBOCNT) by a frame size. DEBOCNT is located in the //// ;/// transmit file. //// ;1. SELECT .DEF FILE ;(1) CHIP C:\\SMDSII\\DATA\\51840.DEF ;2. SELECT EQU FILE ; ===> RAM assignment ;(1) INCLUDE C:\\SMDSII\\HEAD\\518EQU.H ;3. SELECT KEYSCAN FILE ; ===> double keys check in key matrix(64-key) ;(1) INCLUDE C:\\SMDSII\\SRC\\518KSCAN.SRC ;4. SELECT CUSTOM CODE & DATA CODE PRODUCTION FILE ; ===> when a key press, code prodouction ;(1) INCLUDE C:\\SMDSII\\SRC\\518CODE.SRC ;5. SELECT TRANSMISSION FILE ; ===> remocon tx. waveform. ;; ==> samsung tx. format INCLUDE C:\\SMDSII\\SRC\\518SAMTX.SRC ;; ==> sony tx. format ; INCLUDE C:\\SMDSII\\SRC\\518SNYTX.SRC ;; ==> rc-5 tx. format ; INCLUDE C:\\SMDSII\\SRC\\518RC5TX.SRC ;; ==> toshiba tx. format ; INCLUDE C:\\SMDSII\\SRC\\518TOSTX.SRC ;; ==> rca tx. format ; INCLUDE C:\\SMDSII\\SRC\\518RCATX.SRC ;; ==> panasonic tx. format ; INCLUDE C:\\SMDSII\\SRC\\518PANTX.SRC ;; ==> mitsubish tx. format ; INCLUDE C:\\SMDSII\\SRC\\518MITTX.SRC ;; ==> nec(custom code 8-bit) tx. format ; INCLUDE C:\\SMDSII\\SRC\\518NECTX.SRC ;; ==> nec(custom code 16-bit)tx. format ; INCLUDE C:\\SMDSII\\SRC\\518_16TX.SRC END

518SNYTX 518SNYTX.src 11/27/1997 1 of 2 pp. ;;for SONY FORMAT ;;If a key is pressed, after a frame is transmitted,repeat pulse is ;;transmitted until key off. ;;the frame interval is 45 msec. ;; data '1' | | data '0' | | ;; | | | | ;; 0.6ms 1.2ms 0.6ms 0.6ms ORG 0500H JPL RESET TX MOV L,#9 ;select carrier frequency CLRB P2.(L) ;40kHz -> 37.9 KHz MOV L,#0AH ;clear p2.9 & p2.10 CLRB P2.(L) MOV L,#0 ;high for delay time 2.4msec SETB P2.(L) CALLL D2_4 MOV L,#DAT0 ;data code (d0-d3) CALLL DATGEN MOV L,#DAT1_0 ;data code (d4-d6) CALLL DATGEN2 MOV L,#CUS0 ;custom code (c0 ~c3) CALLL DATGEN MOV L,#CUS1 ;custom code (c4) CALLL DATGEN0 MOV L,#1 ;finish code delay time DECS L JP .-1 MOV L,#0 CLRB P2.(L) MOV L,#DAT0 ;data code (d0 ~d3) CALLL LCHEK MOV L,#DAT1_0 ;data code (d4 ~d6) MOV A,L CALLL LCHEK_2 MOV L,#CUS0 ;custom code(c0-c3) CALLL LCHEK MOV L,#CUS1 ;custom code(c4) MOV A,L CALLL LCHEK_0 JPL S_DBCNT 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 ORG 0600H JPL RESET DATGEN MOV A,L CALL D0_6 ;high for 0.6 msec CPBT @HL.0 ;if @hl.0 is high, low for 1.2msec CALL D1_2 ;otherwise, low for 0.6msec CALL D0_6H CALL D0_6 ;high for 0.6msec CPBT @HL.1 ;if @hl.1 is high, low for 1.2msec CALL D1_2 ;otherwise, low for 0.6msec CALL D0_6H CALL D0_6 ;high fo r 0.6 msec CPBT @HL.2 ;if @hl.2 is high, low for 1.2msec CALL D1_2 ;otherwise, low for 0.6msec CALL D0_6H CALL D0_6 ;high for 0.6msec CPBT @HL.3 ;if @hl.3 is high, low for 1.2msec CALL D1_2 ;otherwise, low for 0.6msec CALL D0_6HD RET DATGEN2 MOV A,L CALL D0_6 ;check @hl.0 - @hl.2 CPBT @HL.0 CALL D1_2 CALL D0_6H CALL D0_6 CPBT @HL.1 CALL D1_2 CALL D0_6H CALL D0_6 CPBT @HL.2 CALL D1_2 CALL D0_6HD RET DATGEN2 MOV A,L CALL D0_6 ;check only @hl.0 CPBT @HL.0 CALL D1_2 CALL D0_6HD RET ;;;delay 0.6msec D0_6 MOV L,#0 CLRB P2.(L) MOV L,#0DH MOV H,#4 DECS L

518SNYTX 518SNYTX.src 11/27/1997 2 of 2 pp. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 JP .-2 MOV L,#0 SETB P2.(L) MOV L,A RET ;;delay 1.2msec D1_2L MOV L,#0 JP .+2 D1_2 MOV L,#01H MOV H,#4 DECS L JP .-2 ;;;delay 0.6msec for EOB D0_6H MOV L,#0BH JP .+3 D0_6HD MOV L,#09H MOV H,#4 MOV H,#4 DECS L JP .-2 RET ORG 0700H JPL RESET S_DBCNT CALL D45 MOV H,#0 MOV L,#DEBOCNT ;re-setting debounce time MOV @HL+,#3 JPL MAIN LCHEK MOV A,L CPBT @HL.3 ;if @hl.3 is low, call d1_2l JP LCHEK_2 CALLL D1_2L LCHEK_2 MOV L,A CPBT @HL.2 ;if @hl.2 is low, call d1_2l JP LCHEK_1 CALLL D1_2L LCHEK_1 MOV L,A CPBT @HL.1 ;if @hl.1 is low, call d1_2l JP LCHEK_0 CALLL D1_2L LCHEK_0 MOV L,A CPBT @HL.0 ;if @hl.0 is low, call d1_2l JP LCHEK_R CALLL D1_2L 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 LCHEK_R RET D45 MOV L,#0EH MOV H,#4 MOV H,#4 MOV H,#4 MOV H,#4 DECS L JP .-5 MOV L,#0FH JP .+2 D2_4 MOV L,#0DH CLR A ADDS A,#3 DECS A JP .-1 DECS L JP .-5 MOV H,#4 MOV H,#4 MOV H,#4 MOV H,#4 RET org 0800h jpl reset org 0900h jpl reset org 0a00h jpl reset org 0b00h jpl reset org 0c00h jpl reset org 0d00h jpl rese t org 0e00h jpl reset

518rc5tx 5188rc5tx.src 11/27/1997 1 of 2 pp. ;;for RC-5 FORMAT ;If a key is pressed, after a frame is transmitted, repeat pulse is ;transmitted until key off, and every time a key is released, control ;bit is converted. The frame interval is 64 bits (= 113.8 msec). ; start bit | | custom code | data code | ; control bit ; | | ; ^ v ; | | | | ; = 1bit time ; < rising edge > < falling edge > ORG 0500H JPL RESET TX MOV L,#9 ;select carrier frequency CLRB P2.(L) ;(1/3 duty, fosc/12) MOV L,#0AH ;37.9 kHz CLRB P2.(L) DEBOSET MOV H,#0 MOV L,#DEBOCNT MOV @HL+,#0FH ;;;if continuous flag is reset(= '0'), ;;;continuous flag(=conkey) is set to '1' and ;;;control flag is converted.(namely, every time key release) MOV H,#0 MOV L,#CONKEY CPBT @HL.0 JP STRDLY MOV @HL+,#1 ;setting conkey flag to '1' MOV L,#CTLFLG ;convert control flag (= CTLFLG) CPBT @HL.0 JP .+3 C_LOW MOV @HL+,#1 ;if CTLFLG is low, CTLFLG <- #1 JP .+3 ;otherwise, CTLFLG <- #0 C_HIGH MOV @HL+,#0 MOV H,#4 ;delay time JP START STRDLY MOV L,#2 DECS L JP .-1 MOV H,#4 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 START CALLL DAT_1 ;the first start bit MOV L,#0 DECS L JP .-1 MOV H,#4 JPL CTLOUT D113_8 MOV L,#05H MOV H,#4 MOV H,#4 MOV H,#4 MOV H,#4 DECS L JP .-5 RET ORG 0600H JPL RESET CTLOUT CALLL DAT_1 ;the second start bit MOV H,#0 MOV L,#CTLFLG ;control bit CALLL DATGEN0 MOV L,#CUS0 ;custom code (c0) CALLL DATGEN0 MOV L,#CUS0 ;custom code (c1) CALLL DATGEN1 MOV L,#CUS0 ;custom code (c2) CALLL DATGEN2 MOV L,#CUS0 ;custom code (c3) CALLL DATGEN3 MOV L,#CUS1 ;custom code (c4) CALLL DATGEN0 MOV L,#DAT0 ;data code (d0) CALLL DATGEN0 MOV L,#DAT0 ;data code (d1) CALLL DATGEN1 MOV L,#DAT0 ;data code (d2) CALLL DATGEN2 MOV L,#DAT0 ;data code (d3) CALLL DATGEN3 MOV L,#DAT1_0 ;data code (d4) CALLL DATGEN0 MOV L,#DAT1_0 ;data code (d5) CALLL DATGEN1

518rc5tx 5188rc5tx.src 11/27/1997 2 of 2 pp. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 MOV L ,#2 DECS L JP .-1 MOV L,#0 CLRB P2.(L) MOV L,#07H A_F CLR A ADDS A,#0FH S_F MOV H,#4 MOV H,#4 MOV H,#4 MOV H,#4 MOV H,#4 DECS A JP S_F DECS L JP A_F CALLL D113_8 JPL MAIN ORG 0700H JPL RESET DATGEN0 CPBT @HL.0 ;if @hl.0 is high, rising edge. JP .+3 ;otherwise, falling edge. CALL DAT_0 ;falling edge JP .+2 CALL DAT_1 ;rising edge RET DATGEN1 CPBT @HL.1 ;if @hl.1 is high, rising edge. JP .+3 ;otherwise, falling edge. CALL DAT_0 JP .+2 CALL DAT_1 RET DATGEN2 CPBT @HL.2 ;if @hl.2 is high, rising edge. JP .+3 ;otherwise, falling edge. CALL DAT_0 JP .+2 CALL DAT_1 RET DATGEN3 CPBT @HL.3 ;if @hl.3 is high, rising edge. JP .+3 ;otherwise, falling edge. CALL DAT_0 JP .+2 CALL DAT_1 RET 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 DAT_0 MOV L,#0 SETB P2.(L) MOV L,#0FH ;high for 0.889 msec MOV H,#4 MOV H,#4 DECS L JP .-3 MOV L,#0 CLRB P2.(L) MOV L,#0CH ;low for 0.889 msec MOV H,#4 MOV H,#4 DECS L JP .-3 MOV H,#4 MOV H,#4 MOV H,#4 RET DAT_1 MOV L,#0 CLRB P2.(L) MOV L,#0FH ;low for 0.889 msec MOV H,#4 MOV H,#4 DECS L JP .-3 MOV L,#0 SETB P2.(L) MOV L,#0DH ;high for 0.889 msec MOV H,#4 MOV H,#4 DECS L JP .-3 RET org 0800h jpl reset org 0900h jpl reset org 0a00h jpl reset org 0b00h jpl reset org 0c00h jpl reset org 0d00h jpl reset org 0e00h jpl reset

518TOSTX 518TOSTX.src 11/27/1997 1 of 3 pp. ;;for TOSHIBA FORMAT ;;If a key is pressed, after a frame is transmitted, continuous pulse ;;is transmitted until key off ;;The frame interval is 108 msec or 126 msec according as custom code. ;;Namely, if the high count of custom code (c0-c7) is greater then #4, ;;delay time is 126msec, otherwise, delay time is 108 msec. But, ;;continuous pulse is only 108msec. A frame consists of leader code, ;;custom code and data code. ;;-- leader code consists of high for 4.5 msec and low for 4.5 msec ;;-- custom code consists of 16-bit (= custom code (c0-c7) & custom ;; code (c0-c7)). ;;-- data code consists of 16-bit (= data code (d0-d7) & complement ;; of data code) ;;* transmission waveform * ;; 4.5m 4.5m | |EOB(end of bit) ;; |<--->| ;; '1' or '0' according as complement of custom code 'c0' ;; namely, if 'c0' of custom code is '1', the value is '0' ;; otherwise, the value is '1'. ;; | | | | ;; 0.56ms 0.56ms ;; 1.125msec 2.25msec ORG 0500H JPL RESET TX MOV L,#09H ;select carrier frequency CLRB P2.(L) ;37.9 kHz, 1/3 duty MOV L,#0AH CLRB P2.(L) MOV H,#0 MOV L,#CONKEY ;check continuous key CPNZ @HL JP SIGCON JP SIGOUT SIGCON MOV L,#DEBOCNT ;setting debounce time again MOV @HL+,#0H 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 MOV L,#0 SETB P2.(L) CALLL D4_5 ;high for delay 4.5 msec MOV L,#0 ;low for delay 4.5 msec CLRB P2.(L) CALLL D4_5 MOV L,#0 SETB P2.(L) CALLL D_560F ;;;The value is determined by the complement of custom code (=c0) ----- MOV L,#0 CLRB P2.(L) MOV L,#CUS0 CPBT @HL.0 JP .+3 CALLL D2_25 CALLL D1_125 MOV L,#0 SETB P2.(L) CALLL D_560F ;EOB MOV L,#0 CLRB P2.(L) J_SIGC MOV L,#CUS0 CPBT @HL.0 JP .+2 JP .+3 CALLL D2_25D MOV L,#0FH CALLL D_A MOV L,#04H CALLL D_A MOV L,#03H DECS L JP .-1 JPL MAIN} ORG 0600H JPL RESET SIGOUT MOV @HL+,#1 ;CONKEY <- #1 MOV L,#0 SETB P2.(L) CALLL D4_5 ;high for delay time 4.5 msec MOV L,#0 CLRB P2.(L) CALLL D4_5L ;low for delay time 4.5 msec MOV L,#CUS0 ;output custom code (c0-c3)

518TOSTX 518TOSTX.src 11/27/1997 2 of 3 pp. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 CALLL CDGEN MOV L,#CUS1 ;output custom code (c4-c7) CALLL CDGEN MOV L,#CUS0 ;repeat above custom code CALLL CDGEN MOV L,#CUS1 CALLL CDGEN MOV L,#DAT0 ;output data code (d0-d3) CALLL CDGEN MOV L,#DAT1 ;output data code (d4-d7) CALLL CDGEN MOV L,#DAT2 ;complement of data code (d0-d3) CALLL CDGEN MOV L,#DAT3 ;complement of data code (d4-d7) CALLL CDGEN MOV L,#1 DECS L JP .-1 MOV H,#4 MOV L,#0 SETB P2.(L) ;high for delay 560 usec CALLL D_560F MOV L,#0 CLRB P2.(L) ;;; H_CHEK CLR A MOV L,#CUS0 CALLL H_0 MOV L,#CUS1 CALLL H_0 JPL FDLY ORG 0700H JPL RESET ;;If A is greater than #4, call delay 126 msec ;;;otherwise, call delay 108msec FDLY MOV H,#0 MOV L,#DEBOCNT ADDS A,#0BH JP J_126 MOV @HL+,#6 ;setting debounce time MOV L,#3 ;for 108 msec JP J_E J_126 MOV @HL+,#0AH ;setting debounce time MOV L,#3 DECS L JP .-1 MOV L,#0 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 J_E CALL D_A L_DELAY MOV L,#CUS0 ;custom code (c0-c3) CALLL LOWDLY MOV L,#CUS1 CALLL LOWDLY ;custom code (c4-c7) MOV L,#CUS0 ;custom code (c0-c3) CALLL LOWDLY MOV L,#CUS1 CALLL LOWDLY ;custom code (c4-c7) JPL MAIN H_0 CPBT @HL.0 ;count up high data JP .+2 JP H_1 INCS A ;if data is high, increase value of A H_1 CPBT @HL.1 ;count up high data JP .+2 JP H_2 INCS A H_2 CPBT @HL.2 ;count up high data JP .+2 JP H_3 INCS A H_3 CPBT @HL.3 ;count up hi gh data JP .+2 JP H_R INCS A H_R RET D4_5 MOV L,#1 ;delay 4.5msec DECS L JP .-1 MOV H,#4 D4_5L MOV L,#5 D_A CLR A ADDS A,#0FH MOV H,#4 DECS A JP .-2 DECS L JP .-6 MOV L,#07H DECS L JP .-1 RET

518TOSTX 518TOSTX.src 11/27/1997 3 of 3 pp. 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 ORG 0800H JPL RESET CDGEN MOV A,L CALL D_560 ;high for 0.56msec CPBT @HL.0 ;if @HL.0 is high, low for 2.25 msec CALL D2_25 ;otherwise, low for 1.125msec CALL D1_125 CALL D_560 ;high for 0.56msec CPBT @HL.1 ;if @HL.1 is high, low for 2.25msec CALL D2_25 ;otherwise, low for 1.125msec CALL D1_125 CALL D_560 ;high for 0.56msec CPBT @HL.2 ;if @HL.2 is high, low for 2.25msec CALL D2_25 ;otherwise, low for 1.125msec CALL D1_125 CALL D_560 ;high for 0.56msec CPBT @HL.3 ;if @HL.3 is high, low for 2.25msec CALL D2_25 ;otherwise, low for 1.125msec CALL D1_125F RET D2_25D MOV L,#0EH JP .+2 D2_25 MOV L,#0FH DECS L JP .-1 JP .+6 D1_125 MOV L,#0AH JP .+6 D1_125F MOV L,#08H JP .+4 D_560F MOV L,#0BH MOV H,#4 MOV H,#4 DECS L JP .-2 RET D_560 MOV L,#0 SETB P2.(L) MOV L,#0CH MOV H,#4 DECS L JP .-2 MOV H,#4 MOV L,# 0 CLRB P2.(L) MOV L,A RET LOWDLY MOV A,L CPBT @HL.3 ;if @HL.3 is low, call D2_25D JP LOW_2 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 CALL D2_25D LOW_2 MOV L,A CPBT @HL.2 ;if @HL.2 is low, call D2_25D JP LOW_1 CALL D2_25D LOW_1 MOV L,A CPBT @HL.1 ;if @HL.1 is low, call D2_25D JP LOW_0 CALL D2_25D LOW_0 MOV L,A CPBT @HL.0 ;i f @HL.0 is low, call D2_25D JP LOW_R CALL D2_25D LOW_R RET org 0900h jpl reset org 0a00h jpl reset org 0b00h jpl reset org 0c00h jpl reset org 0d00h jpl reset org 0e00h jpl reset

518RCATX 518RCATX.src 11/27/1997 1 of 2 pp. ;;for RCA FORMAT ;;If a key is pressed, a frame is transmitted. And repeat pulse is ;;transmitted until key off. The frame gap is 8 msec. The head pulse ;;of the first frame is high for 20 msec and low for 4 msec. ;;But, the head pulse of continuous frame is high for 4 msec and low ;;for 4 msec. ;;* transmission waveform * ;;<-20ms->4msec 8ms 4ms 4ms 8ms ;; ____ ;;| | | custom code | data code(8-bit) | custom code| data code | | ;; 4ms 4ms (4-bit) 1ms ;; | | | | ;; | | | | ;; 0.5ms 1ms 0.5ms 2ms ORG 0500H JPL RESET TX MOV L,#9 ;select carrier frequency SETB P2.(L) ;56.9 kHz, 1/2 duty MOV L,#0AH CLRB P2.(L) MOV H,#0 MOV L,#CONKEY ;check continuous key CPNZ @HL JP SIGCON SIGOUT MOV L,#CONKEY ;setting conkey flag to '1' MOV @HL+,#1 MOV L,#0 SETB P2.(L) CALLL D20 ;high for delay 20 msec JP .+5 SIGCON MOV L,#0 SETB P2.(L) CALLL D4 ;high for delay 4 msec MOV L,#0 ;low for delay 4 msec CLRB P2.(L) CALLL D4_L MOV H,#4 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 MOV L,#CUS0 ;custom code 4bits CALLL DATGEN MOV L,#DAT0 ;data code 8bits CALLL DATGEN MOV L,#DAT1_0 CALLL DATGEN MOV L,#CUS2 ;complement of custom code CALLL DATGEN MOV L,#DAT2 ;complement of data code CALLL DATGEN MOV L,#DAT3_0 CALLL DATGEN MOV L,#1 DECS L JP .-1 MOV L,#0 SETB P2.(L) CALLL D1 ;high for delay 1 msec MOV L,#1 DECS L JP .-1 MOV L,#0 CLRB P2.(L) MOV H,#0 MOV L,#DEBOCNT MOV @HL+,#1 CALLL D8 JPL MAIN ORG 0600H JPL RESET ;;;data & custom code generation ;;;high for .5 msec through p2.0 ;;;If the value is '1', low for 1 msec ;;;otherwise, low for 2 msec. DATGEN MOV A,L CALL D0_5 CPBT @HL.0 JP .+2 CALL D2 CALL D1 CALL D0_5 CPBT @HL.1

518RCATX 518RCATX.src 11/27/1997 2 of 2 pp. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 JP .+2 CALL D2 CALL D1 CALL D0_5 CPBT @HL.2 JP .+2 CALL D2 CALL D1 CALL D0_5 CPBT @HL.3 JP .+2 CALL D2 CALL D1_F RET D0_5 MOV L,#0 SETB P2.(L) MOV L,#0BH MOV H,#4 DECS L JP .-2 MOV L,#0 CLRB P2.(L) MOV L,A RET D2 MOV L,#01H ;delay for 2 msec MOV H,#4 MOV H,#4 MOV H,#4 DECS L JP .-4 MOV H,#4 MOV H,#4 D1_F MOV L,#0DH ;be used in the fourth bit MOV H,#4 MOV H,#4 JP .+2 D1 MOV L,#0FH ;delay for 1 msec MOV H,#4 MOV H,#4 MOV H,#4 DECS L JP .-3 RET ORG 0700H JPL RESET D20 CALL D4 CALL D4 CALL D4 MOV L,#0EH MOV H,#4 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 DECS L JP .-2 MOV H,#4 MOV L,#0FH JP D_A D8 MOV L,#08H ;delay for 8 msec DECS L JP .-1 MOV L,#02H JP D_A D4 MOV L,#06H ;delay for 4 msec MOV H,#4 JP .+2 D4_L MOV L,#04H DECS L JP .-1 MOV L,#07H D_A CLR A ADDS A,#09H MOV H,#4 DECS A JP .-2 MOV H,#4 DECS L JP .-7 RET org 0800h jpl reset org 0900h jpl reset org 0a00h jpl reset org 0b00h jpl reset org 0c00h jpl reset org 0d00h jpl reset org 0e00h jpl reset

518PANTX 518PANTX.src 11/27/1997 1 of 2 pp. ;;for PANASONIC FORMAT ;;If a key is pressed, a frame is transmitted, and repeat pulse is ;;transmitted until key off. The frame interval is 100 msec. ;;* transmission waveform * ;;| | ;;| | ;;v v ;; ____ ;;head pulse<- custom code -><-data code -><-custom code-><-- data code --> ;; 5bits 6bits 5bits 6bits ;; head | | data'0' | | data'1' | | ;; 3.4ms 3.4ms 0.8ms 2.4ms ;; 0.9ms 0.9ms ORG 0500H JPL RESET TX MOV L,#09H ;carrier frequency(= 56.9 kHz,1/2 duty) SETB P2.(L) ;2.9 <- high, 2.10 <- low MOV L,#0AH CLRB P2.(L) MOV H,#4 MOV L,#0 SETB P2.(L) CALLL D3_4 ;high for delay 3.4 msec MOV L,#0 CLRB P2.(L) ;low for delay 3.4 msec CALLL D3_4L MOV L,#CUS0 ;output custom code(c0 - c3) CALLL DATGEN MOV L,#CUS1 ;output custom code(c4) CALLL DATGEN0 MOV L,#DAT0 ;output data code(d0 - d3) CALLL DATGEN MOV L,#DAT1_0 ;output data code(d4,d5) CALLL DATGEN1 ; MOV L,#CUS2 ;complement of custom code(c0-c3) 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 CALLL DATGEN MOV L,#CUS3 ;complement of custom code(c4) CALLL DATGEN0 MOV L,#DAT2 CALLL DATGEN ;complement of data code(d0-d3) MOV L,#DAT3_0 CALLL DATGEN1 ;complement of data code(d4,d5) MOV H,#4 ;delay time JPL E_OF ORG 0600H JPL RESET E_OF MOV H,#4 CALLL D0_9 ;finished bit CALLL D100 MOV H,#0 MOV L,#DEBOCNT MOV @HL+,#06H JPL MAIN ORG 0700H JPL RESET DATGEN MOV A,L CALLL D0_9 ;high for 0.9 msec CPBT @HL.0 ;if @hl.0 is high, low for 2.4 msec. CALL D2_4 ;otherwise, low for 0.8 msec. CALL D0_8 CALLL D0_9 ;high for 0.9 msec CPBT @HL.1 ;if @hl.1 is high, low for 2.4 msec. CALL D2_4 ;otherwise, low for 0.8 msec. CALL D0_8 CALLL D0_9 ;high for 0.9 msec CPBT @HL.2 ;if @hl.2 is high, low for 2.4 msec. CALL D2_4 ;otherwise, low for 0.8 msec. CALL D0_8 CALLL D0_9 ;high for 0.9 msec CPBT @HL.3 ;if @hl.3 is high, low for 2.4 msec. CALL D2_4 ;otherwise, low for 0.8 msec. CALL D0_8F RET DATGEN1 MOV A,L ;check @hl.0 - hl.1 CALLL D0_9 CPBT @HL.0

518PANTX 518PANTX.src 11/27/1997 2 of 2 pp. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 CALL D2_4 CALL D0_8 CALLL D0_9 CPBT @HL.1 CALL D2_4 CALL D0_8F RET DATGEN0 MOV A,L ;check only @hl.0 CALLL D0_9 CPBT @HL.0 CALL D2_4 CALL D0_8F RET D2_4 MOV L,#0DH ;delay for 2.4 msec MOV H,#4 MOV H,#4 MOV H,#4 DECS L JP .-4 MOV H,#4 MOV H,#4 MOV H,#4 D0_8F MOV L,#0AH ;delay for .8 msec JP .+4 D0_8 MOV L,#0BH MOV H,#4 MOV H,#4 DECS L JP .-3 MOV H,#4 RET ORG 0800H JPL RESET D100 MOV L,#4 CLR A ADDS A,#0AH MOV H,#4 DECS A JP .-2 DECS L JP .-6 MOV L,#0CH DECS L JP .-1 D3_4 MOV L,#2 ;delay for 3.4 msec DECS L JP .-1 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 D3_4L MOV L,#04H CLR A ADDS A,#0EH MOV H,#4 DECS A JP .-2 DECS L JP .-6 RET D0_9 MOV L,#0 SETB P2.(L) MOV L,#0CH MOV H,#4 MOV H,#4 MOV H,#4 DECS L JP .-4 MOV H,#4 MOV L,#0 CLRB P2.(L) MOV L,A RET org 0900h jpl reset org 0a00h jpl reset org 0b00h jpl reset org 0c00h jpl reset org 0d00h jpl reset org 0e00h jpl reset

518MITTX 518MITTX.src 11/27/1997 1 of 2 pp. ;for MITSUBISHI FORMAT ;If a key is pressed, a frame waveform is transmitted. And repeat ;pulse is transmitted until key off. The frame interval is 60 msec. ;Separator is between custom code and data code. ;|<- leader code ->|<--custom code -->| |seperator|<--data code ->| ; | | | | ; | | data '0' | | data '1' ; 1msec ; SEPARATOR ;The separator delimits custom code and data code and consists of low ;for 4 msec. The separator can be determined at the receiver to ;avoid interference with other remote control system and to establish ;a system with very few operation errors. ORG 0500H JPL RESET TX MOV L,#9 CLRB P2.(L) ;clear p2.9 & p2.10 MOV L,#0AH CLRB P2.(L) MOV H,#4 ;H register selects file #4 MOV L,#0 SETB P2.(L) CALLL D8 ;high for delay 8 msec MOV L,#0 CLRB P2.(L) MOV H,#4 MOV H,#4 CALLL D4 ;low for delay 4 msec MOV L,#CUS0 CALLL CDGEN ;output custom code (c0 - c3) MOV L,#CUS1 CALLL CDGEN ;output custom code (c4 - c7) MOV H,#4 MOV H,#4 MOV H,#4 MOV H,#4 CALLL D0_5 ;high for delay 0.5 msec CALLL D4 ;separator = low for delay 4 msec 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 MOV L,#DAT0 CALLL CDGEN ;output data code (d0 - d3) MOV L,#DAT1_0 CALLL CDGEN ;output data code (d4 - d7) MOV H,#4 MOV H,#4 JPL S_DBCNT ORG 0600H JPL RESET ;;;low value checksum ;;;all values are supposed as high ;;;If the value is low, delay time for 1 msec. S_DBCNT CALLL D0_5 ;high for delay 0.5 msec MOV H,#0 MOV L,#DEBOCNT MOV @HL+,#1 F_DELAY CALL D60 ;;;check low number of custom code & data code LOWSUM MOV H,#4 MOV L,#CUS0 ;custom code (c0 - c3) CALL LOWCHEK MOV L,#CUS1 ;custom code (c4 - c7) CALL LOWCHEK MOV L,#DAT0 ;data code (d0 - d3) CALL LOWCHEK MOV L,#DAT1_0 ;data code (d4 - d7) CALL LOWCHEK JPL MAIN LOWCHEK MOV A,L CPBT @HL.0 JP LOW_1 CALLL D2_F ;add 1 msec LOW_1 MOV L,A CPBT @HL.1 JP LOW_2 CALLL D2_F ;add 1 msec LOW_2 MOV L,A CPBT @HL.2 JP LOW_3 CALLL D2_F ;add 1 msec LOW_3 MOV L,A CPBT @HL.3

518MITTX 518MITTX.src 11/27/1997 2 of 2 pp. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 JP LOW_R CALLL D2_F ;add 1 msec LOW_R RET D60 MOV L,#0FH MOV H,#4 DECS L JP .-2 MOV L,#03H JP D_A D8 MOV L,#0EH DECS L JP .-1 MOV L,#9 JP D_A D4 MOV L,#4 D_A CLR A ADDS A,#0CH D_A1 MOV H,#4 MOV H,#4 DECS A JP .-3 DECS L JP .-7 MOV L,#3 DECS L JP .-1 RET ORG 0700H JPL RESET CDGEN MOV A,L CALL D0_5 ;high for 0.5 msec CPBT @HL.0 CALL D2 ;If HL.0 is high, low for 2 msec CALL D1 ; " low, low for 1 msec CALL D0_5 ;high for 0.5 msec CPBT @HL.1 ;if HL.1 is high, low for 2 msec CALL D2 ;otherwise, low for 1 msec CALL D1 CALL D0_5 ;high for 0.5 msec CPBT @HL.2 ;if HL.2 is high, low for 2 msec CALL D2 ;otherwise, low for 1 msec CALL D1 CALL D0_5 ;high for 0.5 msec CPBT @HL.3 ;if HL.3 is high, low for 2 msec 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 CALL D2 ;otherwise, low for 1 msec CALL D1_F RET D2_F MOV L,#09H JP .+3 D2 MOV L,#0AH JP .+4 MOV H,#4 MOV H,#4 MOV H,#4 DECS L JP .-4 D1_F MOV L,#5 JP .+2 D1 MOV L,#7 MOV H,#4 DECS L JP .-2 MOV H,#4 MOV H,#4 RET D0_5 MOV L,#0 SETB P2.(L) MOV L,#0BH MOV H,#4 DECS L JP .-2 MOV L,#0 CLRB P2.(L) MOV L,A RET org 0800h jpl reset org 0900h jpl reset org 0a00h jpl reset org 0b00h jpl reset org 0c00h jpl reset org 0d00h jpl reset org 0e00h jpl reset

518NECTX 518NECTX.src 11/27/1997 1 of 2 pp. ;; for NEC format ;;If a key pressed, a frame waveform is transmitted. And, continuous ;;pulse is transmitted until key off. The frame interval is 108 msec. ;;A frame consists of leader code, custom code, data code. ;;-- leader code consists of high for 9 msec and low for 4.5 msec. ;;-- custom code consists of 16-bit (custom code 8-bit,complement of ;; custom code 8-bit) ;;-- data code consists of 16-bit (data code 8-bit,complement of data ;; code 8-bit) ;;* transmission waveform * ;;<- leader ->|<-custom code->|<-custom code->|<-data code->|<-data code->| ;; 8bits 8bits 8bits 8bits ;; | | | | ;; |<-->| ;; 2.25msec ;; __ __ ;; | | | | ;; | | data '0' | | data '1' ;; 0.56ms 0.56msec ORG 0500H JPL RESET TX MOV L,#9 ;select carrier frequency CLRB P2.(L) ;(1/3 duty, 37.9 kHz) MOV L,#0AH ;clear p2.9 & p2.10 CLRB P2.(L) MOV H,#0 MOV L,#CONKEY ;if CONKEY is not zero, CPNZ @HL ;tx. continuous signal JP J_SIGCON SIGOUT MOV @HL+,#1 MOV L,#0 SETB P2.(L) CALLL D9 ;high for delay 9 msec MOV L,#0 CLRB P2.(L) 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 CALLL D4_5 ;low for delay 4.5 msec MOV L,#CUS0 CALLL DATGEN ;custom code (c0 - c3) MOV L,#CUS1 CALLL DATGEN ;custom code (c4 - c7) MOV L,#CUS2 CALLL DATGEN ;complement of custom code (c0 - c3) MOV L,#CUS3 CALLL DATGEN ;complement of custom code (c4 - c7) MOV L,#DAT0 CALLL DATGEN ;data code (d0 - d3) MOV L,#DAT1_0 CALLL DATGEN ;data code (d4 - d7) MOV L,#DAT2 CALLL DATGEN ;complement of data code (d0 - d3) MOV L,#DAT3_0 CALLL DATGEN ;complement of data code (d4 - d7) MOV H,#4 ;delay time MOV H,#4 MOV H,#4 CALLL D_56 CALLL D108 MOV H,#0 MOV L,#DEBOCNT MOV @HL+,#6 JPL MAIN J_SIGCON JPL SIGCON ORG 0600H JPL RESET SIGCON MOV L,#0 SETB P2.(L) CALLL D9 ;high for delay 9 msec MOV L,#0 CLRB P2.(L) CALLL D2_25 ;low for delay 2.25 msec MOV L,#0CH CALLL D2_25F CALLL D_56 ;high for delay 0.56 msec

518NECTX 518NECTX.src 11/27/1997 2 of 2 pp. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 MOV H,#0 MOV L,#DEBOCNT MOV @HL+,#0FH ;;; CALL D96_19 ;delay time 96.19 msec JPL MAIN ;;;; delay time of signal output(p2.0) D108 MOV L,#0AH MOV H,#4 DECS L JP .-2 MOV L,#0BH JP D_A D96_19 MOV L,#0FH CALL D_A D9 MOV L,#0CH JP D_A D4_5 MOV L,#7 DECS L JP .-1 MOV L,#05H D_A CLR A ADDS A,#0FH MOV H,#4 DECS A JP .-2 DECS L JP .-6 RET ORG 0700H JPL RESET ;; subroutine for signal out of custom code & data code DATGEN MOV A,L CALL D_56 ;high for delay .56 msec CPBT @HL.0 ;if @hl.0 is high, low for 2.25 msec CALL D2_25 ;otherwise, low for 1.125 msec CALL D1_125 CALL D_56 ;high for delay .56 msec CPBT @HL.1 ;if @hl.1 is high, low for 2.25 msec CALL D2_25 ;otherwise, low for 1.125 msec CALL D1_125 CALL D_56 ;high for delay .56 msec CPBT @HL.2 ;if @hl.2 is high, low for 2.25 msec CALL D2_25 ;otherwise, low for 1.125 msec CALL D1_125 CALL D_56 ;high for delay .56 msec CPBT @HL.3 ;if @hl.3 is high, low for 2.25 msec 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 CALL D2_25 ;otherwise, low for 1.125 msec CALL D1_125F RET D_56 MOV L,#0 SETB P2.(L) MOV L,#0CH MOV H,#4 DECS L JP .-2 MOV H,#4 MOV L,#0 CLRB P2.(L) MOV L,A RET D2_25 MOV L,#0FH D2_25F MOV H,#4 DECS L JP .-2 MOV H,#4 MOV H,#4 D1_125 MOV L,#09H JP .+2 D1_125F MOV L,#08H MOV H,#4 DECS L JP .-2 MOV H,#4 RET org 0800h jpl reset org 0900h jpl reset org 0a00h jpl reset org 0b00h jpl reset org 0c00h jpl reset org 0d00h jpl reset org 0e00h jpl reset

518_ 16TX 518_16TX.src 11/27/1997 1 of 3 pp. ;; for NEC FORMAT ;;If a key is pressed, a frame is transmitted. Continuous pulse is ;;transmitted until key off. The frame interval is 108 msec. ;;A frame consists of leader code, custom code (16-bit), data code ;;(16-bit). ;;--- reader code consists of high for 9msec and low for 4.5msec. ;;--- data code consists of data code (8-bit), the complement of ;; data code (8-bit). ;;--- custom code consists of according to diodes(= 16-bit) between ;; p2.6 and input port and between p2.1 and input port. ;;* transmission waveform * ;;<- leader ->|<- custom code ->|<- data code ->|<- data code ->| ;; 16-bit 8-bit 8-bit ;;| | | | ;; 2.25msec ;; __ __ ;; | | | | ;; data'0' | | data'1' | | ;; Carrier frequency: fosc/12 = 38 kHz, 1/3 duty ORG 0500H JPL RESET TX MOV L,#0DH CLRB P2.(L) MOV H,#4 MOV L,#CUS2 IN A,P0 NOTI A DECS A MOVZ @HL,A ;product custom code (c8 - c11) MOV L,#0DH SETB P2.(L) MOV L,#CUS3 IN A,P0 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 NOTI A DECS A MOVZ @HL,A ;product custom code (c12 - c15) ;;;before code tx., programmer must select carrier frequency. ; MOV L,#9 ; CLRB P2.(L) ; MOV L,#0AH ; CLRB P2.(L) MOV H,#0 MOV L,#CONKEY CPNZ @HL JP J_SIGCON SIGOUT MOV @HL+,#1 MOV L,#0 SETB P2.(L) CALLL D9 ;high for delay 9 msec MOV L,#0 CLRB P2.(L) CALLL D4_5 ;low for delay 4.5 msec MOV L,#CUS0 CALLL DATGEN ;custom code (c0 - c3) MOV L,#CUS1 CALLL DATGEN ;custom code (c4 - c7) MOV L,#CUS2 CALLL DATGEN ;custom code (c8 -c11) MOV L,#CUS3 CALLL DATGEN ;custom code (c12-c15) MOV L,#DAT0 CALLL DATGEN ;data code (d0 - d3) MOV L,#DAT1_0 CALLL DATGEN ;data code (d4 - d7) MOV L,#DAT2 CALLL DATGEN ;the complement of DAT0 MOV L,#DAT3_0 CALLL DATGEN ;the complement of DAT1_0 MOV H,#4 ;delay time MOV H,#4 MOV H,#4 CALLL D_56 ;high for .56 msec JPL D108 J_SIGCON JPL SIGCON ORG 0600H JPL RESET

518_ 16TX 518 _16TX.src 11/27/1997 2 of 3 pp. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 D108 MOV L,#7 DECS L JP .-1 MOV L,#4 CA LL D_A MOV H,#0 MOV L,#DEBOCNT MOV @HL+,#5 LOWCHEK MOV H,#4 MOV L,#CUS0 ;custom code (c0 - c3) CALLL LOWDLY MOV L,#CUS1 ;custom code (c4 - c7) CALLL LOWDLY MOV L,#CUS2 ;custom code (c8 -c11) CALLL LOWDLY MOV L,#CUS3 ;custom code (c12-c15) CALLL LOWDLY JPL MAIN SIGCON MOV L,#0 SETB P2.(L) CALLL D9 ;high for delay 9 msec MOV L,#0 CLRB P2.(L) CALLL D2_25 ;low for delay 2.25 msec MOV L,#0CH CALLL D2_25F CALLL D_56 ;high for delay 0.56 msec MOV H,#0 MOV L,#DEBOCNT MOV @HL+,#0FH ;;; CALL D96_19 ;delay time 96.19 msec JPL MAIN ;;;; delay time of signal output(p2.0) D96_19 MOV L,#0CH MOV H,#4 DECS L JP .-2 MOV L,#0EH CALL D_A D9 MOV L,#0CH JP D_A 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 D4_5 MOV L,#7 DECS L JP .-1 MOV L,#05H D_A CLR A ADDS A,#0FH MOV H,#4 DECS A JP .-2 DECS L JP .-6 RET ORG 0700H JPL RESET ;; subroutine for signal out of custom code & data code DATGEN MOV A,L CALL D_56 ;high for .56 msec CPBT @HL.0 ;if @hl.0 is high, low for 2.25 msec. CALL D2_25 ;otherwise low for 1.125 msec. CALL D1_125 CALL D_56 ;high for .56 msec CPBT @HL.1 ;if @hl.1 is high, low for 2.25 msec. CALL D2_25 ;otherwise low for 1.125 msec. CALL D1_125 CALL D_56 ;high for .56 msec CPBT @HL.2 ;if @hl.2 is high, low for 2.25 msec. CALL D2_25 ;otherwise low for 1.125 msec. CALL D1_125 CALL D_56 ;high for .56 msec CPBT @HL.3 ;if @hl.3 is high, low for 2.25 msec. CALL D2_25 ;otherwise low for 1.125 msec. CALL D1_125F RET D_56 MOV L,#0 SETB P2.(L) MOV L,#0CH MOV H,#4 DECS L JP .-2 MOV H,#4 MOV L,#0 CLRB P2.(L) MOV L,A RET D2_25D MOV L, #0FH JP .+4 D2_25 MOV L,#0FH D2_25F MOV H,#4 MOV H,#4

518_ 16TX 518_16TX.src 11/27/1997 3 of 3 pp. 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 MOV H,#4 DECS L JP .-2 D1_125 MOV L,#09H JP .+2 D1_125F MO V L,#08H MOV H,#4 DECS L JP .-2 MOV H,#4 RET LOWDLY MOV A,L CPBT @HL.3 ;if @hl.3 is low, add delay 1.125 msec JP LOW_2 CALL D2_25D LOW_2 MOV L,A CPBT @HL.2 ;if @hl.2 is low, add delay 1.125 msec JP LOW_1 CALL D2_25D LOW_1 MOV L,A CPBT @HL.1 ;if @hl.1 is low, add delay 1.125 msec JP LOW_0 CALL D2_25D LOW_0 MOV L,A CPBT @HL.0 ;if @hl.0 is low, add delay 1.125 msec JP LOW_R CALL D2_25D LOW_R RET org 0800h jpl reset org 0900h jpl reset org 0a00h jpl reset org 0b00h jpl reset org 0c00h jpl reset org 0d00h jpl reset org 0e00h jpl reset