KS16112

KS16112 SAMSUNG | Alldatasheet

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KS16112/4 9600/14400 bps FAX MODEM - 1 - INTRODUCTION The KS16112 and KS16114 are synchronous, half - duplex modems capable of speeds up to 9600 bps ( KS16112 ) or up to 14400 bps ( KS16114 ). 68 - PLCC - SQ These modems satisfy the requirements specified in ITU-T re - commendations V.17 ( KS16114 ), V.29, V.27 ter, V.21 Channel 2 and T.4, and meet the binary signaling requirements of T.30. These products are intended to be used in Group 3 facsimile machines or fax processing boards and can operate at 14400 ( KS16114 ), 12000 ( KS16114 ), 9600, 7200, 4800, 2400 or 300 bps depending on the selected configuration. These devices also feature V.17 short train ( KS16114 ) and V.27 ter short train and three programmable tone detectors as well as a pro - grammable DTMF receiver. Additionally, HDLC framing ( according to T.30 ) at 14400 ( KS16114 ), 12000 ( KS16114 ), 9600, 7200, 4800, 2400 or 300 bps is also featured. Device Package Operating Temperature 68-PLCC-SQ 68-PLCC-SQ KS16112 KS16114 0 ~ +70 °C

ORDERING INFORMATION

FEATURES

• Group 3 facsimile transmission / reception according to : - ITU-T V.17 short and long train ( KS16114 )
• Half - duplex operation
• Receiver dynamic range : 0 dBm to - 43 dBm
• Programmable transmit level : 0 dBm to - 15 dBm
• Programmable dual tone generation
• Programmable tone detection
• Programmable interface memory interrupt
• Programmable turn on and turn off thresholds
• Automatic T/ 2 adaptive equalizer
• HDLC capability at all speeds
• Diagnostic capability allowing telephone line quality monitoring
• ITU-T V.24 compatible interface
• TTL and CMOS compatible
• Low power consumption, KS16112 : 400mW typical, KS16114 : 550mW typical
• Programmable compromise filter for high speed RX modes These modem devices can operate over the public switched telephone network ( PSTN ) with the addition of the appropriate data access arrangement ( DAA ). KS16112/4

KS16112/4 9600/14400 bps FAX MODEM - 2 - Host I/F Dual - port RAM TXAO RXAI Eye Pattern I/F V.24 I/F Timing Chain CTS RLSD RTS DCLK TXDI RXDO CS READ WRITE EN85 IRQ SEPWCLK SEPCLK SEPXO SEPYO BLOCK DIAGRAM Digital Signal Processor Analog Front End

KS16112/4 9600/14400 bps FAX MODEM - 3 - PIN CONFIGURATION 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

60 PORI

READ - Ø2 CS WRITE - R/W IRQ KS16112 / 4

KS16112/4 9600/14400 bps FAX MODEM - 4 - PIN DESCRIPTION Pin No. Symbol Type Description RS4 RS3 RS2 RS1 RS0 CS READ - Ø2 WRITE -R/W I I/O I I I

• Register select bus These lines are used to address interface memory registers within the modem. When CS is active, the modem decodes RS0 through RS4 to address one of its 32 internal interface memory registers. RS4 is the most significant bit. In a typical design, RS0 - RS4 are connected to A0 - A4 address lines of the host microprocessor.
• Data bus These bi-directional data bus lines provide parallel data transfer between the modem and the host microprocessor. D7 is the most significant bit. The direction of the D0 - D7 data bus is controlled by the READ - Ø2 and WRITE - R/W signals. When not being written into or read from, D0 - D7 assume the high impedance state.
• Chip select The modem is selected and decodes RS0 - RS4 when CS becomes active at which time data transfer between the modem and the host can take place over the parallel data bus. Typically, CS is driven by address decode logic.
• Read enable ( bus mode ) or phase2 ( 6500 bus mode ) If 8085 bus mode is selected ( EN85 is connected to ground ), this signal acts as the READ input. If 6500 bus mode is selected ( EN85 is pulled - up to +5V ), this signal acts as the Phase 2 clock input.
• Write enable ( bus mode ) or R/W ( 6500 bus mode ) If 8085 bus mode is selected ( EN85 is connected to ground ), this signal acts as the WRITE input. If 6500 bus mode is selected ( EN85 is pulled - up to +5V ), this signal acts as the R/W strobe.

KS16112/4 9600/14400 bps FAX MODEM - 5 -

• Transmit data input TXDI is the modem’s transmit data serial input. When configured for serial data mode ( PDME bit is reset ) the modem accepts data bits for transmission via this input. When transmitting data, the modem reads the TXDI pin on the rising edge of DCLK. When the modem is con - figured for parallel data mode ( PDME bit is set ), the TXDI pin is ig - nored and transmit data is accepted by the modem via the DBFR register. Pin No. Symbol Type Description
• Interrupt request The modem can use IRQ to interrupt the host microprocessor program execution. IRQ can be enabled in the modem interface memory to be asserted in response to a specified change of conditions in the modem status. IRQ is an open drain output and must be connected to an external pull up resistor of suitable value ( typically, a 5.6 KΩ , 1/4 watt, 5% resistor is adequate ). IRQ TXDI RXDO RTS O I O I
• Receive data output RXDO is the modem receive data output. Received data is output to the DTE via the RXDO pin in both serial and parallel data modes ( PDME bit set or reset ). When receiving data, the modem outputs a data bit on the falling edge of DCLK. The center of RXDO bits coincides with the rising edge of DCLK, thus, the DTE should read RXDO on the rising edge of DCLK.
• Request to send When the RTS input is forced low, the transmitter starts transmitting the modem training sequence according to the selected configuration. Once the training sequence has been transmitted ( signaled by the CTS pin and CTSB bit becoming active ), data present at either the TXDI input pin in serial mode ( PDME bit is reset ) or written into the DBFR register in parallel mode ( PDME bit is set ) is modulated and transmitted. The RTS input pin is logically ORed with the RTSB bit in the interface memory. PIN DESCRIPTION ( Continued )

KS16112/4 9600/14400 bps FAX MODEM - 6 - O O O I O

• Clear to send CTS is used to indicate of that the training sequence transmission has been completed and the modem is ready to transmit any data present at either the TXDI input pin in serial mode ( PDME bit is reset ) or in DBFR in parallel mode ( PDME bit is set ). CTS RLSD DCLK XTALI XTALO
• Received line signal detector RLSD becomes active at the end of the reception of the training sequence indicating the beginning of data reception. If no training is detected but the received energy level is above the RLSD off - to - on threshold, RLSD will become active.
• Data clock DCLK acts as received data clock or transmit data clock depending on the state of the modem ( transmit or receive mode ). The frequency of the clock corresponds to the data rate of the selected modem configuration and is accurate to ± 0.01%. In receive mode the RXDO pin is clocked out by the modem on the rising edge of DCLK. In transmit mode, TXDI is clocked in by the modem on the falling edge of DCLK. Pin No. Symbol Type Description
• Oscillator In / Out An external 24.00014 MHz ( KS16112 ) or 38.00053 MHz ( KS16114 ) crystal and two capacitors are connected to the XTALI and XTALO. Alternatively, an external crystal oscillator of the appropriate frequency can be connected to the XTALI input leaving XTALO unconnected. In order to minimize electromagnetic emissions and ensure proper oscillator start up and operation, the crystal and the capacitors should be placed as close as possible to the XTALI and XTALO pins. Further, the circuit board traces connecting the crystal and capacitors to XTALI and XTALO should be as short as possible. The use of circuit board vias should be avoided in the crystal oscillator circuitry and circuit board traces should be routed using curved turns. PIN DESCRIPTION ( Continued )

KS16112/4 9600/14400 bps FAX MODEM - 7 - Pin No. Symbol Type Description

• Power On reset In/Out PORI and PORO must be connected together forming a bi-directional modem reset signal ( POR ). When power is first applied to the modem, POR is held low for approximately 350 ms. The modem is then ready for normal operation 15 ms after the low to high transition of POR. PORI PORO VDD VCC VBB GNDA1 GNDA2 EN85
• + 5V Digital voltage supply This pin must be connected to +5V ± 5% supply. The + 5V Digital power supply voltage ripple should not exceed 100mVP - P.
• + 5V Analog voltage supply This pin must be connected to +5V ± 5% supply. The + 5V Analog power supply voltage ripple should not exceed 100mVP - P.
• - 5V Analog voltage supply This pin must be connected to -5V ± 5% supply. The - 5V Analog power supply voltage ripple should not exceed 100mVP - P.
• Digital ground These pin must be connected to digital ground.
• Analog ground These pin must be connected to analog ground.
• Enable 8085 bus mode When EN85 is connected to ground, 8085 bus mode is selected and the modem can interface directly to an 8085 compatible microprocessor bus using READ and WRITE. When EN85 is pulled - up to + 5V, 6500 bus mode is selected and the modem can interface directly to a 6500 compatible micro - processor using Ø2 and R/W. I O Power Power Power I PIN DESCRIPTION ( Continued ) GNDD1 GNDD2 GND GND

KS16112/4 9600/14400 bps FAX MODEM - 8 - Pin No. Symbol Type Description

• Cable 1 and Cable 2 equalizer select These two inputs are used to select equalization for the following cable lengths : CABL2 CABL1 CABL2 XCLKO YCLKO SEPXO SEPYO SEPCLK SEPWCLK
• XCLK output This output pin is a 12MHz ( KS16112 ) or 19MHz ( KS16114 ) square wave output derived from XTALI.
• YCLK output This output pin is a 6MHz ( KS16112 ) or 9.5MHz ( KS16114 ) square ware output derived from XTALI.
• Serial eye pattern bit data These two outputs provide two serial bit streams containing eye pattern display data for the oscilloscope X and Y axis. The data words are 9 bits long with the sign bit shifted out first and the bits clocked by the rising edge of SEPCLK.
• Serial eye pattern bit clock SEPCLK is a 230.4KHz clock used to shift the eye pattern data into the serial-to-parallel converters. SEPXO and SEPYO are shifted out by the modem on the rising edge of SEPCLK. CABLE TYPE LENGTH Gain (dB) CABL1 LENGTH 700Hz 1500Hz 2000Hz 3000Hz low low high high low high low high 0.0Km 1.8Km 3.6Km 7.2Km 0.00 -0.99 -2.39 -3.93 0.00 -0.20 -0.65 -1.22 0.00 0.15 0.87 1.90 0.00 1.43 3.06 4.58
• Serial eye pattern word clock SEPWCLK ( 9600Hz ) provides SEPXO and SEPYO 9 - bit word timing and its rising edge is used for copying the output of the serial to parallel converters into the X and Y digital-to-analog converters. I O O O O O O PIN DESCRIPTION ( Continued )

KS16112/4 9600/14400 bps FAX MODEM - 9 - ABSOLUTE MAXIMUM RATINGS ( Ta = 25 °C ) Pin No. Symbol Type Description

• Transmitter analog output The TXAO can supply a maximum of 3.03 VPK into a load resistance of 10KΩ ( minimum ). An external analog smoothing filter with transfer function 28735.63 / ( S + 11547.34 ) is required.
• Receiver analog input The input impedance of RXAI is greater them 1MΩ . An external analog anti - aliasing filter with transfer function 21551.72 / ( S + 11547.43 ) is required between the line interface and the modem RXAI input. The maximum input signal level into the anti-aliasing filter should not exceed 0 dBm. TXAO RXAI AUXAI O I I
• Auxiliary analog input The transmitter output ( TXAO ) can be accessed by user equipment through AUXAI. Since this is a sampled input any signals with frequency components higher than 4800Hz ( half of the sampling rate ) will cause aliasing errors. The input impedance of AUXAI is 1MΩ and the gain to TXAO is 0 dB ± 1dB. Characteristic Positive Digital Supply Voltage Positive Analog Supply Voltage Negative Analog Supply Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD VCC VBB PD TOPR TSTG Value 5V ± 5% 5V ± 5% -5V ± 5% 400 (KS16112) 550 (KS16114) 0 ~ 70 -55 ~ 150 Unit V V V mW PIN DESCRIPTION ( Continued )

KS16112/4 9600/14400 bps FAX MODEM - 10 -

ELECTRICAL CHARACTERISTICS

( Ta = 25 °C , VCC = 5V, VBB = -5V, Unless otherwise specified ) VIH VIL IIH IIL II( LKG ) IO( LKG ) VOH VOL IOH( CLK ) IOL( CLK ) CL CD Input Voltage Input Current Input Leakage Current Output Leakage Current Output Voltage V.24 Signals, V.24 Signals, Clock Output Current Capacitive Load Capacitive Drive Characteristic Symbol Test Condition Min Typ Max Unit VCC = 5.25V, Vin = 5.25V VCC = 5.25V VCC = 5.25V Vin = 0 to 5V Vin = 0.4 to VCC - 1 ILOAD = -100 µA ILOAD = -40 µA ILOAD = 1.6mA ILOAD = 0.8mA ILOAD = 0.4mA -0.3 3.5 2.4 100 0.8 -400 ± 2.5 ± 10 0.4 0.4 0.4 -0.1 100 VCC VCC V V µA µA µA µA V V mA µA PF PF 2.0 0.8VCC TTL PORI TTL TTL w / p - up TTL 3 - S TTL 3 - S PORO IRQ D0 - D7 PORO TTL and PORI TTL w / p - up TTL 3-S and Open Drain CLOCK PORITTL and

KS16112/4 9600/14400 bps FAX MODEM - 11 - MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ( Ta = 25 °C ) Characteristics Symbol Min Typ Max Unit CS Set up time RSI Set up time Data access time Data hold time Control hold time Write data set up time Write data hold time Phase 2 Clock high tCS tRS tDA tDHR tHC tWDS tDHW t2CH 100 nSec nSec nSec nSec nSec nSec nSec nSec

Figure 1. MICROPROCESSOR BUS INTERFACE TIMING DIAGRAM

1 Configurations, Signaling Rates and Data Rates

The various modem configurations with the corresponding modulation specifications are shown in Table 7. Table 7. Modulation Specifications

2 Transmitted Data Spectrum

At 2400 baud a square root of 25% raised cosine filter is used. At 1600 baud a square root of 50% raised cosine filter is used. At 1200 baud a square root of 90% raised cosine filter is used.

3 Turn - On Sequence

The transmitter turn - on sequence times are shown in Table 8. Table 8. Turn - On Sequence Duration

4 Turn - Off Sequence

followed by 20 ms of silence. and 7 ms of data and scrambled ones ( 1600 baud ) and 20 ms of silence.

• for V.21 ch 2 the transmitter turns-off within 7 ms after RTS goes inactive.

5 Data Encoding

6 Equalization

48 - tap T/2 transversal equalizer.

KS16112/4 9600/14400 bps FAX MODEM - 15 -

7 Tone Generation

The modem is capable of generating single or dual tones in the frequency range of 400 to 3200 Hz with a resolution of 0.15 Hz and accuracy of 0.01%. This feature allows the modem to function as a DTMF dialer.

8 Transmit Level

The transmitter output level is programmable from 0 dBm to - 15.0 dBm and is accurate to ± 1.0 dB.

9 Scrambler / Descrambler

The scrambler and descrambler are in accordance with ITU-T recommendations V.17 ( KS16114 ), V.29 and V.27ter.

10 Receiver Dynamic Range

The receiver can operate with line signal levels from 0 dBm to - 43 dBm at the receiver analog input ( RXAI ). The RLSD threshold levels are programmable as follows: Turn on: - 10 dBm to - 47 dBm ( default = - 43 dBm ) Turn off: - 10 dBm to - 52 dBm ( default = - 48 dBm )

11 Receiver Timing

The receiver can track a timing error of up to ± 0.035%

12 Carrier Recovery

The receiver can track a frequency offset up to ± 10 Hz.

13 Received Data

The serial received data output ( RXDO ) is clamped to a constant mark whenever RLSD is off.

14 Tone Detection

The modem features three tone detectors two of which operate in all non - high speed modes. The third tone detector operates in all receive modes. The three tone detectors can be cascaded to form a single 12th order filter. The filter coefficients of each tone detector are programmable by the host.

KS16112/4 9600/14400 bps FAX MODEM - 16 -

15 Power Requirements

The power requirements are as follows: + 5V ± 5% @ 60 mA ( typical : KS16112 ), @95mA ( typical : KS16114 ) - 5V ± 5% @ 14 mA ( typical )

16 Environmental Requirements

The environmental requirements are as follows: Temperature operating range from 0 - 70 °C.

17 Differences Between the Samsung KS16112/4 and Rockwell R96DFX/R144EFX

The KS16112/4 are pin - to- pin and software compatible modem devices that can be used to replace the Rockwell R96DFX /R144EFX modem. Functionally, the Samsung and Rockwell modems are nearly identical. However, there are a few differences between the two that the user should be aware of.

• The KS16112/4 feature an improved equalizer with 48 taps thus allowing better performance without a compromise equalizer. The KS16112/4 work over 7 Japanese links as well as over all EIA lines. The equalizer is always T/2 fractionally spaced and there is no provision for a T-spaced equalizer. Also when reading the equalizer taps from the DSP it should be noted that the direction of the time axis is different from Rockwell’s ( i.e the smallest address corresponds to the oldest data ). The tap coefficients between the Samsung KS16112/4 and Rockwell R96DFX / R144EFX are not interchangeable ( i.e taps stored from the R96DFX / R144EFX cannot be loaded into the KS16112/4 ).
• Instantaneous energy detector ( IED ) does not include state 2.
• During DTMF detection the DEDT bit is the same as the DTDT bit.
• The following DTMF parameters are not available: Minimum cycle time Minimum dropout time ( is always set to 5 ms ) Frequency deviation, low group Frequency deviation, high group Maximum energy hit time
• Programmable Interrupt does not include dual port interface memory locations 0 and 10.

KS16112/4 9600/14400 bps FAX MODEM - 17 -

• The signal level should be derived from the AGC gain word since the average energy is not implemented.
• The carrier detect turn - on and carrier detect turn - off thresholds function differently from the R96DFX / R144EFX . The carrier thresholds should be changed by changing MAXG ( MAXG is R96DFX /R144EFX compatible ).
• Samsung modem does not support squelch extend.
• The host should complete high speed configuration change prior to 30mS before receiving data.
• The host should not write data into DBFR during RTS to CTS in HDLC mode
• Maximum speed energy ( CR1=1 , ADDR1=1E ) works differently from Rockwell. Maximum speech energy sets the ratio between the total energy and the DTMF tone energy before valid DTMF digits are detected. The default is 4000 hex which is 3dB.
• 1800pF capacitor must be connected between AGCIN and GNDA1 OR GNDA2.
• Data speed detection of V.33 is not supported ( KS16114 ).
• 1700 HZ carrier for V.17 is not supported ( KS16114 ).
• Samsung modem provides a host programmable receiver compromise filter.
• G2 mode is not supported ( KS16114 ).
• Voice mode is not supported ( KS16114 ).
• IRQ2 is not supported ( KS16114 ).

KS16112/4 9600/14400 bps FAX MODEM - 18 -

• DSP memory bits that are not supported KS16112 does not support Rockwell R96DFX DSP memory
• 07:2 SQEXT
• 07:1 T2 KS16114 does not support R144EFX DSP memory
• 1E:4 B2I2E
• 1E:1 B1I2E
• 1D:7 SHPR
• 1D:6 ASPEED
• 1D:5 PR
• 1D:4 PRDET
• 15:6 AREX2
• 15:4 DR2
• 0E:7 FSKFLS
• 0D:3 G2FGC
• 08:2 FSK7E
• 08:1 G2CTK
• 07:2 SQEXT
• 05:6 AREX1
• 05:5 PIDR
• 05:4 DR1

KS16112/4 9600/14400 bps FAX MODEM - 19 - SOFTWARE INTERFACE Communication between the modem and the host microprocessor is accomplished by means of a dual port interface memory. The dual port memory consists of 32 8-bit registers that both the host microprocessor and the modem have access to. The host can control modem operation by writing control bits or parameter values to the dual port interface memory. The host can also monitor modem operation by reading status bits or data values ( such as the eye quality monitor value or EQM ) from the interface memory. The dual port read and write procedures are described in section 3. 1. Dual - Port Memory Map The memory map for the 32 - byte interface memory registers is shown in Table 1. These registers can be accessed during any host read or write cycle. In order to operate on a single bit or a group of bits, the host microprocessor must first read the desired register, set or reset the desired bits and then write the modified and unmodified bits back into the interface memory register.

2 Modem Interface Memory Bit Definitions

This section describes in detail the function of all bits, fields and registers in the interface memory. All bit, field or register names are listed in alphanumeric order. For each bit, field or register the convention R :B ( D ) is used to indicate the location of the term and its power up default value. R is the register number ( hexadecimal ), B is the bit or group of bits within that register and D is the associated power up default value. A default value of ‘- ’ indicates that the bit state depends on modem operating conditions, thus, these bits do not truly have a power up default value. In the transmit mode when ABORT is set the modem will finish sending the current DBFR byte after which it will send continuous ones ( if ZCLMP is reset ) or continuous zeros ( if ZCLMP is set ). When ABORT is reset the modem will not send continuous ones or zeros. Address 1ADR 1 ABORT 09 : 3 ( - )Abort/Idle 04 : 0 - 7 ( 17h ) ADR1 is used to specify the modem’s internal RAM address to be read or written ( data RAM if CRAM1=0 or coefficient RAM if CRAM1=1) during a RAM access cycle. The 16-bit real and imaginary data to be written into RAM or read out of RAM is placed in XDM1, XDL1 and YDM1, YDL1. The address value in ADR1 also determines the data to be output by the modem via the eye pattern interface ( SEPXO and SEPYO ). At power-up, ADR1 defaults to 17h which corresponds to the rotated equalizer output ( normal eye pattern output ). In the receive mode when ABORT is set the modem has received a minimum of seven consecutive ones. ABORT must then be reset by the host.

Table 1. Dual Port Interface Memory Map written into RAM or read out of RAM is placed in XDM2, XDL2 and YDM2, YDL2.

Table 1. Dual Port Interface Memory Map ( Continued )

KS16112/4 9600/14400 bps FAX MODEM - 22 - When AHEOF is set while in HDLC transmit mode, the modem automatically generates and transmits the FCS ( frame check sequence ) and at least one closing flag upon detecting an underrun condition in the transmission of data. AHEOF is valid only when the modem is configured for HDLC mode ( HDLCE is set ). Buffer Data Available No.2 1E : 0 ( - ) When BDA1 has been set by the modem, the modem has either written or read buffer data to/from the YDL1 register. The setting of the BDA1 bit can be setup to cause an IRQ interrupt ( see INTE1 and INTA1 bit descriptions ). When the host microprocessor reads or writes the YDL1 register, the modem automatically resets the BDA1 bit. BDA 1 Buffer Data Available No.1 1E : 3 ( - ) When BDA2 has been set by the modem and the modem is in parallel data mode ( PDME is set ), with or without HDLC enabled, transmit data has been read from DBFR by the modem ( transmit mode ) or received data has been written by the modem into DBFR ( receive mode ). When the modem is in serial mode ( PDME is reset ), the modem sets BDA2 whenever data has been read from or written into YDL2. The setting of the BDA2 bit can be setup to cause an IRQ interrupt ( see INTE2 and INTA2 bit descrip - tions ). When the host microprocessor reads or writes the YDL2/DBFR register, the modem automatically resets the BDA2 bit. BRT 1 Baud Rate 1 05 : 2 ( 1 ) When BRT1 is set, RAM access for ADR1 takes place at the baud rate ( the baud rate depends on the se - lected configuration ), otherwise it occurs at the sample rate ( 9600Hz ). This bit must be zero in FSK, Tone or DTMF receive modes. BRT 2 Baud Rate 2 15 : 2 ( 0 ) When BRT2 is set RAM access for ADR2 takes place at the baud rate ( the baud rate depends on the se - lected configuration ). Otherwise it occurs at the sample rate ( 9600Hz ). This bit must be zero in FSK, Tone or DTMF receive modes. CASC Select 12th Order Filter Cascade 08 : 4 ( 0 ) When CASC is set, the tone detectors are cascaded to form one 12th order filter ( TD3 is the output status bit for the 12th order filter cascade ). When CASC is reset, the three tone detectors operate as three parallel independent 4th order filters. The 12th order mode is only valid in the FSK , FSK and DTMF receiver modes when RTS is off and RTSB is reset. AHEOF Automatic HDLC End of Frame 15 : 5 ( 0 ) BDA 2

KS16112/4 9600/14400 bps FAX MODEM - 23 - CONFIG Configuration 06 : 0 - 7 ( 14th ) The contents of CONFIG determine the modem operating configuration. The following table lists all valid 8 - bit configuration codes and the corresponding selected configuration.: At power up, the modem defaults to V.29 9,600 bps. After changing the contents of CONFIG, the host must set the CSET bit to instruct the modem to carry out the configuration change. When the configu - ration change has been completed, the modem resets the CSET bit. CRAM1 Coefficient RAM 1 Select 05 : 0 ( 1 ) When CRAM1 is set, ADR1 addresses coefficient RAM and when CRAM1 is reset, ADR1 addresses data RAM. This bit must be set according to the desired RAM address. CRAM2 Coefficient RAM 2 Select 15 : 0 ( 1 ) V.17 14,400 bps TCM ( KS16114 ) V.17 12,000 bps TCM ( KS16114 ) V.17 9,600 bps TCM ( KS16114 ) V.17 7,200 bps TCM ( KS16114 ) V.29 9,600 bps V.29 7,200 bps V.29 4,800 bps V.27 ter 4,800 bps V.27 ter 2,400 bps Transmit : V.21 Ch 2 300 bps (FSK) Receive : V.21 Ch 2 300 bps (FSK) and tone detector Transmit : V.21 Ch 2 300 bps (FSK) Receive : V.21 Ch 2 300 bps (FSK), tone detector and DTMF receiver Transmit : Dual tone Receive : Tone detector CONFIG (Hexadecimal) Selected Modem Configuration

KS16112/4 9600/14400 bps FAX MODEM - 24 - DATM Data Mode 0C : 5 ( - ) Status bit DATM is set by the modem to indicate that the transmitter or receiver is in data mode. Data mode implies that the modem is in a state where user data may be transmitted or received. DBFR Transmit/Receive Data Buffer 10 : 0 - 7 ( - ) When the modem is configured in parallel data mode ( PDME is set ), the host microprocessor reads parallel received data from DBFR or writes parallel transmit data into DBFR. DBFR data is transmitted bit 0 first. Transmission and reception of data is synchronized by polling the BDA2 status bit or by IRQ interrupts ( see INTE2 and INTA2 bit descriptions ). When CRCE and EOHF are both set, the received frame is erroneous. If CRCE is reset and EOHF is set the received frame is correct. CRCE becomes valid immediately before EOHF is set. The host informs the modem to implement a configuration change by setting the CSET bit. The host sets the CSET bit after writing a configuration code into the CONFIG bits ( register 6:0-7 ). The CSET bit is reset by the modem after the configuration change has been completed. CRCE Cyclic Redundancy Check Error 09 : 1 ( - ) CSET Configuration Setup 1F : 0 ( 0 ) CTSB Clear to Send Bit 0F : 1 ( - ) When CTSB is set the modem has completed the training sequence transmission and any data present at TXDI ( if PDME is reset ) or DBFR ( if PDME is set ) will be transmitted. CTSB parallels the operation of the CTS output pin. When CRAM2 is set, ADR2 addresses coefficient RAM and when CRAM2 is reset, ADR2 addresses data RAM. This bit must be set according to the desired RAM address.

KS16112/4 9600/14400 bps FAX MODEM - 25 - Status bit DCDB is set by the modem when the receiver has completed the reception of a training sequence or has detected energy above the RLSD turn on threshold and is receiving data. DCDB parallels the oper - ation of the RLSD output pin. DCDB Data Carrier Detect Bit 0F : 0 ( - ) Status bit DEDT is the same as DTDT. DEDT DTMF Early Detection 1C : 7 ( - ) Status bit DOTS is set by the modem when the on - time requirements for a DTMF signal is satisfied. The modem resets this bit either after DSDET is set or if the received signal fails to meet the DTMF signal requirements. DOTS DTMF On Time Satisfied 1C : 5 ( - ) Status bit DSDET is set by the modem when a DTMF signal that satisfies all the detection requirements has been detected. After detection, this bit must be reset by the host. DSDET DTMF Signal Detected 1C : 4 ( - ) DTDT Dual Tone Detected 1C : 6 ( - ) When a signal that meets all DTMF requirements except on - time, off - time and cycle time is detected, the modem sets status bit DTDT. The encoded DTMF value is available at this time in DTMFW. This bit is reset by the modem either after DSDET is set or if the signal fails to meet the DTMF detection require - ments. DTMFW DTMF Output Word 1C : 0 - 3 ( - ) The encoded DTMF output is written into this field when a DTMF tone is being received ( status bit DSDET is set by the modem ). The DTMF output codes are:

KS16112/4 9600/14400 bps FAX MODEM - 26 - A B C D A B C D E F DTMF Symbol Encoded Output DTMF Symbol Encoded Output EOHF End of HDLC Frame 09 : 2 ( - ) In the transmit mode when AHEOF is reset, the EOHF bit is used to instruct the modem to send the 16 - bit FCS and ending flag of a HDLC frame. The host must set the EOHF bit after the modem has read the last byte of the frame from DBFR. The modem will then reset EOHF after generating and sending the end of frame sequence. If AHEOF is set, the modem will set EOHF and output the 16 bits FCS and at least one ending flag when an underrun condition occurs. EOHF is reset when the frame closing flag is sent. EPTE Echo Protector Tone Enable 07 : 3 ( 1 ) In the receive mode, the modem sets EOHF when it has received a frame ending flag and updates CRCE. The host must reset EOHF before the ending flag of the following frame. When this bit is set, the modem transmits unmodulated carrier for 187.5 ms followed by 20 ms of silence prior to sending the training sequence. With EPTE reset the modem will immediately send the training sequence except in the V.29 configuration. In the V.29 configuration the modem precedes the training sequence with 20 ms of silence. When FLG is set while in the HDLC transmitter mode, the modem transmits a flag sequence. In the HDLC receive mode, the modem sets the FLG bit when it receives a flag sequence. FLG FLAG Mode 09 : 0 ( 0 )

KS16112/4 9600/14400 bps FAX MODEM - 27 - When control bit HDLCE is set, the modem performs HDLC framing. To activate or deactivate HDLC mode the host must set or reset HDLCE and PDME and then set the CSET bit to instruct the modem to carry out the configuration change. FRZEQ Freeze Equalizer 09 : 5 ( 0 ) When control bit FRZEQ is set, equalizer tap updating is disabled freezing the equalizer tap coefficients at their current value. IED is a fast responding energy detection status indicator. The received signal level is indicated by the following codes: HDLCE HDLC Enable 07 : 0 ( 0 ) IED Instantaneous Energy Detector 0F : 6 - 7( 0 ) No Energy Present Invalid Invalid Energy Above Turn - On Threshold IED Energy Level If BDA 1 is set by the modem when INTE 1 is set, the modem asserts IRQ and sets status bit INTA 1 to indicate that BDA 1 caused the interrupt. The host resets INTA 1 by reading or writing register 0. If BDA 2 is set by the modem when INTE 2 is set, the modem asserts IRQ and sets status bit INTA 2 to indicate that BDA 2 caused the interrupt. The host resets INTA 2 by reading or writing register 10h. The contents of INTADR specify the register number on which the programmable interrupt will take effect on. The host register addresses and the corresponding INTADR 5 - bit codes are provided in the table. INTA 1 Interrupt Active 1 1E : 6 ( - ) INTA 2 Interrupt Active 2 1E : 7 ( - ) INTADR Interrupt Address OA : 0 - 4 ( 0 )

KS16112/4 9600/14400 bps FAX MODEM - 28 - The modem will assert IRQ and set INTA 1 when BDA 1 is set by the modem if control bit INTE 1 is set ( interrupt enabled ). If INTE 1 is reset ( interrupt disabled ) IRQ and INTA 1 are unaffected by BDA 1. The modem will assert IRQ and set INTA 2 when BDA 2 is set by the modem if control bit INTE 2 is set ( interrupt enabled ). If INTE 2 is reset ( interrupt disabled ) IRQ and INTA 2 are unaffected by BDA 2. INTE 1 INTE 2 Interrupt Enable 1 Interrupt Enable 2 1E : 2 ( 0 ) 1E : 5 ( 0 ) Host Register ( Hex ) INTADR ( Hex ) Host Register ( Hex ) INTADR ( Hex ) When control bit INTML is set when programmable interrupts are enabled ( PINTE is set ), the modem will logically AND the contents of the interface memory register specified by INTADR with the contents of INTMSK. Thus, the IRQ condition will be met if all the bits in the specified register masked by INTMSK are set. When control bit INTML is reset when programmable interrupts are enabled ( PINTE is set ), the modem will logically OR the contents of the interface memory register specified by INTADR with the contents of INTMSK. Thus, the IRQ condition will be met if any the bits in the specified register masked by INTMSK are set. Note that ITRIG places additional interrupt triggering requirements on the programmable interrupt which must also be met in order for IRQ to be asserted by the modem. INTML Interrupt Mask Logic (AND / OR Logic) 0A : 5 ( 0 )

KS16112/4 9600/14400 bps FAX MODEM - 29 - A bit mask function is performed by this byte on the register specified by INTADR for the programmable interrupt. The INTML bit determines whether a logical AND or a logical OR masking operation is performed with the contents of the register specified by INTADR and the contents of INTMSK. Note that ITRIG places additional triggering requirements which must also be met in order for IRQ to be asserted by the modem. Additionally, programmable interrupts must be enabled ( PINTE set ) and PIRQ must have been reset by the host prior to the occurrence of the interrupt condition in order for IRQ to be asserted by the modem. ITRIG places triggering polarity requirements on the programmable interrupt which must be met in order for the modem to assert IRQ. The four possible ITRIG settings and their corresponding function are described below. Interrupt Triggering 0A : 6 -7 ( 0 )ITRIG INTMSK Interrupt Bit Mask 0B : 0 - 7 ( 0 ) During HDLC parallel mode data transmission ( HDLCE and PDME are set ) the host microprocessor must load DBFR with consecutive transmit data bytes within eight bit times of each other. If more than eight bit times elapse between transmit data bytes being written into DBFR, an underrun condition is detected by the modem and is indicated by the ORUR and ABORT bits being set. When an underrun condition occurs, the modem clamps the transmit data to ones. The clamping of transmit data will continue until the host microprocessor resets the ABORT bit. When the host microprocessor resets the ABORT bit, the modem will complete the transmission of the current group of eight binary ones and will then proceed to start the transmission of the next frame if BA2 has been reset ( the host reading or writing DBFR causes BA2 to reset ). Otherwise, the modem will transmit continuous HDLC flags. In the receive mode, the modem indicates an overrun condition by setting ORUR. An overrun condition occurs when the host microprocessor fails to read the received data in DBFR before it is overwritten by the next received byte. The host must reset the ORUR bit before the next received data overrun condition can be indicated by the modem setting ORUR. ORUR Overrun / Underrun 09 : 7 ( - ) ITRIG (Bin) Description Continuous interrupt when interrupt condition Interrupt when interrupt condition from false to true Interrupt when interrupt condition from true to false Interrupt when any change in interrupt condition

KS16112/4 9600/14400 bps FAX MODEM - 30 - In the high speed transmit mode ( all data configurations except FSK ), the modem sets P1S to indicate that the P1 sequence is being transmitted. The P1 sequence is also referred to as the echo protector tone and consists of 187.5 ms of unmodulated carrier followed by 20 ms of silence. In the receive mode the P1S bit has no significance. In the high speed transmit mode ( all data configurations except FSK ), the modem sets P2S to indicate that the P2 sequence is being transmitted. In the receive mode, the modem sets P2S to indicate that the modem has detected an incoming P2 sequence and is in the process of searching for the P2 to PN transition. When the PDME control bit is set, the modem is configured for parallel data mode. During parallel data mode transmission, the modem accepts transmit data from DBFR ( 10 : 0 - 7 ) rather than the TXDI serial input. During the receive mode the modem simultaneously outputs the received data to DBFR ( 10 : 0 - 7 ) and the RXDO serial output. HDLC framing is performed only in parallel data mode. When PDME is reset, the modem is in serial data mode and the modem accepts transmit data via the TXDI serial input and issues received data via the RXDO serial output. PDME Parallel Data Mode Enable 07 : 5 ( 0 ) P2S P2 Sequence 0C : 2 ( - ) P1S P1 Sequence 0C : 1 ( - ) The ORUR function is disabled if the AHEOF control bit is set. The ORUR bit is valid only while the modem is configured for HDLC mode ( HDLCE is set ). When programmable interrupts are enabled ( PINTE is set ). PINTA is set by the modem when the interrupt condition specified by INTMSK, INTADR, ITRIG, and INTML is true. The modem asserts IRQ if PIRQ has been previously reset by the host. PINTA is automatically reset when the host resets PIRQ. PINTE Programmable Interrupt Enable 1F : 4 ( 0 ) PINTA Programmable Interrupt Active When PINTE is set and the interrupt condition as specified by INTMSK, INTADR, ITRIG, and INTML is true, the modem asserts IRQ if control bit PIRQ has been previously reset by the host. Bits INTMSK, INTADR, ITRIG, INTML, and PIRQ have no effect on IRQ and PINTA when programmable interrupts are disabled ( PINTE is reset ). 1F : 7 ( - ) PIRQ Programmable Interrupt Request 1F : 3 ( - ) When PINTE is set and the interrupt condition is true as specified by INTMSK, INTADR, ITRIG, and INTML, the modem asserts IRQ if control bit PIRQ has been previously reset by the host, PIRQ is set by the modem when the programmable interrupt condition is true. The host must reset PIRQ after servicing the interrupt. The modem will not assert IRQ when an interrupt condition is met unless PIRQ is reset.

KS16112/4 9600/14400 bps FAX MODEM - 31 - PNDT PN Detected 0D : 6 ( - ) The modem receiver sets the PNDT status bit to indicate that it has detected the beginning of the PN segment of the training sequence. PNDT remains set during the reception of the PN segment and is reset at the end of the PN segment. PNS PN Sequence 0C : 3 ( - ) In the high speed transmit mode, the modem sets the PNS bit to indicate that the PN segment of the training sequence is being transmitted. In the high speed receive mode, the PNS bit is set by the modem while it is receiving the PN segment of the training sequence. The modem sets the PNSX status bit when it has successfully trained at the end of the PN segment of the high speed training sequence. If training fails, PNSX is reset. PNSX is valid after the DCDB bit is set. RA1 RAM Access 1 05 : 7 ( 1 ) PNSX PN Success 08 : 3 ( - ) When the host sets the RA1 control bit, the modem accesses the RAM addressed by ADR1 and the CRAM1 bit and performs a read or write as determined by the WT1 control bit. SAVEQ Save Equalizer RTSB Request to Send Bit 09 : 6 ( 0 ) 07 : 7 ( 0 ) REC Receive State 0D : 7 ( - ) RA2 RAM Access 2 15 : 7 ( 1 ) When the host sets the RA2 control bit, the modem accesses the RAM addressed by ADR2 and the CRAM2 bit and performs a read or write as determined by the WT2 control bit. The modem sets the REC status bit to indicate that the modem is in the receive state. When the REC bit is reset, the modem is in the transmit state. The modem begins a transmit sequence when the RTSB bit is set or the RTS input pin is driven low. The modem will continue to transmit as long as RTSB is set or RTS is low. When the SAVEQ bit is set by the host, the taps of the adaptive equalizer are not cleared when entering the training state, thus saving the equalizer tap coefficients obtained during the previous training.

KS16112/4 9600/14400 bps FAX MODEM - 32 - In the high speed transmit mode, the modem sets the SCR1S status bit to indicate that the modem is sending the scrambled ones sequence. In the high speed receive mode, the modem sets the SCR1S status bit to indicate that the modem is receiving the scrambled ones sequence. In the receive mode, SCR1S is reset to indicate that the modem is not receiving the scrambled ones sequence. The KS16114 supports V.17 and V.27ter short train while the KS16112 supports V.27ter short train. To utilize these short train modes, the receiver must first be trained using a long training sequence at the same speed as the subsequent short training sequence. After the long training sequence has been success - fully received, the host may configure the modem for short train mode by setting SHRTN. At this time the host must also set the SAVEQ bit to preserve the equalizer tap coefficients obtained during the long train. SHTRN Short Train 07 : 4 ( 0 ) SCR1S Scrambled Ones Sequence 0C : 4 ( - ) SILIDL Silence / Idle 0C : 0 ( - ) When in the high speed transmit mode, the modem sets the SILIDL status bit to indicate that the modem is transmitting silence. In the high speed receive mode, the modem sets the SILIDL status bit to indicate that the modem is in the idle state waiting for energy to be received. The TD1 bit is set when the modem detects energy above the turn - on threshold of tone detector No 1. As the default, tone detector No.1 is programmed to detect energy in the 2100 Hz ± 25 Hz frequency range. All three tone detectors ( TD1, TD2 and TD3 ) have host programmable filter coefficients. Tone detector No. 1 is operational in FSK, FSK and DTMF receiver and Tone configurations and whenever the modem is not transmitting. The TD2 bit is set when the modem detects energy above the turn on threshold of tone detector No 2. As the default, tone detector No. 2 is programmed to detect energy in the 1100 Hz ± 30 Hz frequency range. All three tone detectors ( TD1, TD2 and TD3 ) have host programmable filter coefficients. Tone detector No. 2 is operational in FSK, FSK and DTMF receiver and Tone configurations and whenever the modem is not transmitting. TD2 Tone Detector No.2 08 : 6 ( - ) TD1 Tone Detector No.1 08 : 5 ( - )

KS16112/4 9600/14400 bps FAX MODEM - 33 - The TD3 bit is set when the modem detects energy above the turn on threshold of tone detector No. 3. As the default, tone detector No. 3 is programmed to detect energy in the 462Hz ± 14Hz frequency range. All three tone detectors ( TD1, TD2 and TD3 ) have host programmable filter coefficients. Tone detector No. 3 is operational in FSK, FSK and DTMF receiver and Tone configurations and whenever the modem is not transmitting. TD3 serves as the output status indicator when the CASC bit is set forming a 12th order filter using TD1, TD2, and TD3 ( see CASC bit description ). When the host sets the TRND bit while in the receive mode, the modem will not recognize the training sequence and will not enter the training state. In the transmit mode, the modem will not transmit the training sequence when the RTS input is active or the RTSB bit is set. When the WT1 control bit is set, the modem reads 16 bits of data from the Y RAM Data 1 registers ( YDM 1, YDL 1 ) and writes it into its internal RAM as addressed by ADR1 and CRAM1 immediately following the host setting the RA1 control bit. If the MSB of ADR1 is a zero, the data is copied into X RAM, if the MSB of ADR1 is a one, the data is copied into Y RAM. When WT1 is reset the modem reads real and imaginary 16 - bit data from its internal RAM locations as addressed by ADR1 and CRAM1 and writes it into the X RAM Data 1 registers ( XDM1, XDL1 ) and Y RAM Data 1 registers ( YDM1, YDL1 ) immediately after the host sets the RA1 control bit. WT1 RAM Write 1 05 : 1 ( 0 ) TRND Training Disable 07 : 6( 0 ) TD3 Tone Detector No.3 08 : 7( - ) When the WT2 control bit is set, the modem reads 16 bits of data from the Y RAM Data 2 registers ( YDM1, YDL1 ) and writes it into its internal RAM as addressed by ADR2 and CRAM2 immediately following the host setting the RA2 control bit. If the MSB of ADR2 is a zero, the data is copied into X RAM. If the MSB of ADR2 is a one, the data is copied into Y RAM. When WT2 is reset, the modem reads real and imaginary 16bits data from its internal RAM locations as addressed by ADR2 and CRAM2 and writes it into the X RAM Data 1 registers ( XDM1, XDL1 ) and Y RAM Data 1 registers ( YDM1, YDL1 ) immediately after the host sets the RA2 control bit. WT2 RAM Write 2 15 : 1 ( 0 ) XDL1 contains the least significant byte of the 16-bit X RAM1 Data word used while reading XRAM locations. XDL2 X RAM Data 2 LSB 12 : 0 - 7 ( - ) XDL1 X RAM Data 1 LSB 02 : 0 - 7 ( - )

KS16112/4 9600/14400 bps FAX MODEM - 34 - XDL2 contains the least significant byte of the 16-bit X RAM2 Data word used while reading XRAM locations. XDM1 contains the most significant byte of the 16-bit X RAM1 Data word used while reading XRAM locations. XDM2 contains the most significant byte of the 16-bit X RAM2 Data word used while reading XRAM locations. YDAL1 contains the least significant byte of the 16-bit Y RAM1 Data word used while reading YRAM locations. YDAL2 contains the least significant byte of the 16-bit Y RAM2 Data word used while reading YRAM locations. YDM1 contains the most significant byte of the 16-bit Y RAM1 Data word used while reading YRAM locations. YDM2 contains the most significant byte of the 16-bit Y RAM2 Data word used while reading YRAM locations. When both ABORT and ZCLMP are set the modem will transmit continuous zeros. When ZCLMP is reset and ABORT is set the modem will send continuous ones. With ABORT reset ZCLMP is disabled. The internal DSP random access memory ( RAM ) is organized into two parts : real ( XRAM ) and imaginary ( YRAM ). The host processor has access to both the XRAM and the YRAM.

3 Digital Signal Processor ( DSP ) RAM Access

ZCLMP Zero Clamp 09 : 4 ( 0 ) YDM2 Y RAM Data 2 MSB YDM1 Y RAM Data 1 MSB 11 : 0 - 7 ( - ) 01 : 0 - 7 ( - ) YDL2 Y RAM Data 2 LSB 10 : 0 - 7 ( - ) YDL1 Y RAM Data 1 LSB 00 : 0 - 7 ( - ) XDM2 X RAM Data 2 MSB 13 : 0 - 7 ( - ) X RAM Data 1 MSBXDM1 03 : 0 - 7 ( - )

The dual port interface memory is used during host-to-DSP RAM or DSP RAM-to-host data transfers. corresponding BRTX bit setting. The DSP RAM access functions, codes and registers are listed in Table 2. Table 2. Modem DSP RAM Access Codes

3.1 Interface Memory Access of DSP RAM

3.2 Host DSP Read and Write Procedures

transmit/receive data buffer ( DBFR ). Table 2. Modem DSP RAM Access Codes ( Continued )

27 RX BPF compromise filter 0 1 6A-89

KS16112/4 9600/14400 bps FAX MODEM - 37 -

3.3 DSP RAM Read Procedure

The RAM read procedure is a 32 - bit transfer from the DSP RAM to the interface memory. Both the X and Y RAM data is transferred simultaneously. The sequence of events is as follows:

• Before accessing the DSP interface memory, first reset RA1 and/or RA2, then reset BDA1 and/or BDA2 by reading YDL1 and/or YDL2.
• Reset WT1 and/or WT2 to instruct the modem that a RAM read operation will take place when RA1 and/or RA2 is set.
• Load the RAM address into ADR1 and/or ADR2 and then set CRAMX and BRTX to desired values, where x = 1 or 2
• Set RA1 and/or RA2 to instruct the modem to perform the RAM read operation.
• BDA1 and/or BDA2 will be set when the modem has completed the transfer from the DSP RAM to the interface memory RAM data registers.
• When the modem sets BDA1 and/or BDA2, IRQ is also asserted if INTE1 and/or INTE2 is set. INTA1 and/or INTA2 is set to inform the host that BDA1 and/or BDA2 was the source of the interrupt.
• In the order listed, read XDM1, XDL1, YDM1, and YDL1; and/or XDM2, XDL2, YDM2, and YDL2. Reading YDL1 resets INTA1 and BDA1 and/or reading YDL2 resets INTA2 and BDA2 causing IRQ to go inactive if no other interrupts are pending. The DSP RAM write procedure is a 16 - bit transfer from the interface memory to the DSP RAM. Thus X RAM data or Y RAM data can be transferred each baud or sample time. The sequence of events is as follows :

3.4 DSP RAM Write Procedure

• Before writing to the DSP interface memory, first reset RA1 and/or RA2 and then reset BDA1 and/or BDA2 by reading YDL1 and/or YDL2, respectively.
• Write the RAM address into ADR1 and/or ADR2 and then set CRAM1 and BRT1 and/or CRAM2 and BRT2 to the desired values.

KS16112/4 9600/14400 bps FAX MODEM - 38 -

• Set WT1 and/or WT2 to instruct the modem that a RAM write operation will take place when RA1 and/or RA2 is set.
• Write the desired data into the interface memory RAM data registers YDL1 and YDM1 and/or YDL2 and YDM2.
• Set RA1 and/or RA2 to instruct the modem to perform the RAM write operation.
• BDA1 and/or BDA2 will be set when the transfer from the interface memory RAM data registers into RAM has been completed.
• When BDA1 and/or BDA2 is set, IRQ is also asserted if INTE1 and/or INTE2 is set.
• Reset INTA1 and BDA1 and/or INTA2 and BDA2 by reading or writing to YDL1 and/or YDL2. Reading or writing YDL1 and/or YDL2 also causes IRQ to return to the inactive state if no other interrupts are pending.

4 Parallel Data Transfers

Parallel data transfers use register 10h in the interface memory ( DBFR ). The modem and the host can synchronize data transfers by observing the BDA2 bit in the interface memory. Parallel data transfers may also be performed under IRQ interrupts ( see INTE2 and INTA2 bit descriptions ).

4.1 Receiving Parallel Data

During parallel data mode ( PDME is set ), the modem writes received data to DBFR once every eight bit times. When received data is available the modem sets the BDA2 bit. The BDA2 bit is automatically reset when the host reads DBFR. When BDA2 is set the host must take action within eight bit times or the data will be lost since the modem will overwrite DBFR ( DBFR overrun condition ). During parallel data mode ( PDME is set ), the modem reads DBFR once every eight bit times. The BDA2 bit is set by the modem when DBFR has been read, thus requesting the next transmit data byte. The BDA2 bit is reset automatically when the host writes to DBFR. When BDA2 is set the modem must respond within eight bit times or the modem will retransmit the data in register DBFR ( DBFR underrun condition ). The least significant bit of register DBFR represents the oldest data and the most significant bit represents the newest data received.

4.2 Transmitting Parallel Data

The LSB ( bit 0 ) in DBFR is transmitted first in time and the MSB ( bit 7 ) is transmitted last.

KS16112/4 9600/14400 bps FAX MODEM - 39 - Start Start RAx 0 Read YDLx to to reset BDAx WTx 0 ADRx Address CRAMx 1 or 0 BRTx 1 or 0 RAx 1 BDAx = 1 ? Read YDMx and YDLx or XDMx and XDLx Read more RAM ? Yes No End End Yes No RAx 0 Read YDLx to to reset BDAx ADRx Address CRAMx 1 or 0 BRTx 1 or 0 WTx 1 YDMx MSB YDLx LSB RAx 1 Write more RAM ? No Yes BDAx = 1 ? Yes No DSP Ram read DSP RAM Write Note: x is 1 for RAM access 1 x is 2 for RAM access 2

KS16112/4 9600/14400 bps FAX MODEM - 40 - Start PDME 1 BDA2 = 1 ? Read DBFR Read more Yes No End Yes No CSET 1 CSET = 0 ?No Yes Clear BDA2 by reading DBFR Start PDME 1 CTSB = 1 ? Write to DBFR Write more Yes No End Yes No CSET 1 CSET = 0 ?No Yes RTSB 1 BDA2 = 1 ?No RTSB 0 Parallel data transmitParallel data receive

KS16112/4 9600/14400 bps FAX MODEM - 41 -

5 Programmable Interrupt Feature

This feature makes it possible for the host to select an interrupt to occur on any combination of bits within an interface memory register.

5.1 Programmable Interrupt Bits

The programmable interrupt routine is executed at the sampling rate. ( 9,600Hz ) in all configurations. When the host sets the PINTE bit and the modem sets the PINTA bit, IRQ goes active ( low ) when the interrupt condition is met. The PIRQ bit must be reset by the host after the interrupt service, since this bit will not be reset by the modem and no further interrupts will occur until PIRQ has been reset. An interrupt may occur due to a single interface memory register based on any combination of bits. The register is selected by specifying the interrupt Address in the INTADR field. The interrupt bit mask register ( INTMSK ) selects the bits to be tested in the interface memory register specified by INTADR.

5.2 Programmable Interrupt Operation Modes

There are two operating logic modes ( AND/OR ) with each having four trigger options. The triggering option is selected by the ITRIG field and the logic ( AND/OR ) is selected by INTML.

6 DSP RAM Parameter Definitions and Scaling

In the following the DSP RAM parameters are described as they appear in Table 2

• Received Signal Sample / Received Signal Sample ( FSK ) Format: 16 bits, signed two’s complement Equation: VINT ( V ) = [( A / D Sample Word ) h * ( 3.03/2 15 )] VEXT = VINT + LOG 10 -1 {( AGC Gain ( dB )) /20}
• AGC Gain Word Format: 16 bits, unsigned Equation: AGC Gain ( dB ) = 50 [ 1 - ( AGC Gain Word ) h / 215 ]

KS16112/4 9600/14400 bps FAX MODEM - 42 -

• Carrier Detect Turn - On Threshold
• Carrier Detect Turn - Off Threshold
• Receiver Sensitivity, MAXG Format : 16 bits, two’s complement, positive value Equation: Carrier Detect Turn - on Threshold = 2185 [ 10 ( TON + MG ) ] Carrier Detect Turn - off Threshold = 2185 [ 10 ( TOFF + MG ) ] Receiver Sensitivity, MAXG = 655.36 [ 50 - Gain Limit ( dB )] Where: TON is the turn - on threshold in dB/10 TOFF is the turn - off threshold in dB/10 MG = 50 [ 1 - ( MAXG )h/215] /10 MAXG is programmable, default = 0FC0h
• Tone 1 Frequency
• Tone 2 Frequency Format: 16 bits, unsigned Equation: N = 216 / 9600 * ( Frequency in Hz )
• Tone 1 Output Level
• Tone 2 Output Level Format: 16 bits. two’s complement, positive value Total power is the result of both tone 1 power and tone 2 power added together. These can be independently calculated using the equation for transmit output level ( item 10 ).

KS16112/4 9600/14400 bps FAX MODEM - 43 -

• Transmit Output Level Format: 16 bits, two’s complement, positive Equation: Transmit Output Level = 18426 [ 10 ( PO / 20 ) ] Where: Po = Output Power ( dBm ) into 600 Ω
• Equalizer Tap Coefficients Format: 16 bits, signed two’s complement, complex These numbers are complex and thus require two write operations per tap. One for the real part and one for the imaginary part.
• Rotated Equalizer Output, Eye Pattern
• Decision Points, Ideal Points Format: 16 bits, two’s complement, complex
• Error Vector Format: 16 bits, two’s complement, complex This is the difference between the received point and the nearest ideal point
• Rotation Angle Format: 16 bits, two’s complement
• Frequency Correction Format: 16 bits, two’s complement Equation: Frequency Corr. ( Hz ) = [( Frequency Corr. Word )h/2 16] * baud in Hz Equation: Rotation Angle ( degree ) = [( Rotation Angle Word )h/2 16] * 180 degrees

KS16112/4 9600/14400 bps FAX MODEM - 44 -

• Eye Quality Monitor ( EQM ) Format: 16 bits, two’s complement, positive This is the filtered squared magnitude of the error vector.
• Minimum DTMF On - Time Format: 16 bits, two’s complement, positive Range: 0 to 7FFFh
• Minimum DTMF Off - Time Format: 16 bits, two’s complements, positive Range: 0 to 7FFFh
• Negative Twist Control
• Positive Twist Control Format: 16 bits, two’s complements, Positive Range: 0 to 7FFFh These parameters control the acceptable twist ( negative or positive ) for the DTMF signals. To increase the acceptable twist ( negative or positive ) level decrease this parameters from its default value.
• Number of Additional Flags ( HDLC ) Format: 16 bits, two’s complement, positive Equation: desired number of flags - 1 This parameter specifies the number of flags between frames or at the end of the final frame in the HDLC mode.

KS16112/4 9600/14400 bps FAX MODEM - 45 -

• TD1 Tone Detector Coefficient
• TD2 Tone Detector Coefficient
• TD3 Tone Detector Coefficient Format: 16 bits, two’s complement These parameters control the frequency responses of the three tone detec - tors. See Section Tone Detection for a detailed description of the structure of the tone detectors.
• Maximum Speech Energy Format : 16 bits, two’s complement This parameter sets the ratio between the total energy ( speech energy plus DTMF energy ) and the DTMF tone energy before valid DTMF digits are detected. The default is 4000hex which is 3dB.
• RX compromise filter The receiver’s 32 tap complex FIR BPF filter can be host programmed to include a compromise filter. New filter taps can be downloaded from the host after the host has configured the modem for high speed operation.

KS16112/4 9600/14400 bps FAX MODEM - 46 - HDLC OPERATION The modem is capable of performing HDLC framing ( High Level Data Link control ). The modem uses the SDLC ( Synchronous Data Link control ) in an eight bit octet format which is a subset of HDLC.

1 HDLC Frames

Information on an HDLC link is transmitted by means of frames. The information is organized into a format specified by an international standard that enables the synchronization between the transmitter and the receiver. An HDLC frame has the following parts :

• Flags
• Address Field
• Control Field
• Information Field
• Fame Check Sequence The frame check sequence computation uses the cyclic redundancy check ( CRC ) method and implement a polynomial specified in ITU-T T.30 and X.25 as follows : X 16 + X 12 + X 5 +1 The HDLC is functional under the following transmitter and receiver modes:
• V.17 ( KS16114 )
• V.29
• V.27ter
• V.21 Ch. 2
• V.21 Ch. 2 with DTMF Receiver

1 DTMF Dialing

quency ( DTMF ) dialing. The amplitude and frequency of each tone generator are programmable by the host.

1.1 DTMF Requirements

Table 3. DTMF Frequencies

1.2 Setting DTMF Parameters

tone the desired output power while compensating for modem filter characteristics.

Table 4. DTMF Default Values

2 Tone Detection

2.1 Programmable Tone Detection

12th order filter by setting the CASC bit in the dual port interface memory. Figure 2. Tone Detector Block Diagram

the RAM access codes for all filter coefficients. Table 5. Default Tone Detector Filter Coefficients Table 6. Filter RAM Access Codes

KS16112/4 9600/14400 bps FAX MODEM - 51 -

3 Fax Transmit/Receive

Phase B, D, and E are transmitted using 300 FSK and the messages are transmitted in HDLC frames. Phase C is either transmitted in HDLC frame, if error correction is required, or without HDLC. The flowcharts on next pages illustrate how to implement facsimile transmit and receive for HDLC frames and for normal high speed message transmission. ITU-T T.30 recommendation provides procedures for facsimile transmission over the PSTN. T.30 recommendation supports two modes of transmission, low speed FSK with HDLC, and high speed data transmission for facsimile message. The high speed may or may not support HDLC which depends on implementations of ECM mode (Error Correction). The error correction mode is negotiated in phase B of facsimile establishment phase, as shown below. If both the originating fax and the answering fax modem support error correction, then the high speed message transmission must be done using the HDLC. Facsimile transmission is done in 5 phases as shown below, Phase A. Call establishment. In phase A the originating fax unit will send the CalliNG (CNG) tone to indicate it is a non-speech terminal. CNG tone is a 1100 Hz tone for a duration of .5 second on and 3 off. The answering fax will send the CallED (CED) tone. CED tone is a 2100 Hz tone for a duration of 2.6 to 4 sec. Phase B. Pre-message procedure. Phase B is for identification and selection of required facilities. In phase B the answering fax will send the DIS (Digital ID Signal) and the originating fax will send DCS (Digital Command Signal). The train check (TCF) is then transmitted by the originating fax for a duration of 1.5 second. If the answering fax receives the TCF, it will send CFR (Confirmation to Receive) and the two modem enter Phase C. Phase C. Message Transmission. In Phase C the facsimile message will be transmitted form the originating fax to the answering fax unit. Phase D. Post-message Procedure. In Phase D the transmitter of fax message will send EOM (End Of Message) and will wait for a response from the answering fax unit. The answering fax unit will in response return one of the following messages, MCF (Message Confirmation), RTP, RTN, PIP, or PIN. Phase E. Call Release. After post message signals where exchanged, the two fax units enter phase E (after last page of message was transmitted) and the originating fax will send DCN (Disconnect) to indicate the Phase E. DCN message requires no response.

Figure 3. Transmitter and Reciever Flow Charts

Figure 4. Modem Configuration

KS16112/4 9600/14400 bps FAX MODEM - 54 - stop modem disable interrupt 0 ---> INTE2 (1E:5) drop RTS 0 ---> RTSB (7:7) RETURN disable prog int 0 ---> PINTE (1F:4) infrom dsp of change 1 ---> CSET (1F:0) CSET (1F:0) ? RETURN SETUP function program PINTE to interrupt on CSET low modem IRQ = SETUP IRQ enable prog. int 1 ---> PINTE (1F:4) RETURN SETUP IRQ function disable prog. int 0 ---> PINTE (1F:4) Modem Configuration Continued

Figure 5. Transmit HDLC Frame

KS16112/4 9600/14400 bps FAX MODEM - 56 - FLG(09:0) ? stop modem FLG IRQ RETURN more frames ? YES read data from frame buffer write to TX BUFF data ---> DBFR (10:7-0) modem IRQ = HDLC TX IRQ enable int 1 ---> INTE2 (1E:5) disable prog int, 0 ---> PINTE (1F:4) NO end of one frame harden_signal switch to next frame delay 1 second send preamble enable interrupt, 1 ---> INTE2 (1E:5) RETURN modem IRQ = HDLC TX IRQ speed = 300 ? YES NO CTSB IRQ disable prog. int 0 ---> PINTE (1F:4) CTSB(F:1)

KS16112/4 9600/14400 bps FAX MODEM - 57 - dummy read to start int DBFR (10:7-0) receive with HDLC drop RTS 0 ---> RTSB (7:7) enable interrupt 1 ---> INTE2 (1E:5) enable prog int 1 ---> PINTE(1F:4) RETURN modem IRQ = HDLC RX IRQ program PINTE to interrupt on EOHF(9:2) high and ABORT (9:3) high 0 ---> EOHF (9:2) time out ? signal recognition detect high/low speed HIGH speed detected ? NO timeout error YES LOW speed ? LOW HIGH error, received low speed program PINTE to interrupt on FLG (9:0) high enable prog int 1 ---> PINTE(1F:4) modem IRQ = RX FLG IRQ HDLC RX IRQ RETURN

Figure 6. Receive HDLC Frame

Figure 7. Transmit TCF - Training Check

Figure 8. Receive TCF - Training Check

Figure 9. Transmit FAX message (NO HDLC)

Figure 10. Receive FAX message (NO HDLC)

KS16112/4 9600/14400 bps FAX MODEM - 63 - message RX IRQ BDA2(1E:3) ? write to frame buffer read from RX BUFF DBFR (10:7-0) <--- data RETURN DCDB (F:0) ? error, carrier dropped stop modem 1 frame yet ? end of one frame harden_signal NO start new frame YES

24.00014 MHz

Table 9. KS16112 Crystal Specifications

Table 10. KS16114 Fundamental Crystal Specifications

38.000530 MHz

Table 11. KS16114 Third Overtone Crystal Specifications

1. All Resistors ± 5%, ∗ 1/8W unless noted
2. All capacitors µF, ± 20%, 50V unless noted

15 VDD

Figure 11. Complete Modem Circuit and Eye Pattern Generator

KS16112/4 9600/14400 bps FAX MODEM - 68 - Package Dimension 25 15 ± 0.12 24.23 ± 0.10 #1 #68 24.23 ± 0.10 25 15 ± 0.12 23.37 ± 0.50 +0.20 4.32 -0.10 3.76 ± 0.12 +0.10 0.20 -0.05 +0.07 0.46 -0.12 +0.10 0.71 -0.05 1.27 0.1MAX

KS16112/4 9600/14400 bps FAX MODEM - 69 - Samsung Preliminary Fax Modem designer’s guide Date: July, 1996 Revision: 1.0