KS0715 SAMSUNG | Alldatasheet
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33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD
January .2000 Ver. 4 .0 Prepared by : Jae-Su, Ko Ko1942@samsung.co.kr Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD KS0715
KS0715 Specification Revision History Version Content Date 1.0 CAP3P → C3+, CAP2P → C2+, CAP1P → C1+ CAP3M → C3-, CAP2M → C2-, CAP1M → C1- Oscillator frequency F OSC ( k Hz) = → 19 (Min.): 22.5 ( Typ.): 26 (Max.) 2.0 Temperature coefficien t Absolute maximu m ratings Dynamic current consumption IDD1: 40 µA (Max.) IDD2: 75 µA ( Typ.), 100 µA (Max.) 3.0 Oscillator frequency (internal) Oscillator frequency (external) 3.1 Apr.1999
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD CO NTENTS
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD INTRODUCTION The KS0715 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 33 common and 1 00 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8- bit parallel display data and stores in an on-chip display data RAM of 65 x 1 32 bits. It provides a highly-flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
− 33 common outputs / 1 00 segment outputs On-chip Display Data RAM − Capacity: 65 x 1 32 = 8 ,58 0 bits − Bit data "1": a dot of display is illuminated . − Bit data "0": a dot of display is not illuminated . Multi-chip O peration ( M aster, S lave) A vailable Applicable Duty Ratios D uty ratio Applicable LCD bias Maximum display area 1/33 1/5 or 1/6 33 × 100 Microprocessor Interface − 8-bit parallel bi-directional interface with 6800-series or 8080-series − Serial interface (only write operation) available Various Instruction S etting On-chip Low Power Analog Circuit − On-chip oscillator circuit − Voltage converter (x2 , x3 and x4) − Voltage regulator (temperature coefficient: -0.05%/ °C , -0. 2 %/ °C) − On-chip electronic contrast control function ( 32 steps) − Voltage follow er (LCD b ias: 1/5 or 1/6) Operating Voltage Range − Supply voltage (V DD ): 2.4 to 3 .6 V − LCD driving voltage (V LCD = V0 - V SS ): 4.0 to 1 5 .0 V Low Power Consumption − 100 µΑ Typ. (V DD = 3V, x 4 boosting, V0 = 8 V, internal power supply ON and display OFF) − 10 µΑ Max. ( during power save [standby] mode) Wide O perating T emperature R ange − Ta = -40 °C to +85 °C Package Type − Gold bumped chip or TCP
Product c ode TEMPS p in Temp. c oefficient Package Chip t hickness KS0715UM-L0CC 670 µm KS0715UM-L4CC (V SS c onnected) -0.05%/ °C 470 µm KS0715UM-H0CC 670 µm KS0715UM-H4CC (V DD c onnected) -0.2%/ °C COG 470 µm KS0715TB-XX-L0TF 670 µm KS0715TB-XX-L4TF (V SS c onnected) -0.05%/ °C 470 µm KS0715TB-XX-H0TF 670 µm KS0715TB-XX-H4TF (V DD c onnected) -0.2%/ °C TCP 470 µm * XX: TCP ordering number
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD BLOCK DIAGRAM MS CL M FRS DISP V DD V SS VR TE MPS VOUT C1- C1+ C2- C2+ C3 - C 3+ V / C CIRCUIT V / R CIRCUIT V / F CIRCUIT
34 COMMON
MPU INTERFACE (PARALLEL & SERIAL) INSTRUCTION DECODERBUS HOLDER COLUMN ADDRESS CIRCUIT LINE ADDRESS CIRCUIT PAGE ADDRESS CIRCUIT DISPLAY DATA RAM
65 X 1 32 = 8 ,58 0 Bits
DB6(SCLK) DB7(SID) MI RESETB PS RW_WR E_RD RS CS2 CS1B COMS COM31 COM0 COMS SEG99 SEG98 SEG66 SEG65 SEG64 SEG1 SEG0 OSCILLATOR I/O BUFFER STATUS REGISTER INSTRUCTION REGISTER TESTL2 1 00 SEGMENT DRIVER CIRCUITS TESTL1 Figure 1 . Block Diagram
ððð ððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððð ððð Y 1082 09 1072 10 83234 82 1 KS071 5(TOP VIEW) (0,0) X ðððððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððððððð ðððð - - - -ðððð ðððð - - - -ðððð Figure 2 . KS0715 Chip Configuration Table 1 . KS0715 Pad Dimensions Size Item Pad No. X Y Unit Chip size - 7980 2 70 0 1 to 82 90 Pad pitch 83 to 234 7 0 1 to 82 5 6 11 4 83 to 1 07 108 50 1 08 to 2 09 50 108 Bumped pad size 2 10 to 23 4 108 50 Bumped pad height All pad 1 7 ( Typ.) µm COG Align Key Coordinate ILB Align Key Coordinate 30 µm 30 µm 30 µm (-3832, -1055) 30 µm 30 µm 30 µm (+3832, -1070) 30µm30µm30µm 60µm30µm 42 µm 108 µm 42µm108µm 42µm108µm 42 µm108 µm
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD PAD CENTER COORDINATES Table 2 . P ad Center Coordinates [Unit: µm] No. Name X Y No. Name X Y No. Name X Y
1 DUMMY -3645 -1226 51 C1+ 855 -1226 101 COM1 3830 420
2 TESTL1 -3555 -1226 52 C1+ 945 -1226 102 COM0 3830 490
3 VDD -3465 -1226 53 C1- 1035 -1226 103 COMS 3830 560
4 FRS -3375 -1226 54 C1- 1125 -1226 104 DUMMY 3830 630
5 M -3285 -1226 55 C2+ 1215 -1226 105 DUMMY 3830 700
6 CL -3195 -1226 56 C2+ 1305 -1226 106 DUMMY 3830 770
7 DISP -3105 -1226 57 C2- 1395 -1226 107 DUMMY 3830 840
8 VDD -3015 -1226 58 C2- 1485 -1226 108 DUMMY 3535 1190
9 MS -2925 -1226 59 VSS 1575 -1226 109 SEG0 3465 1190
10 VSS -2835 -1226 60 VSS 1665 -1226 110 SEG1 3395 1190
11 RESETB -2745 -1226 61 VR 1755 -1226 111 SEG2 3325 1190
12 VDD -2655 -1226 62 VR 1845 -1226 112 SEG3 3255 1190
13 PS -2565 -1226 63 V0 1935 -1226 113 SEG4 3185 1190
14 VSS -2475 -1226 64 V0 2025 -1226 114 SEG5 3115 1190
15 CS1B -2385 -1226 65 V0 2115 -1226 115 SEG6 3045 1190
16 CS2 -2295 -1226 66 V0 2205 -1226 116 SEG7 2975 1190
17 VDD -2205 -1226 67 V0 2295 -1226 117 SEG8 2905 1190
18 MI -2115 -1226 68 V0 2385 -1226 118 SEG9 2835 1190
19 VSS -2025 -1226 69 V1 2475 -1226 119 SEG10 2765 1190
20 VDD -1935 -1226 70 V1 2565 -1226 120 SEG11 2695 1190
21 RS -1845 -1226 71 V2 2655 -1226 121 SEG12 2625 1190
22 VSS -1755 -1226 72 V2 2745 -1226 122 SEG13 2555 1190
23 RW_WR -1665 -1226 73 V3 2835 -1226 123 SEG14 2485 1190
24 E_RD -1575 -1226 74 V3 2925 -1226 124 SEG15 2415 1190
25 VDD -1485 -1226 75 V4 3015 -1226 125 SEG16 2345 1190
26 VDD -1395 -1226 76 V4 3105 -1226 126 SEG17 2275 1190
27 VDD -1305 -1226 77 VSS 3195 -1226 127 SEG18 2205 1190
28 VDD -1215 -1226 78 VSS 3285 -1226 128 SEG19 2135 1190
29 VDD -1125 -1226 79 TEMPS 3375 -1226 129 SEG20 2065 1190
30 VDD -1035 -1226 80 VDD 3465 -1226 130 SEG21 1995 1190
31 DB0 -945 -1226 81 TESTL2 3555 -1226 131 SEG22 1925 1190
32 DB1 -855 -1226 82 DUMMY 3645 -1226 132 SEG23 1855 1190
33 DB2 -765 -1226 83 DUMMY 3830 -840 133 SEG24 1785 1190
34 DB3 -675 -1226 84 DUMMY 3830 -770 134 SEG25 1715 1190
35 DB4 -585 -1226 85 DUMMY 3830 -700 135 SEG26 1645 1190
36 DB5 -495 -1226 86 DUMMY 3830 -630 136 SEG27 1575 1190
37 DB6 -405 -1226 87 COM15 3830 -560 137 SEG28 1505 1190
38 DB7 -315 -1226 88 COM14 3830 -490 138 SEG29 1435 1190
39 VSS -225 -1226 89 COM13 3830 -420 139 SEG30 1365 1190
40 VSS -135 -1226 90 COM12 3830 -350 140 SEG31 1295 1190
41 VSS -45 -1226 91 COM11 3830 -280 141 SEG32 1225 1190
42 VSS 45 -1226 92 COM10 3830 -210 142 SEG33 1155 1190
43 VSS 135 -1226 93 COM9 3830 -140 143 SEG34 1085 1190
44 VSS 225 -1226 94 COM8 3830 -70 144 SEG35 1015 1190
45 VOUT 315 -1226 95 COM7 3830 0 145 SEG36 945 1190
46 VOUT 405 -1226 96 COM6 3830 70 146 SEG37 875 1190
47 C3+ 495 -1226 97 COM5 3830 140 147 SEG38 805 1190
48 C3+ 585 -1226 98 COM4 3830 210 148 SEG39 735 1190
49 C3- 675 -1226 99 COM3 3830 280 149 SEG40 665 1190
50 C3- 765 -1226 100 COM2 3830 350 150 SEG41 595 1190
Table 2 . P ad Center Coordinates (Continued) [U nit: µm] No. Name X Y No. Name X Y No. Name X Y
151 SEG42 525 1190 201 SEG92 -2975 1190
152 SEG43 455 1190 202 SEG93 -3045 1190
153 SEG44 385 1190 203 SEG94 -3115 1190
154 SEG45 315 1190 204 SEG95 -3185 1190
155 SEG46 245 1190 205 SEG96 -3255 1190
156 SEG47 175 1190 206 SEG97 -3325 1190
157 SEG48 105 1190 207 SEG98 -3395 1190
158 SEG49 35 1190 208 SEG99 -3465 1190
159 SEG50 -35 1190 209 DUMMY -3535 1190
160 SEG51 -105 1190 210 DUMMY -3830 840
161 SEG52 -175 1190 211 DUMMY -3830 770
162 SEG53 -245 1190 212 DUMMY -3830 700
163 SEG54 -315 1190 213 DUMMY -3830 630
164 SEG55 -385 1190 214 COM16 -3830 560
165 SEG56 -455 1190 215 COM17 -3830 490
166 SEG57 -525 1190 216 COM18 -3830 420
167 SEG58 -595 1190 217 COM19 -3830 350
168 SEG59 -665 1190 218 COM20 -3830 280
169 SEG60 -735 1190 219 COM21 -3830 210
170 SEG61 -805 1190 220 COM22 -3830 140
171 SEG62 -875 1190 221 COM23 -3830 70
172 SEG63 -945 1190 222 COM24 -3830 0
173 SEG64 -1015 1190 223 COM25 -3830 -70
174 SEG65 -1085 1190 224 COM26 -3830 -140
175 SEG66 -1155 1190 225 COM27 -3830 -210
176 SEG67 -1225 1190 226 COM28 -3830 -280
177 SEG68 -1295 1190 227 COM29 -3830 -350
178 SEG69 -1365 1190 228 COM30 -3830 -420
179 SEG70 -1435 1190 229 COM31 -3830 -490
180 SEG71 -1505 1190 230 COMS -3830 -560
181 SEG72 -1575 1190 231 DUMMY -3830 -630
182 SEG73 -1645 1190 232 DUMMY -3830 -700
183 SEG74 -1715 1190 233 DUMMY -3830 -770
184 SEG75 -1785 1190 234 DUMMY -3830 -840
185 SEG76 -1855 1190
186 SEG77 -1925 1190
187 SEG78 -1995 1190
188 SEG79 -2065 1190
189 SEG80 -2135 1190
190 SEG81 -2205 1190
191 SEG82 -2275 1190
192 SEG83 -2345 1190
193 SEG84 -2415 1190
194 SEG85 -2485 1190
195 SEG86 -2555 1190
196 SEG87 -2625 1190
197 SEG88 -2695 1190
198 SEG89 -2765 1190
199 SEG90 -2835 1190
200 SEG91 -2905 1190
Table 3. Power S upply Pin Description according to the state of LCD Bias. Table 4. LCD D river S upply Pin Description
Table 5. System C ontrol Pin Description The following table depends on the MS status. connected each other for sync . This pin is used together with the M pin. LCD display blanking control input/output. (multi-chip), the DISP pins must be connected each other.
Table 6. Microprocessor Interface Pin Description When RESETB is “L”, initialization is executed. should be fixed to either “H” or “L”. Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip select is non-active, DB0 to DB7 may be high impedance. − RS = "H": DB0 to DB7 are display dat a. − RS = "L": DB0 to DB7 are control data .
Table 6. Microprocessor Interface Pin Description (Continued) the falling edge of the E signal. When /RD is “L”, DB0 to DB7 are in an output status. When chip select is not active, DB0 to DB7 may be high impedance.
Table 8. LCD D river O utputs Pin Description The display data and the M signal control the output voltage of segment driver. The internal scanning data and M signal control the output voltage of common driver. The output signals of two pins are same. When not used, these pins should be left open. Table 8. Test Pin Description NOTE: DUMMY – These pins should be opened (floated).
There are CS1B and CS2 pins for C hip S election. The KS0715 can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface KS0715 has three types of interface with an MPU, which are one serial and two parallel interface. This parallel or serial interface is determined by PS pin as shown in table 9 . Table 9 . Parallel / Serial Interface Mode PS Type CS1B CS2 MI Interface mode H 6800-series MPU mode H Parallel CS1B CS2 L 8080-series MPU mode L Serial CS1B CS2 * × Serial-mode * × : Don't care Parallel Interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in table 10 . The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 11 . Table 10 . Microprocessor Selection for Parallel Interface MI CS1B CS2 RS E_RD RW_WR DB0 to DB7 MPU bus H CS1B CS2 RS E RW DB0 to DB7 6800-series L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series Table 11 . Parallel Data Transfer Common 6800-series 8080-series RS E_RD (E) RW_WR (RW) E_RD (/RD) RW_WR (/WR)
Description
H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction)
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD Serial interface (PS = "L") When the KS0715 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and control data when RS is low. Since the clock signal ( DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. CS1B CS2 SID SCLK RS DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7 Figure 3 . Serial Interface Timing Busy Flag The B usy F lag indicates whether the KS0715 is operating or not. When DB7 is “H” in r ead s tatus operation, this device is in busy status and will accept only r ead s tatus instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
The KS0715 uses bus holder and internal data bus for D ata T ransfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4 . And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5 . This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. T herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. RS /WR DB0 to DB7 N D(N) D(N+1) D(N+2) D(N+3) Internal signals MPU signals /WR BUS HOLDER COLUMN ADDRESS N N+1 N+2 N+3 N D(N) D(N+1) D(N+2) D(N+3) Figure 4 . Write Timing
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD RS /WR /RD DB0 to DB7 N MPU signals Dummy D(N) D(N+1) Internal signals /WR /RD BUS HOLDER COLUMN ADDRESS N D(N) D(N+1) D(N+2) N N+1 N+2 N+3 Figure 5 . Read Timing
DISPLAY DATA RAM (DDRAM) The Display Data RAM stores pixel data for the LCD. It is 65 -row by 1 32 -column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and the 9 th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. COM 0 - - COM 1 - - COM 2 - - COM 3 - - COM 4 - - DB0 0 0 1 - - 0 DB1 1 0 0 - - 1 DB2 0 1 1 - - 0 DB3 1 0 1 - - 0 DB4 0 0 0 - - 1 D isplay D ata RAM LCD Display Figure 6 . RAM-to-LCD Data Transfer Page Address Circuit This circuit is for providing a page address to Display Data RAM shown in figure 8 . It incorporates 4-bit P age A ddress register changed by only the “Set Page” instruction. Page A ddress 8 (DB3 is “H”, but DB2, DB1 and DB0 are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on-chip RAM. Line Address Circuit This circuit assigns DDRAM a L ine A ddress corresponding to the first line (COM 0 ) of the display. Therefore, by setting L ine A ddress repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8 . It incorporates 6 -bit line address register changed by only the in itial d isplay line instruction and 6 -bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the L ine A ddress for transferring the 1 32 -bit RAM data to the 100 d isplay data latch circuit. However, display data of icons are not scrolled because the MPU can not access L ine A ddress of icons.
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD Column Address Circuit Column A ddress circuit has an 8 -bit preset counter that provides column address to the Display Data RAM as shown in figure 8 . When set Column Address MSB / LSB instruction is issued, 8 -bit [Y 7 :Y0] is updated. And, since this address is increased by 1 each a r ead or w rite Data instruction, microprocessor can access the display data continuously. However, the counter is not incre as ed and locked if a non-existing address above 84 H. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the column address counter is independent of page address register. ADC s elect instruction makes it possible to invert the relationship between the column address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC s elect instruction. Refer to the following figure 7 . SEG output - SEG SEG SEG SEG SEG 99 - Column address [Y 7 :Y0] 00H~ 83 H Display data × 1 0 0 0 1 1 0 LCD panel display ( ADC = 0 ) Not outputted LCD panel display ( ADC = 1 ) Not outputted Figure 7 . The Relationship b etween t he Column Address a nd t he Segment Outputs Segment Control Circuit This circuit controls the display data by the display ON / OFF, r everse d isplay ON / OFF and e ntire d isplay ON / OFF instructions without changing the data in the display data RAM.
- - - - - - - - - - ---- - SEG99 SEG98 SEG97 SEG0 SEG1 SEG2 - - - - - ADC=1 ADC=0Column Address LCD Output DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 00H 08H 07H 06H 05H 04H 03H 02H 01H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 18H 17H 16H 15H 14H 13H 12H 11H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 28H 27H 26H 25H 24H 23H 22H 21H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 38H 37H 36H 35H 34H 33H 32H 31H 39H 3AH 3BH 3CH 3DH 3EH 3FH COM1 COM0 COM2 COM11 COM10 COM9 COM8 COM7 COM5 COM6 COM4 COM3 COM12 COM21 COM20 COM19 COM18 COM17 COM15 COM16 COM14 COM13 COM22 COM31 COM30 COM29 COM28 COM27 COM25 COM26 COM24 COM23 COMS Start Initial start line address = 1CH- 74 7273 71 00 - 0F 1110 12 12 11 10 -1F 00 71 72 73 -74 83 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Figure 8 . Display Data RAM Map
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD LCD DISPLAY CIRCUITS Oscillator This is completely on-chip O scillator and its frequency is nearly independent of V DD . This oscillator signal is used in the voltage converter and display timing generation circuit. * Test C ondition: Temperature: 25 °C & 85 °C, TEMPS = ” L ” , No L oad V DD vs. fosc 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 V DD [V] fosc [kHz] 1/33 Duty (25°C) 1/33 Duty (85°C) Figure 9 . V DD vs. f OSC Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock (CL) and the 1 00 -bit display data is latched by the display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and internal timing signal are shown in figure 10 . In a multi ple -chip configuration , the slave chip requires the M , CL and DISP signals from the master. T able 12 shows the M, CL, and DISP status. Table 12 . Master and Slave Timing Signal Status Operation mode Oscillator M CL DISP ON (internal clock used) Output Output Output Master OFF (external clock used) Output Input Output Slave - Input Input Input
Instruction specifies the scanning direction of the common output pins . Table 13. The Relationship between Duty Ratio and Common Output
0 COM0 to COM31
1 COM31 to COM0
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD LCD DRIVER CIRCUIT This driver circuit is configured by 34-c hannel (including 2 COMS channel) common driver and 1 00 -channel segment driver. This LCD panel driver voltage depends on the combination of display data and M signal. COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM1 0 COM1 1 COM1 2 COM1 3 COM1 4 COM 15 S E G S E G S E G S E G S E G
0 SEG 2
M V SS V SS V SS V SS V SS V SS V DD V SS Figure 10 . Segment and Common Timing
The P ower S upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low- power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For details, refers to "Instruction Description". Table 14 shows the referenced combinations in using P ower S upply circuits. Table 14 . Recommended Power Supply Combinations User setup Power control (VC VR VF) V/C circuits V/R circuits V/F circuits VOUT V0 V1 to V4 Only the internal power supply circuits are used 1 1 1 ON ON ON Open Open Open Only the voltage regulator circuits and voltage follower circuits are used 0 1 1 OFF ON ON External input Open Open Only the voltage follower circuits are used 0 0 1 OFF OFF ON Open External input Open Only the external power supply circuits are used 0 0 0 OFF OFF OFF Open External input External input
Voltage Regulator Circuits The function of the internal V oltage R egulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in f igure 14 , it is necessary to be applied internally or externally. For the Eq. 1 , we determine V0 by Ra, Rb and V EV . The Ra and Rb are connected internally or externally by INTRS pin. And V EV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 31 . V REF voltage at Ta = 25 °C is shown in t able 15-1 . Rb Ra ( 31 - α) 15 0 Table 15-1. V REF V oltage at Ta = 25 °°C TEMPS Temp. coefficient V REF [V] L -0.05% / °C 1 .9 H -0. 2 % / °C 2.1 Table 15-2. Reference Voltage Parameter ( αα) S V4 S V3 S V2 S V1 S V0 Reference voltage p arameter ( αα) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 30 1 1 1 1 1 31
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD V EV GND Ra Rb V SS VR VOUT Figure 14 . Internal V oltage R egulator C ircuit
It is necessary to connect external regulator resistor Ra between VR and V SS , and Rb between V0 and VR.
- LCD driver voltage, V0 = 8 V
- 5 -bit reference voltage register = (1, 1 , 1 , 1 , 1 )
- M aximum current flowing Ra, Rb = 1 uA
The following table shows the range of V0 depending on the above requirements. Table 16. V0 depending on Electronic Volume L evel
Table 17. T he R elationship between V1 to V4 L evel and Bias
Figure 15. When Using al l LCD Power Circuits Figure 16. When not U sing V/C C ircuit Figure 17. When Using s ome LCD Power Circuits Figure 18. When not U sing Internal
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD RESET CIRCUIT Setting RESETB to “L” or Reset instruction can initialize internal function. When RESETB becomes “L”, following procedure is occurred. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) LCD bias ratio: 1/6 R ead -m odify -write : OFF SHL select: OFF (normal) Static indicator mode: OFF D isplay start line: 0 (first) Column address: 0 Page address: 0 Reference voltage set: off Reference voltage control register: ( S V4, S V3, S V2, S V1, S V0) = (0, 0, 0, 0, 0) When RESET instruction is issued, following procedure is occurred. R ead -m odify- write : OFF Static indicator mode: OFF SHL select: 0 D isplay start line: 0 (first) Column address: 0 Page address: 0 Reference voltage set: OFF Reference voltage control register: ( S V4, S V3, S V2, S V1, S V0) = (0, 0, 0, 0, 0) While RESETB is “L” or r eset instruction is executed, no instruction except read status c ould be accepted. Reset status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
Table 18 . Instruction Table × : Don’t care Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Read display data 1 1 Read data Read data from DDRAM Write display data 1 0 Write data Write data into DDRAM Read status 0 1 BUSY ADC ON /OFF RES ETB 0 0 0 0 Read the internal status Display ON / OFF 0 0 1 0 1 0 1 1 1 D ON Turn ON / OFF LCD panel When D ON = 0: display OFF When D ON = 1: display ON Initial display line 0 0 0 1 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 Specify DDRAM line for COM0 Set r eference v oltage m ode 0 0 1 0 0 0 0 0 0 1 Set r eference v oltage m ode Set r eference v oltage r egister 0 0 1 0 0 S V4 S V3 S V2 S V1 S V0 Set r eference v oltage r egister Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address Set column address MSB 0 0 0 0 0 1 0 Y6 Y5 Y4 Set column address MSB Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB ADC select 0 0 1 0 1 0 0 0 0 ADC Select SEG output direction When ADC = 0 : normal direction (SEG0 → SEG99) When A DC = 1 : reverse direction (SEG99 → SEG0) Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV Select normal / reverse display When REV = 0 : normal display When REV = 1 : reverse display Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON Select normal/ entire display ON When EON = 0 : normal display. When EON = 1 : entire display ON LCD bias select 0 0 1 0 1 0 0 0 1 BIAS Select LCD bias Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode Reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal functions SHL select 0 0 1 1 0 0 SHL × × × Select COM output direction When SHL = 0 : normal direction (COM0 → COM31) When SHL = 1: reverse direction (COM31 → COM0) Power control 0 0 0 0 1 0 1 VC VR VF Control power circuit operation Set static indicator r egister 0 0 1 0 1 0 1 1 0 S I Set static indicator register SI = 0 (OFF), SI = 1 (ON) Power s ave - - - - - - - - - - Compound instruction of display OFF and entire display ON Test instruction 0 0 1 1 1 1 × × × × Don't use this instruction.
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD Read Display Data 8-bit data from D isplay D ata RAM specified by the column address and page address c ould be read by this instruction. As the column address is incre as ed by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 Read data Write Display Data 8-bit data of display data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is incre as ed by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 Write data Data Write Set Column Address Set Page Address Optional Status Column = Column + 1 NO YESData Write Continue ? Dummy Data Read Set Column Address Set Page Address Optional Status Column = Column + 1 NO YESData Read Continue ? Data Read Column = Column + 1 Figure 19 . Sequence for Writing Display Data Figure 20 . Sequence for Reading Display Data
Indicates the internal status of the KS0715 RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ADC ON / OFF RES ETB 0 0 0 0 Flag Description BUSY The device is busy when internal operation or reset Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. ADC Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG 99 → SEG 0 ), 1: normal direction (SEG 0 → SEG 99 ) ON / OFF Indicates display ON / OFF status 0: display ON, 1: display OFF RES ETB Indicates the initialization is in progress by RESETB signal 0: chip is active, 1: chip is being reset Display ON / OFF Turns the display ON or OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 1 D ON D ON = 1: display ON D ON = 0: display OFF Initial Display Line Sets the line address of display RAM to determine the Initial D isplay L ine . The RAM display data is displayed at the top row (COM 0 when SHL = L, COM31 when SHL = H ) of LCD panel. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD Reference Voltage Select Consists of 2-byte Instruction The 1 st instruction sets reference voltage mode , the 2 nd one updates the contents of reference vol tage register. After second instruction, reference voltage m ode is released. The 1 st Instruction : Set Reference Voltage Select M ode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 0 0 1 The 2 nd Instruction : Set Reference Voltage R egister RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 S V4 S V3 S V2 S V1 S V0 S V4 S V3 S V2 S V1 S V0 Reference voltage pa rameter ( αα) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 30 1 1 1 1 1 31 2 nd Instruction for Register Setting Setting R eference V oltage End 1 st Instruction for Mode Setting Setting R eference V oltage Start Figure 21 . Sequence for Setting the R eference V oltage
Sets the P age A ddress of display data RAM from the microprocessor into the P age A ddress register. Any RAM data bit can be accessed when its P age A ddress and column address are specified. Along with the column address, the P age A ddress defines the address of the display RAM to write or read display data. Changing the P age A ddress doesn't effect to the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 P age 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 Set Column Address Sets the C olumn A ddress of display RAM from the microprocessor into the column address register. Along with the C olumn A ddress, the C olumn A ddress defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, C olumn A ddresses are automatically incre as ed. Set Column Address MSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 Y6 Y5 Y4 Set Column Address LSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Y6 Y5 Y4 Y3 Y2 Y1 Y0 C olumn address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 0 1 0 98 1 1 0 0 0 1 1 99
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD ADC Select Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins c ould be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 0 ADC ADC = 0: normal direction (SEG 0 → SEG 99 ) ADC = 1: reverse direction (SEG 99 → SEG 0 ) Reverse Display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = “1” RAM bit data = “0” 0 (normal) LCD pixel is illuminated LCD pixel is not illuminated 1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated Reverse Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the r everse d isplay O N / O FF instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 0 EON EON = 0: normal di splay EON = 1: e ntire d isplay O N Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 1 Bias LCD biasD uty r atio B ias = 0 B ias = 1 1/33 1/ 6 1/5
This instruction stops the automatic increment of the column address by the r ead d isplay d ata instruction, but the column address is still increased by the w rite di splay d ata instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the r eset Modify- r ead instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 0 0 Reset Modify -r ead This instruction cancels the Modify-read mode, and makes the column address return to its initial value just before the s et Modify -r ead instruction is started. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 1 1 1 0 Set Modify- R ead Reset Modify- R ead Set Page Address Data P rocess NO YES Change C omplete ? Set Column Address (N) Dummy R ead Data R ead Data W rite Return C olumn A ddress (N) Figure 22 . Sequence for Cursor Display
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD Reset This instruction R esets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply , which is initialized by the RESETB pin. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 0 SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 SHL × × × × : Don ’t care SHL = 0: normal direction (COM 0 → COM 31 ) SHL = 1: r everse direction (COM 31 → COM 0 ) Power Control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON Set Static Indicator State This instruction sets the Static Indicator ON / OFF. When it is on, the static indicator operates and blinks at an interval of approximately 1second. Set Static Indicator Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 0 S I S I Status of static indicator output
0 OFF
1 ON (about 1 second blinking)
Power Save ( Compound Instruction ) If the entire display ON / OFF instruction is issued during the display OFF state, KS0715 enters the P ower S ave status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, P ower S ave is entered to one of two modes (sleep and standby mode). When s tatic indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released by the display ON & entire display OFF instruction. Release Standby Mode Power Save OFF (Compound Instruction) [Entire Display OFF] [Display ON] Release Sleep Mode Power Save OFF (Compound Instruction) [Entire Display OFF] [Static Indicator ON] [Display ON] Power Save (Compound Instruction) [Display OFF] [Entire Display ON] Static Indicator OFF Static Indicator O N Sleep Mode [Oscillator C ircuit: OFF] [LCD Power S upply C ircuit: OFF] [All COM / SEG O utputs: V SS ] [Consumption C urrent: < 2 µA] Standby Mode [Oscillator C ircuit: ON] [LCD Power S upply C ircuit: OFF] [All COM / SEG O utputs: V SS ] [Consumption C urrent: < 10 µA] Figure 23 . Power Save Routine
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD R eferential Instruction Setup Flow (1) End of Initialization Waiting for Stabilizing the LCD Power Levels User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select] Start of Initialization RESETB Pin = “ H ” Waiting for Stabilizing the Power Power O N (V DD - V SS ) Keeping the RESETB Pin = “ L ” User System Setup by External Pins User LCD P ower Setup by Internal Instructions [Voltage Converter ON] User LCD P ower Setup by Internal Instructions [Voltage Regulator ON] User LCD P ower Setup by Internal Instructions [Voltage Follower ON] Waiting for ≥ 1ms Waiting for ≥ 1ms User LCD P ower Setup by Internal Instructions [Reference Voltage R egister S et] Figure 24 . Initializing with the B uilt-in P ower S upply C ircuits
R eferential Instruction Setup Flow (2) User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select] Start of Initialization RESETB Pin = “ H ” Waiting for Stabilizing the Power Power O N (V DD - V SS ) Keeping the RESETB Pin = “ L ” User System Setup by External Pins Set Power Save Release Power Save User LCD P ower Setup by Internal Instructions [Reference Voltage R egister S et] Waiting for Stabilizing the LCD Power Levels End of Initialization Figure 25 . Initializing without the B uilt-in P ower S upply C ircuits
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD R eferential Instruction Setup Flow (3) End of Initialization Write Display ON / OFF by Instruction [Display O N / OFF] Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address] End of Data Display Turn Display ON / OFF by Instruction [Display O N / O FF ] Figure 26 . Data D isplaying
R eferential Instruction Setup Flow (4) Turn Display ON / OFF by Instruction [Display O FF ] Optional Status Power OFF (V DD -V SS ) User LCD Power Setup by Internal Instructions [Voltage Follower O FF ] User LCD Power Setup by Internal Instructions [Voltage Regulator O FF ] User LCD Power Setup by Internal Instructions [Voltage Converter O FF ] Waiting for ≥ 50ms Waiting for ≥ 1ms Waiting for ≥ 1ms Figure 27 . Power OFF
Table 19. Absolute Maximum Ratings
- VDD and VLCD are based on V SS = 0V.
- Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. (VLCD = V0 – VSS)
- If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
Table 20. DC Characteristics
KS0715 33 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD Dynamic Current Consumption (1): when the B uilt-in Power C ircuit is OFF (At O perate M ode) ( Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used Dynamic current consumption (1) IDD1 V DD = 3.0V V0 – V SS = 8.0V Display OFF, c hecker p attern - 5 20 µΑ *11 Dynamic Current Consumption (2): when t he built-in power circuit is ON (At operate mode) ( Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used V DD = 3.0V, quad boosting, V0 – V SS = 8 .0V, 1/65 duty ratio, Display OFF, c hecker pattern Normal power mode - 47 70 Dynamic current consumption (2) IDD2 V DD = 3.0V, quad boosting, V0 – V SS = 8 .0V, Display ON, checker pattern Normal power mode - 75 100 µΑ *1 2 Current Consumption during Power Save mode ( Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used Sleep mode IDDS1 During s leep - - 2.0 µA Standby mode IDD S 2 During s tandby - - 10.0 µA
Table 21 . The relationship between oscillation frequency and frame frequency Duty ratio Item f CL f M On-chip oscillator circuit is used f OSC f OSC 16 × 33 On-chip oscillator circuit is not used External input ( f CL ) f OSC 2 × 33 ( f OSC : oscillation frequency, f CL : display clock frequency, f M : LCD AC signal frequency ) [* Remark Solves] *1 . Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2 . In case of external power supply is applied. *3 . CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI , PS, TEMPS , CL, M, DISP pins . *4 . DB0 to DB7, M , FRS, DISP, CL pins . *5 . CS1B, CS2, RS, DB [7:0], E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins. *6 . Applies when the DB [7:0], M, DISP, and CL pins are in high impedance. *7 . Resistance value when ± 0.1[ mA] is applied during the ON status of the output pin SEGn or COMn. RON= ΔV / 0.1 [k Ω ] ( ΔV: voltage change when ± 0.1[ mA] is applied in the ON status.) *8 . See table 21 for the relationship between oscillation frequency and frame frequency. *9 . The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range . *10 . On-chip reference voltage source of the voltage regulator circuit to adjust V0. *11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors ( Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc.
Figure 28. Display Pattern is O FF
Figure 29. Display Pattern is O FF Figure 30. Display Pattern is Checker
Figure 31. Read / Write Characteristics (8080-series MPU)
Figure 32. Read / Write Characteristics (6800-series Microprocessor)
Figure 33. Serial Interface Characteristics
Figure 34. Reset Input Timing Figure 35. Display Control Output Timing
CONNECTIONS BETWEEN KS0715 AND LCD PANEL Single Chip Configuration (1/ 33 Duty Configurations) COM 15 COM 0 COMS COMS COM 3 1 COM 16 KS071 5 ( Bottom View) COM 15 COM 0 COMS COMS COM 3 1 COM 16 KS071 5 ( Top View) 32 × 1 00 pixels 32 × 1 00 pixels Figure 39 . SHL = 0, ADC = 1 Figure 40 . SHL = 0, ADC = 0 CO M S COM 0 CO M15 CO M16 COM 3 1 COM S KS071 5 ( Top View) 32 × 1 00 pixels COM 16 COM 3 1 COMS COMS COM 0 COM 15 KS071 5 ( Bottom View) 32 × 1 00 pixels Figure 41 . SHL = 1, ADC = 0 Figure 42 . SHL = 1, ADC = 1
Figure 45. 66COM (64COM + 2COMS) ×× 100SEG
Figure 46. TCP Pin Layout