KS0713 SAMSUNG | Alldatasheet
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65 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD
January .2000 Ver. 4.0 Prepared by : Jae-Su, Ko Ko1942@samsung.co.kr Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
65 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD KS071 3
KS071 3 Specification Revision History Version Content Date 2.0 Neglect the more past version than version 2.0 Nov. 1998 2.1 fOSC = 16kHz ( Typ.) → 22kHz ( Typ.): For removing flicker phenomenon Temperature coefficient (when TEMPS = L): -0.0%/ °C → -0.05%/ °C Nov. 1998 3.0 Modified some syntax errors Voltage regulator reference voltage [V REF ]: TBD → 2.0 Modified voltage regulator block of “Functional Description” Nov. 1998 3.1 V LCD absolute maximum rating: 15.0V → 17.0V Power consumption: 100 µA → 80 µA Oscillator frequency (2): 22 ( M in.) → 20 ( M in.), 28 ( M ax.) → 30 ( M ax.)
3.3 Modified Y-axis values of “Pad Center Coordinates”
Modified the contents of “Referential Instruction Setup Flow” 3.4 Word-processor version change Apr.1999 3.5 Modified error: pad No.113 (COMS) Y Coordinate: -1210 → -1140 (after) Oct.1999
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD CO NTENTS
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD INTRODUCTION The KS071 3 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 6 5 common s and 1 32 segment s driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-bit parallel display data and stores in an on-chip D isplay D ata RAM of 65 x 1 32 bits. It provides a high-flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no externally operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
− 6 5 common outputs / 1 32 segment outputs On-chip Display Data RAM − Capacity: 65 x 1 32 = 8 ,58 0 bits Applicable Duty Ratios D uty ratio Applicable LCD bias Maximum display area 1/ 6 5 1/ 7 or 1/ 9 6 5 × 1 32 1/49 1/6 or 1/8 49 × 132 1/33 1/5 or 1/6 33 × 132 Microprocessor Interface − 8-bit parallel bi-dire ctional interface with 6800-series or 8080-series − Serial interface (only write operation) available Function Set − Various instructions s ets − H/W, S/W r eset capable Built-in A nalog C ircuit − On-chip oscillator circuit − Voltage converter (x2 , x3, x4, x5) − Voltage regulator ( temperature coefficient: -0.05%/ °C , -0. 2 %/ °C) − Voltage follower − E lectronic contrast control function (64 steps) Operating Voltage Range − Supply voltage (V DD ): 2.4 to 3 .6 V − LCD driving voltage (V LCD = V0 - V SS ): 4.0 to 1 5 .0 V Low Power Consumption − 70 µΑ Typ. (V DD = 3V, x 4 boosting, V0 = 1 1 V, internal power supply ON) − 10 µΑ Max. ( during power save [standby] mode) Package Type − Gold bumped chip or TCP
Product c ode TEMPS pin Temp. c oefficient Package Chip t hickness KS0713UM-L0CC 670 µm KS0713UM-L4CC (V SS c onnected) -0.05%/ °C 470 µm KS0713UM-H0CC 670 µm KS0713UM-H4CC (V DD c onnected) -0.2%/ °C COG 470 µm KS0713TB-XX-L0TF 670 µm KS0713TB-XX-L4TF (V SS c onnected) -0.05%/ °C 470 µm KS0713TB-XX-H0TF 670 µm KS0713TB-XX-H4TF (V DD c onnected) -0.2%/ °C TCP 470 µm * XX: TCP ordering number
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD BLOCK DIAGRAM MS CL M FRS DISP DUTY0 DUTY1 VDD VSS HPMB VR INTRS TE MPS VOUT C1- C1+ C2- C2+ C3 - C 3+ DCDC5B BSTS V / C CIRCUIT V / R CIRCUIT V / F CIRCUIT
33 COMMON
MPU INTERFACE (PARALLEL & SERIAL) INSTRUCTION DECODERBUS HOLDER COLUMN ADDRESS CIRCUIT LINE ADDRESS CIRCUIT PAGE ADDRESS CIRCUIT DISPLAY DATA RAM
65 X 1 32 = 8 ,58 0 Bits
DB6(SCLK) DB7(SID) MI RESETB PS RW_WR E_RD RS CS2 CS1B COMS COM64 COM33 SEG132 SEG131 SEG130 SEG3 SEG2 SEG1 COM32 COM1 COMS OSCILLATOR 1 32 SEGMENT DRIVER CIRCUITS STATUS REGISTER INSTRUCTION REGISTER CLS Figure 1 . Block Diagram
ððð ððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððð ððð Y 1 482 87 1 472 88 11 132 4 11 0 1 KS071 3(TOP VIEW) (0,0) X ðððððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððððððð ððððððð ðððð - - - - ððð Figure 2 . KS071 3 Chip Configuration Table 1 . KS071 3 Pad Dimensions Size Items Pad No. X Y Unit Chip size - 10860 2 92 0 1 to 110 90 Pad pitch 11 1 to 32 4 7 0 1 to 110 5 6 11 4 11 1 to 1 47 108 50 1 48 to 2 87 50 108 Bumped pad size 2 88 to 32 4 108 50 Bumped pad height 1 to 32 4 1 7 ( Typ.) µm COG Align Key Coordinate ILB Align Key Coordinate 30 µm 30 µm 30 µm (-5065, +1302) 30 µm 30 µm 30 µm (+5065, +1317) 30µm30µm30µm 60µm 30µm 42 µm 108 µm 42µm 108µm 42µm 108µm 42 µm108 µm
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD PAD CENTER COORDINATES Table 2 . P ad Center Coordinates [Unit: µm] No. Name X Y No. Name X Y No. Name X Y
1 DUMMY -4905 -1336 51 VDD -405 -1336 101 BSTS 4095 -1336
2 DUMMY -4815 -1336 52 VDD -315 -1336 102 DCDC5B 4185 -1336
3 FRS -4725 -1336 53 VDD -225 -1336 103 VDD 4275 -1336
4 M -4635 -1336 54 VDD -135 -1336 104 HPM 4365 -1336
5 CL -4545 -1336 55 VDD -45 -1336 105 INTRS 4455 -1336
6 DISP -4455 -1336 56 VDD 45 -1336 106 VSS 4545 -1336
7 VSS -4365 -1336 57 VOUT 135 -1336 107 TEMPS 4635 -1336
8 CS1B -4275 -1336 58 VOUT 225 -1336 108 VDD 4725 -1336
9 CS2 -4185 -1336 59 VOUT 315 -1336 109 DUMMY 4815 -1336
10 VDD -4095 -1336 60 VOUT 405 -1336 110 DUMMY 4905 -1336
11 RESETB -4005 -1336 61 C3+ 495 -1336 111 DUMMY 5271 -1280
12 RS -3915 -1336 62 C3+ 585 -1336 112 DUMMY 5271 -1210
13 VSS -3825 -1336 63 C3+ 675 -1336 113 COMS 5271 -1140
14 RW_WR -3735 -1336 64 C3+ 765 -1336 114 COM1 5271 -1070
15 E_RD -3645 -1336 65 C3- 855 -1336 115 COM2 5271 -1000
16 VDD -3555 -1336 66 C3- 945 -1336 116 COM3 5271 -930
17 DB0 -3465 -1336 67 C3- 1035 -1336 117 COM4 5271 -860
18 DB1 -3375 -1336 68 C3- 1125 -1336 118 COM5 5271 -790
19 DB2 -3285 -1336 69 C1+ 1215 -1336 119 COM6 5271 -720
20 DB3 -3195 -1336 70 C1+ 1305 -1336 120 COM7 5271 -650
21 DB4 -3105 -1336 71 C1+ 1395 -1336 121 COM8 5271 -580
22 DB5 -3015 -1336 72 C1+ 1485 -1336 122 COM9 5271 -510
23 DB6 -2925 -1336 73 C1- 1575 -1336 123 COM10 5271 -440
24 DB7 -2835 -1336 74 C1- 1665 -1336 124 COM11 5271 -370
25 VSS -2745 -1336 75 C1- 1755 -1336 125 COM12 5271 -300
26 VDD -2655 -1336 76 C1- 1845 -1336 126 COM13 5271 -230
27 VDD -2565 -1336 77 C2+ 1935 -1336 127 COM14 5271 -160
28 VDD -2475 -1336 78 C2+ 2025 -1336 128 COM15 5271 -90
29 DUTY0 -2385 -1336 79 C2+ 2115 -1336 129 COM16 5271 -20
30 DUTY1 -2295 -1336 80 C2+ 2205 -1336 130 COM17 5271 50
31 VSS -2205 -1336 81 C2- 2295 -1336 131 COM18 5271 120
32 MS -2115 -1336 82 C2- 2385 -1336 132 COM19 5271 190
33 CLS -2025 -1336 83 C2- 2475 -1336 133 COM20 5271 260
34 VDD -1935 -1336 84 C2- 2565 -1336 134 COM21 5271 330
35 MI -1845 -1336 85 VSS 2655 -1336 135 COM22 5271 400
36 PS -1755 -1336 86 VSS 2745 -1336 136 COM23 5271 470
37 VSS -1665 -1336 87 VR 2835 -1336 137 COM24 5271 540
38 VSS -1575 -1336 88 VR 2925 -1336 138 COM25 5271 610
39 VSS -1485 -1336 89 V0 3015 -1336 139 COM26 5271 680
40 VSS -1395 -1336 90 V0 3105 -1336 140 COM27 5271 750
41 VSS -1305 -1336 91 V1 3195 -1336 141 COM28 5271 820
42 VSS -1215 -1336 92 V1 3285 -1336 142 COM29 5271 890
43 VSS -1125 -1336 93 V2 3375 -1336 143 COM30 5271 960
44 VSS -1035 -1336 94 V2 3465 -1336 144 COM31 5271 1030
45 VSS -945 -1336 95 V3 3555 -1336 145 COM32 5271 1100
46 VSS -855 -1336 96 V3 3645 -1336 146 DUMMY 5271 1170
47 VDD -765 -1336 97 V4 3735 -1336 147 DUMMY 5271 1240
48 VDD -675 -1336 98 V4 3825 -1336 148 DUMMY 4865 1301
49 VDD -585 -1336 99 VSS 3915 -1336 149 DUMMY 4795 1301
50 VDD -495 -1336 100 VSS 4005 -1336 150 DUMMY 4725 1301
Table 2 . P ad Center Coordinates (Continued) [Unit: µm] No. Name X Y No. Name X Y No. Name X Y
151 DUMMY 4655 1301 201 SEG50 1155 1301 251 SEG100 -2345 1301
152 SEG1 4585 1301 202 SEG51 1085 1301 252 SEG101 -2415 1301
153 SEG2 4515 1301 203 SEG52 1015 1301 253 SEG102 -2485 1301
154 SEG3 4445 1301 204 SEG53 945 1301 254 SEG103 -2555 1301
155 SEG4 4375 1301 205 SEG54 875 1301 255 SEG104 -2625 1301
156 SEG5 4305 1301 206 SEG55 805 1301 256 SEG105 -2695 1301
157 SEG6 4235 1301 207 SEG56 735 1301 257 SEG106 -2765 1301
158 SEG7 4165 1301 208 SEG57 665 1301 258 SEG107 -2835 1301
159 SEG8 4095 1301 209 SEG58 595 1301 259 SEG108 -2905 1301
160 SEG9 4025 1301 210 SEG59 525 1301 260 SEG109 -2975 1301
161 SEG10 3955 1301 211 SEG60 455 1301 261 SEG110 -3045 1301
162 SEG11 3885 1301 212 SEG61 385 1301 262 SEG111 -3115 1301
163 SEG12 3815 1301 213 SEG62 315 1301 263 SEG112 -3185 1301
164 SEG13 3745 1301 214 SEG63 245 1301 264 SEG113 -3255 1301
165 SEG14 3675 1301 215 SEG64 175 1301 265 SEG114 -3325 1301
166 SEG15 3605 1301 216 SEG65 105 1301 266 SEG115 -3395 1301
167 SEG16 3535 1301 217 SEG66 35 1301 267 SEG116 -3465 1301
168 SEG17 3465 1301 218 SEG67 -35 1301 268 SEG117 -3535 1301
169 SEG18 3395 1301 219 SEG68 -105 1301 269 SEG118 -3605 1301
170 SEG19 3325 1301 220 SEG69 -175 1301 270 SEG119 -3675 1301
171 SEG20 3255 1301 221 SEG70 -245 1301 271 SEG120 -3745 1301
172 SEG21 3185 1301 222 SEG71 -315 1301 272 SEG121 -3815 1301
173 SEG22 3115 1301 223 SEG72 -385 1301 273 SEG122 -3885 1301
174 SEG23 3045 1301 224 SEG73 -455 1301 274 SEG123 -3955 1301
175 SEG24 2975 1301 225 SEG74 -525 1301 275 SEG124 -4025 1301
176 SEG25 2905 1301 226 SEG75 -595 1301 276 SEG125 -4095 1301
177 SEG26 2835 1301 227 SEG76 -665 1301 277 SEG126 -4165 1301
178 SEG27 2765 1301 228 SEG77 -735 1301 278 SEG127 -4235 1301
179 SEG28 2695 1301 229 SEG78 -805 1301 279 SEG128 -4305 1301
180 SEG29 2625 1301 230 SEG79 -875 1301 280 SEG129 -4375 1301
181 SEG30 2555 1301 231 SEG80 -945 1301 281 SEG130 -4445 1301
182 SEG31 2485 1301 232 SEG81 -1015 1301 282 SEG131 -4515 1301
183 SEG32 2415 1301 233 SEG82 -1085 1301 283 SEG132 -4585 1301
184 SEG33 2345 1301 234 SEG83 -1155 1301 284 DUMMY -4655 1301
185 SEG34 2275 1301 235 SEG84 -1225 1301 285 DUMMY -4725 1301
186 SEG35 2205 1301 236 SEG85 -1295 1301 286 DUMMY -4795 1301
187 SEG36 2135 1301 237 SEG86 -1365 1301 287 DUMMY -4865 1301
188 SEG37 2065 1301 238 SEG87 -1435 1301 288 DUMMY -5271 1240
189 SEG38 1995 1301 239 SEG88 -1505 1301 289 DUMMY -5271 1170
190 SEG39 1925 1301 240 SEG89 -1575 1301 290 COMS -5271 1100
191 SEG40 1855 1301 241 SEG90 -1645 1301 291 COM64 -5271 1030
192 SEG41 1785 1301 242 SEG91 -1715 1301 292 COM63 -5271 960
193 SEG42 1715 1301 243 SEG92 -1785 1301 293 COM62 -5271 890
194 SEG43 1645 1301 244 SEG93 -1855 1301 294 COM61 -5271 820
195 SEG44 1575 1301 245 SEG94 -1925 1301 295 COM60 -5271 750
196 SEG45 1505 1301 246 SEG95 -1995 1301 296 COM59 -5271 680
197 SEG46 1435 1301 247 SEG96 -2065 1301 297 COM58 -5271 610
198 SEG47 1365 1301 248 SEG97 -2135 1301 298 COM57 -5271 540
199 SEG48 1295 1301 249 SEG98 -2205 1301 299 COM56 -5271 470
200 SEG49 1225 1301 250 SEG99 -2275 1301 300 COM55 -5271 400
Table 2. P ad Center Coordinates (Continued)
301 COM54 -5271 330
302 COM53 -5271 260
303 COM52 -5271 190
304 COM51 -5271 120
305 COM50 -5271 50
306 COM49 -5271 -20
307 COM48 -5271 -90
308 COM47 -5271 -160
309 COM46 -5271 -230
310 COM45 -5271 -300
311 COM44 -5271 -370
312 COM43 -5271 -440
313 COM42 -5271 -510
314 COM41 -5271 -580
315 COM40 -5271 -650
316 COM39 -5271 -720
317 COM38 -5271 -790
318 COM37 -5271 -860
319 COM36 -5271 -930
320 COM35 -5271 -1000
321 COM34 -5271 -1070
322 COM33 -5271 -1140
323 DUMMY -5271 -1210
324 DUMMY -5271 -1280
Table 3. Power Supply Pin Description according to the state of LCD Bias. Table 4. LCD Driver Supply Pin Description It is valid only when on-chip resistors are not used (INTRS = “L”) .
Table 5. System Control Pin Description The following table depends on the MS status. This pin is used together with the M pin. This pin selects the resistors for adjusting V0 voltage level. − INTRS = "H": use the internal resistors. − INTRS = "L": use the external resistors. V0 voltage is controlled with VR pin and external resistive divider. This pin is valid in master operation.
Table 5. System Control Pin Description (Continued) When BSTS pin is “ L ” , V DD must be higher than 4V in four times boosting. recommend that BSTS pin should be fixed to “ H ” .
Table 6. Microprocessor Interface Pin Description When RESETB is “L”, initialization is executed. DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”. Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip select is non-active, DB0 to DB7 may be high impedance.
Table 6. Microprocessor Interface Pin Description (Continued) the falling edge of the E signal. When /RD is “L”, DB0 to DB7 are in an output status. When chip select is not active, DB0 to DB7 may be high impedance.
Table 7. LCD Driver Outputs Pin Description The display data and the M signal control the output voltage of segment driver. The internal scanning data and M signal control the output voltage of common driver. The output signals of two pins are same. When not used, these pins should be left open. NOTE: DUMMY - These pins should be opened (floated).
There are CS1B and CS2 pins for C hip S election. The KS0713 can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface KS0713 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 8. Table 8 . Parallel / Serial Interface Mode PS Type CS1B CS2 MI Interface mode H 6800-series MPU mode H Parallel CS1B CS2 L 8080-series MPU mode L Serial CS1B CS2 * × Serial-mode * × : Don't care Parallel Interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in table 9 . The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table10 . Table 9 . Microprocessor Selection for Parallel Interface MI CS1B CS2 RS E_RD RW_WR DB0 to DB7 MPU bus H CS1B CS2 RS E RW DB0 to DB7 6800-series L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series Table 10 . Parallel Data Transfer Common 6800-series 8080-series RS E_RD (E) RW_WR (RW) E_RD (/RD) RW_WR (/WR)
Description
H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction)
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD Serial Interface (PS = "L") When the KS0713 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and control data when RS is low. Since the clock signal ( DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. CS1B CS2 SID SCLK RS DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7 Figure 3 . Serial Interface Timing Busy Flag The B usy F lag indicates whether the KS0713 is operating or not. When DB7 is “H” in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
The KS0713 uses bus holder and internal data bus for D ata T ransfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4 . And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5 . This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. T herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. RS /WR DB0 to DB7 N D(N) D(N+1) D(N+2) D(N+3) Internal signals MPU signals /WR BUS HOLDER COLUMN ADDRESS N N+1 N+2 N+3 N D(N) D(N+1) D(N+2) D(N+3) Figure 4 . Write Timing
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD RS /WR /RD DB0 to DB7 N MPU signals Dummy D(N) D(N+1) Internal signals /WR /RD BUS HOLDER COLUMN ADDRESS N D(N) D(N+1) D(N+2) N N+1 N+2 N+3 Figure 5 . Read Timing
DISPLAY DATA RAM (DDRAM) The Display Data RAM stores pixel data for the LCD. It is 65 -row by 1 32 -column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and the 9 th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in Figure 6 . The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. COM 1 - - COM 2 - - COM 3 - - COM 4 - - COM 5 - - DB0 0 0 1 - - 0 DB1 1 0 0 - - 1 DB2 0 1 1 - - 0 DB3 1 0 1 - - 0 DB4 0 0 0 - - 1 Display Data RAM LCD Display Figure 6 . RAM-to-LCD Data Transfer Page Address Circuit This circuit is for providing a P age A ddress to D isplay Data RAM shown in figure 8 . It incorporates 4-bit P age A ddress register changed by only the “Set Page” instruction. Page A ddress 8 (DB3 is “H”, but DB2, DB1 and DB0 are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on-chip RAM. Line Address Circuit This circuit assigns DDRAM a L ine A ddress corresponding to the first line (COM 1 ) of the display. Therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8 . It incorporates 6 -bit line address register changed by only the initial display line instruction and 6 -bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the L ine A ddress for transferring the 1 32 -bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU can not access L ine Ad dress of icons.
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD Column Address Circuit Column address circuit has a 8 -bit preset counter that provides column address to the Display Data RAM as shown in figure 8 . When set Column Address MSB / LSB instruction is issued, 8 -bit [Y 7 :Y0] is updated. And, since this address is increased by 1 each a Read or Write Data instruction, microprocessor can access the display data continuously. However, the counter is not incre as ed and locked if a non-existing address above 84 H. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the C olumn A ddress counter is independent of page address register. ADC s elect instruction makes it possible to invert the relationship between the C olumn A ddress and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC s elect instruction. Refer to the following figure 7 . SEG output SEG SEG SEG SEG 129 SEG 130 SEG 131 SEG 132 Display data 1 0 1 0 1 1 0 0 LCD panel display ( ADC = 0 ) LCD panel display Figure 7 . The Relationship b etween t he Column Address a nd t he Segment Outputs Segment Control Circuit This circuit controls the display data by the Display ON / OFF, Reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.
- - - - - - - - - - SEG132 SEG131 SEG2 SEG1 SEG130 SEG129 SEG128 SEG127 SEG3 SEG4 SEG5 SEG6 - - - - - ADC=1 ADC=0Column Address LCD Output DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 00H 08H 07H 06H 05H 04H 03H 02H 01H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 18H 17H 16H 15H 14H 13H 12H 11H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 28H 27H 26H 25H 24H 23H 22H 21H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 38H 37H 36H 35H 34H 33H 32H 31H 39H 3AH 3BH 3CH 3DH 3EH 3FH COM9 COM8 COM7 COM6 COM5 COM3 COM4 COM2 COM1 COM10 COM19 COM18 COM17 COM16 COM15 COM13 COM14 COM12 COM11 COM20 COM29 COM28 COM27 COM26 COM25 COM23 COM24 COM22 COM21 COM30 COM39 COM38 COM37 COM36 COM35 COM33 COM34 COM32 COM31 COM40 COM49 COM48 COM47 COM46 COM45 COM43 COM44 COM42 COM41 COM50 COM59 COM58 COM57 COM56 COM55 COM53 COM54 COM52 COM51 COM60 COM63 COMS COM62 COM61 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Start Duty Duty COM64 83 81 7F80 7E 00 - 02 0403 05 05 04 03 0102 00 7E 7F 80 8281 8301
82 When the initial display
is 1C[HEX] Figure 8 . Display Data RAM Map
in the voltage converter and display timing generation circuit. Figure 9. V DD vs. f OSC waveform and internal timing signal are shown in figure 9 . shows the M, CL, and DISP status.
Instruction specifies the scanning direction of the common output pins . Table 12. The Relationship between Duty Ratio and Common Output
0 COM[1:16] *NC COM[17:32]1/33 1 COM[32:17] *NC COM[16:1] COMS
0 COM[1:24] *NC COM[25:48]1/49 1 COM[48:25] *NC COM[24:1] COMS
0 COM[1:64]1/65 1 COM[64:1] COMS
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD LCD DRIVER CIRCUIT This driver circuit is configured by 66-c hannel common drivers (including 2 COMS channels) and 1 32 -channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal. COM 1 COM2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM 10 COM1 1 COM1 2 COM1 3 COM1 4 COM1 5 COM 16 S E G S E G S E G S E G S E G
1 SEG 3
M V SS V SS V SS V SS V SS V SS V DD V SS Figure 11 . Segment and Common Timing
The P ower S upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For details, refers to "Instruction Description". Table 13 shows the referenced combinations in using power supply circuits. Table 13 . Recommended Power Supply Combinations User setup Power control (VC VR VF) V/C circuits V/R circuits V/F circuits VOUT V0 V1 to V4 Only the internal power supply circuits are used 1 1 1 ON ON ON Open Open Open Only the voltage regulator circuits and voltage follower circuits are used 0 1 1 OFF ON ON External input Open Open Only the voltage follower circuits are used 0 0 1 OFF OFF ON Open External input Open Only the external power supply circuits are used 0 0 0 OFF OFF OFF Open External input External input
Voltage Regulator Circuits The function of the internal V oltage R egulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 16 , it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and V EV . The Ra and Rb are connected internally or externally by INTRS pin. And V EV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. V REF voltage at Ta = 25 °C is shown in table 14-1 . Rb Ra (63 - α) 3 00 Table 14-1. V REF Voltage at Ta = 25 °°C TEMPS Temp. coefficient V REF [V] L -0.05% / °C 2.0 H -0. 2 % / °C 2.0 Table 14-2. Reference Voltage Parameter s ( αα) S V5 S V4 S V3 S V2 S V1 S V0 Reference voltage p arameter ( αα) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD V EV GND Ra Rb V SS VR VOUT Figure 16 . Internal V oltage R egulator C ircuit
In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is “H”, resistor Ra is connected internally between VR pin and V SS , and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 15 . Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 The following figure shows V0 voltage measured by adjusting internal regulator re s ist o r ratio ( Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 °C. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0 8 16 24 32 40 48 56 Electronic volume level [V] (1 1 1) (1 1 0) (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) Figure 17 . Electronic Volume Level
- LCD driver voltage, V0 = 10V
- 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)
- M aximum current flowing Ra, Rb = 1 uA
The following table shows the range of V0 depending on the above requirements. Table 16. V0 D epending on Electronic Volume L evel
between V1 to V4 level and each duty ratio. Table 17. The Relationship between V1 to V4 level and Duty Ratio
Figure 20. When Using s ome LCD Power Circuits (V/C: O FF , V/R: O FF , V/F: O N ) Figure 21. When Not Using a ny Internal LCD Power Supply Circuits (V/C: O FF , V/R: O FF , V/F: O FF )
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD RESET CIRCUIT Setting RESETB to “L” or Reset instruction can initialize internal function. When RESETB becomes “L”, following procedure is occurred. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) LCD bias ratio: 1/ 7 (1/65 d uty), 1/6 (1/49 d uty), 1/5 (1/33 d uty) R ead -m odify -write : OFF SHL select: OFF (normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) D isplay start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage set: OFF Reference voltage control register: ( S V5, S V4, S V3, S V2, S V1, S V0) = (1, 0, 0, 0, 0, 0) When RESET instruction is issued, following procedure is occurred. R ead -m odify- write : OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: 0 D isplay start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage set: OFF Reference voltage control register: ( S V5, S V4, S V3, S V2, S V1, S V0) = (1, 0, 0, 0, 0, 0) While RESETB is “L” or Reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
Table 18 . Instruction Table × : Don’t care Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Read display data 1 1 Read data Read data from DDRAM Write display data 1 0 Write data Write data into DDRAM Read status 0 1 BUSY ADC ON /OFF RES ETB 0 0 0 0 Read the internal status Display ON / OFF 0 0 1 0 1 0 1 1 1 D ON Turn on/off LCD panel When D ON = 0: display OFF When D ON = 1: display ON Initial display line 0 0 0 1 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 Specify DDRAM line for COM1 Set r eference v oltage m ode 0 0 1 0 0 0 0 0 0 1 Set r eference v oltage Mode Set r eference v oltage r egister 0 0 × × S V5 S V4 S V3 S V2 S V1 S V0 Set r eference v oltage r egister Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address Set column address MSB 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address MSB Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB ADC select 0 0 1 0 1 0 0 0 0 ADC Select SEG output direction When ADC = 0 : normal direction (SEG1 → SEG132) When A DC = 1 : reverse direction (SEG132 → SEG1) Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV Select normal / reverse display When REV = 0 : normal display When REV = 1 : reverse display Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON Select normal / entire display ON When EON = 0 : normal display. When EON = 1 : entire display ON LCD bias select 0 0 1 0 1 0 0 0 1 BIAS Select LCD bias Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode Reset modify-read 0 0 1 1 1 0 1 1 1 0 Release modify-read mode Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal functions SHL select 0 0 1 1 0 0 SHL × × × Select COM output direction When SHL = 0 : normal direction (COM1 → COM64) When SHL = 1: reverse direction (COM64 → COM1) Power control 0 0 0 0 1 0 1 VC VR VF Control power circuit operation Regulator resistor select 0 0 0 0 1 0 0 R2 R1 R0 Select internal resistance ratio of the regulator resistor Set static indicator mode 0 0 1 0 1 0 1 1 0 SM Set static indicator mode Set static indicator register 0 0 × × × × × × S1 S0 Set static indicator register Power s ave - - - - - - - - - - Compound instruction of display OFF and entire display ON Test instruction 0 0 1 1 1 1 × × × × Don't use this instruction.
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD Read Display Data 8-bit data from D isplay D ata RAM specified by the column address and page address can be read by this instruction. As the column address is incre as ed by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display D ata cannot be read through the serial interface. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 Read data Write Display Data 8-bit data of D isplay D ata from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is incre as ed by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 Write data Data Write Set Column Address Set Page Address Optional Status Column = Column + 1 NO YESData Write Continue ? Dummy Data Read Set Column Address Set Page Address Optional Status Column = Column + 1 NO YESData Read Continue ? Data Read Column = Column + 1 Figure 22 . Sequence for Writing Display Data Figure 23 . Sequence for Reading Display Data
Indicates the internal status of the KS0713. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ADC ON / OFF RES ETB 0 0 0 0 Flag Description BUSY The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. ADC Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG 132 → SEG 1 ), 1: normal direction (SEG 1 → SEG 132 ) ON / OFF Indicates display ON / OFF status 0: display ON, 1: display OFF RES ETB Indicates the initialization is in progress by RESETB signal. 0: chip is active, 1: chip is being reset. Display ON / OFF Turns the display ON or OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 1 D ON D ON = 1: display ON D ON = 0: display OFF Initial Display Line Sets the line address of display RAM to determine the Initial D isplay L ine . The RAM display data is displayed at the top row (COM 1 when SHL = L, COM64 when SHL = H ) of LCD panel. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 L ine address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD R eference Voltage Select Consists of 2-byte instruction The 1 st instruction sets reference voltage mode , the 2 nd one updates the contents of reference vol tage register. After second instruction, reference voltage m ode is released. The 1 st Instruction : Set Reference Voltage Select M ode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 0 0 1 The 2 nd Instruction : Set Reference Voltage R egister RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 × × SV5 S V4 S V3 S V2 S V1 S V0 S V5 S V4 S V3 S V2 S V1 S V0 Reference voltage pa rameter ( αα) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd Instruction for Register Setting Setting R eference V oltage End 1 st Instruction for Mode Setting Setting R eference V oltage Start Figure 24 . Sequence for Setting the R eference V oltage
Sets the P age A ddress of display data RAM from the microprocessor into the P age A ddress register. Any RAM data bit can be accessed when its P age A ddress and column address are specified. Along with the column address, the P age A ddress defines the address of the display RAM to write or read display data. Changing the P age A ddress doesn't effect to the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 P age 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 Set Column Address Sets the C olumn A ddress of display RAM from the microprocessor into the C olumn A ddress register. Along with the C olumn A ddress, the C olumn A ddress defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, column addresses are automatically incre as ed. Set Column Address MSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set Column Address LSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 C olumn address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD ADC Select Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins can be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 0 ADC ADC = 0: normal direction (SEG 1 → SEG 132 ) ADC = 1: reverse direction (SEG 132 → SEG 1 ) Reverse Display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = “1” RAM bit data = “0” 0 (normal) LCD pixel is illuminated LCD pixel is not illuminated 1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated Entire Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 0 EON EON = 0: normal di splay EON = 1: e ntire di splay O N Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 1 B ias LCD biasD uty r atio D UTY 1 D UTY0 B ias = 0 Bias = 1 1/33 0 0 1/ 5 1/6 1/49 0 1 1/ 6 1/8 1/65 1 0 /1 1/ 7 1/9
This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 0 0 Reset Modify-Read This instruction cancels the Modify-read mode, and makes the column address return to its initial value just before the set Modify - read instruction is started. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 1 1 1 0 Set Modify- R ead Reset Modify- R ead Set Page Address Data P rocess NO YES Change C omplete ? Set Column Address (N) Dummy R ead Data R ead Data W rite Return C olumn A ddress (N) Figure 25 . Sequence for Cursor Display
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD Reset This instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply which is initialized by the RESETB pin. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 0 SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 SHL × × × × : Don ’t care SHL = 0: normal direction (COM 1 → COM 64 ) SHL = 1: reverse direction (COM 64 → COM 1 ) Power control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. R efer to the table 15 . RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 1 + ( Rb / Ra ) 0 0 0 1.9 0 0 0 1 2.19 0 1 0 2.55 0 1 1 3.02 1 0 0 3.61 1 0 1 4.35 1 1 0 5.29 1 1 1 6.48 Set Static Indicator State Consists of two bytes instruction. The first byte instruction (set Static Indicator mode) enables the second byte instruction (set Static Indicator r egister) to be valid. The first byte sets the static indicator ON / OFF. When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after setting the data of indicator register. The 1 st Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 0 SM SM = 0: static indicator OFF SM = 1: static indicator ON The 2 nd Instruction: Set Static Indicator Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S1 S0 Status of static indicator output 0 0 OFF 0 1 ON (about 1 second blinking) 1 0 ON (about 0.5 second blinking ) 1 1 ON (always ON)
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD Power Save ( C ompound Instruction) If the entire display ON / OFF instruction is issued during the display OFF state, KS0713 enters the P ower S ave status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, power save is entered to one of two modes (sleep and standby mode). When s tatic indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released by the display ON and entire display OFF instruction. Release Standby Mode Power Save OFF (Compound Instruction) [Entire Display OFF] [Display ON] Release Sleep Mode Power Save OFF (Compound Instruction) [Entire Display OFF] [Static Indicator ON] [Display ON] Power Save (Compound Instruction) [Display OFF] [Entire Display ON] Static Indicator OFF Static Indicator O N Sleep Mode [Oscillator C ircuit: OFF] [LCD Power S upply C ircuit: OFF] [All COM / SEG O utputs: V SS ] [Consumption C urrent: < 2 µA] Standby Mode [Oscillator C ircuit: ON] [LCD Power S upply C ircuit: OFF] [All COM/SEG O utputs: V SS ] [Consumption C urrent: < 10 µA] Figure 26 . Power Save Routine
Referential Instruction S etup F low (1) End of Initialization Waiting for Stabilizing the LCD Power Levels User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select] Start of Initialization RESETB Pin = “ H ” Waiting for Stabilizing the Power Power O N (V DD - V SS ) Keeping the RESETB Pin = “ L ” User System Setup by External Pins User LCD P ower Setup by Internal Instructions [Voltage Converter ON] User LCD P ower Setup by Internal Instructions [Voltage Regulator ON] User LCD P ower Setup by Internal Instructions [Voltage Follower ON] User LCD P ower Setup by Internal Instructions [Regulator R esistor S elect] [Reference Voltage R egister S et] Waiting for ≥ 1ms Waiting for ≥ 1ms Figure 27 . Initializing with the B uilt-in P ower S upply C ircuits
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD Referential Instruction S etup F low (2) User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select] Start of initialization RESETB pin = “ H ” Waiting for stabilizing the power Power On ( V DD - V SS ) keeping the RESETB pin = “ L ” User System Setup by External pins Set Power Save Release Power Save User LCD P ower Setup by Internal Instructions [Regulator R esistor S elect] [Reference Voltage R egister S et] Waiting for Stabilizing the LCD Power Levels End of Initialization Figure 28 . Initializing without the B uilt-in P ower S upply C ircuits
Referential Instruction S etup F low (3) End of Initialization Write Display ON / OFF by Instruction [Display O N / OFF] Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address] End of Data Display Turn Display ON / OFF by Instruction [Display O N / O FF ] Figure 29 . Data D isplaying
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD Referential Instruction S etup F low (4) Turn Display ON / OFF by Instruction [Display O FF ] Optional Status Power OFF (V DD - V SS ) User LCD Power Setup by Internal Instructions [Voltage Follower O FF ] User LCD Power Setup by Internal Instructions [Voltage Regulator O FF ] User LCD Power Setup by Internal Instructions [Voltage Converter O FF ] Waiting for ≥ 50ms Waiting for ≥ 1ms Waiting for ≥ 1ms Figure 30 . Power O FF
Table 19. Absolute Maximum Ratings
- VDD and VLCD are based on V SS = 0V.
- Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. (VLCD = V0 – VSS)
- If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
Table 20. DC Characteristics
Dynamic Current Consumption (1) when the B uilt-in Power C ircuit is OFF (At O perate M ode) ( Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used Dynamic current consumption (1) IDD1 V DD = 3.0V V0 – V SS = 11.0V 1/65 du ty ratio Display p attern OFF - - 20 µΑ *11 Dynamic Current Consumption (2) when t he built-in power circuit is ON (At operate mode) ( Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used V DD = 3.0V, quad boosting, V0 – V SS = 11.0V, 1/65 duty ratio, Display pattern OFF, Normal power mode - 70 100 µΑ *1 2 Dynamic current consumption (2) IDD2 V DD = 3.0V, quad boosting, V0 – V SS = 11.0V, 1/65 duty ratio, Display pattern checker, Normal power mode - 95 160 µΑ *1 2 Current Consumption During Power Save M ode ( Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used Sleep mode current IDDS1 During s leep - - 2.0 µA Standby mode current IDD S 2 During st andby - - 10.0 µA
KS071 3 6 5 COM / 1 32 SEG DRIVER & CONTROLLER FOR STN LCD Table 21 . The Relationship between Oscillation Frequency and Frame Frequency Duty Ratio Item f CL f M On-chip oscillator circuit is used f OSC f OSC 8 × 65 On-chip oscillator circuit is not used External input ( f CL ) f OSC 2 × 65 On-chip oscillator circuit is used f OSC f OSC 12 × 49 On-chip oscillator circuit is not used External input ( f CL ) f OSC 2 × 49 On-chip oscillator circuit is used f OSC f OSC 16 × 33 On-chip oscillator circuit is not used External input ( f CL ) f OSC 2 × 33 ( f OSC : oscillation frequency, f CL : display clock frequency, f M : LCD AC signal frequency ) [* Remark Solves] *1 . Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2 . In case of external power supply is applied. *3 . CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI , PS, INTRS, HPM, TEMPS , BSTS , DCDC5B, CLS, CL, M, DISP pins . *4 . DB0 to DB7, M , FRS, DISP, CL pins . *5 . CS1B, CS2, RS, DB [7:0], E_RD, RW_WR, RESETB, MS, MI, PS, INTRS, HPM, TEMPS, BSTS , DCDC5B, CLS, CL, M, DISP pins. *6 . Applies when the DB [7:0], M, DISP, and CL pins are in high impedance. *7 . Resistance value when ± 0.1[ mA] is applied during the ON status of the output pin SEGn or COMn. RON= ΔV / 0.1 [k Ω ] ( ΔV: voltage change when ± 0.1[ mA] is applied in the ON status.) *8 . See table 21 for the relationship between oscillation frequency and frame frequency. *9 . The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range *10 . On-chip reference voltage source of the voltage regulator circuit to adjust V0. *11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors ( Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc.
Figure 31. Display Pattern is O FF
Figure 34. Read / Write Characteristics (8080-series MPU)
Figure 35. Read/Write Characteristics (6800-series Microprocessor)
Figure 36. Serial Interface Characteristics
Figure 39. Interfacing with 6800-series (PS = “H”, MI = “H”) Figure 40. I nterfacing with 8080-series (PS = “H”, MI = “L”) Figure 41. S erial Interface (PS = “L”, MI = “H/L”)
Single Chip Configuration (1/ 49 Duty Configurations) Figure 46 . SHL = 0, ADC = 0 Figure 47 . SHL = 0, ADC = 1 Figure 48 . SHL = 1, ADC = 0 Figure 49 . SHL = 1, ADC = 1
Mu lti ple C hip Configuration - 65COM (64COM + 1COMS) ×× 264SEG (132SEG ×× 2) Figure 54 . SHL = 0, ADC = 0 ♦ Connect the following pins of two chips each other - Display clock pins: CL, M - Display c ontrol pin: DISP - LCD power pins: V0, V1, V2, V3, V4 Figure 55 . SHL = 1, ADC = 1 ♦ Connect the following pins of two chips each other - Display clock pins: CL, M - Display c ontrol pin: DISP - LCD power pins: V0, V1, V2, V3, V4
Figure 56. 130COM ( 1 28COM + 2COMS) ×× 132SEG
Figure 57. TCP Pin Layout