KS0708

KS0708 SAMSUNG | Alldatasheet

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64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 1M/M-96-D001 97-09-19 INTRODUCTION KS0708 is a single-chip LCD driver LSI for liquid crystal dot-matrix graphic display systems. It incorporates 192 driver circuit for 64 commom and 128 segment and 64x128-bit bit-map RAM. It is capable of interfac- ing with the microprocessor, accepting 8-bit parallel display data directly from it, and storing data in an onechip Display Data RAM. And it generates internal signals for using LCD driving independent of micro- processor clock.

FEATURES

¡Ü 64-Channel COMMON & 128-Channel SEGMENT Driver for DOT matrix LCD ¡Ü On-chip display data RAM : 64 X 128 = 8192bits ¡Ü Display data is stored in display data RAM from MPU - RAM bit data : ON(1), OFF(0) ¡Ü Internal timing generator circuit for dynamic display ¡Ü 8-bit parallel bi-directional data bus ¡Ü Applicable LCD duty : 1/64 ¡Ü Power supply voltages : Power supply voltage range : 4.5 ~ 5.5 V(VDD) LCD Driving voltage range : 8.0 ~ 17.0 V(VLCD = VDD - VEE) ¡Ü Wide operating temperature range : Ta = -30¡É ~ 85¡É ¡Ü High Voltage CMOS process ¡Ü Package : available bumped chip

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 2M/M-96-D001 97-09-19 BLOCK DIAGRAM

64 CHANNEL

64-BIT DATA LATCH 64-BIT DATA LATCH DISPLAY DATA RAM

64 X 64 = 4,096 BITS

PAGE & LINE Decoder PAGE & LINE Decoder Column Decoder Column Decoder RAM Address register RAM Address register INSTRUCTION DECODER INSTRUCTION DECODER ISTATUS REGISTER STATUS REGISTER I/O REGISTER I/O BUFFERI/O BUFFER OSCILLATOR DISPLAY TIMING GENERATOR CIRCUIT SHL PCLK2 VDD VEE VSS FS C CR R ADC CS1B DB0 ~ DB7 RESETB E RS RW CS2B

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 3M/M-96-D001 97-09-19 PAD CONFIGURATION 219 218 250 Y X(0,0) KS0708 (TOP VIEW) ITEM PAD NO... SIZE UNIT X Y CHIP SIZE - 12590 3630 ¥ìm PAD PITCH - 90(MIN) BUMPED PAD SIZE 1 ~ 53 56 140 54 ~ 85 140 56 86 ~ 218 56 140 219 ~ 250 140 56 BUMPED PAD HEIGHT ALL PAD 18 ¡¾ 3 . . . .

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 4M/M-96-D001 97-09-19 PAD LOCATION PAD NO. PAD NAME X Y PAD NO. PAD NAME X Y PAD NO. PAD NAME X Y PAD NO. PAD NAME X Y DUMMY DUMMY DUMMY VEE VEE VEE VDD VDD VDD VSS VSS VSS PCLK2 FS SHL ADC CS2B C CR R DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RS RW E CS1B RESETB DUMMY DUMMY C10 -6115 -6025 -5935 -5477 -5257 -5037 -4817 -4597 -4377 -4157 -3937 -3717 -3497 -3277 -3057 -2837 -2617 -2397 -2177 -1957 -1737 -1517 -1297 -1077 -857 -637 -417 -197 243 463 683 903 1123 1343 1563 1783 2003 2175 2467 2759 3051 3343 3635 3927 4219 4559 4779 4999 5219 5439 6025 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1386.5 -1296.5 -1206.5 -1116.5 -1026.5 -936.5 -846.5 -756.5 -666.5 -576.5 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 DUMMY DUMMY S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6025 5715 5625 5535 5445 5355 5265 5175 5085 4995 4905 4815 4725 4635 4545 4455 4365 4275 4185 4095 4005 3915 3825 3735 3645 3555 3465 3375 3285 3195 3105 3015 2925 2835 2745 2655 2565 2475 2385 2295 -486.5 -396.5 -306.5 -216.5 -126.5 -36.5 53.5 143.5 233.5 323.5 413.5 503.5 593.5 683.5 773.5 863.5 953.5 1043.5 1133.5 1223.5 1313.5 1403.5 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 2205 2115 2025 1935 1845 1755 1665 1575 1485 1395 1305 1215 1125 1035 945 855 765 675 585 495 405 315 225 135 -45 -135 -225 -315 -405 -495 -585 -675 -765 -855 -945 -1035 -1125 -1215 -1305 -1395 -1485 -1575 -1665 -1755 -1845 -1935 -2025 -2115 -2205 -2295 -2385 -2475 -2565 -2655 -2745 -2835 -2925 -3015 -3105 -3195 -3285 -3375 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 DUMMY DUMMY DUMMY C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 -3465 -3555 -3645 -3735 -3825 -3915 -4005 -4095 -4185 -4275 -4365 -4456 -4545 -4635 -4725 -4815 -4905 -4995 -5085 -5175 -5265 -5355 -5445 -5535 -5625 -5715 -5935 -6025 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1403.5 1313.5 1223.5 1133.5 1043.5 953.5 863.5 773.5 683.5 593.5 503.5 413.5 323.5 233.5 143.5 53.5 -36.5 -126.5 -216.5 -306.5 -396.5 -486.5 -576.5 -666.5 -756.5 -846.5 -936.5 -1026.5 -1116.5 -1206.5 -1296.5 -1386.5

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 5M/M-96-D001 97-09-19 PAD DESCRIPTION Power Supply Name I/O Description VDD Supply Power supply VSS Supply Ground VEE Supply For LCD driver circuit V0, V1 V2, V3 V4, V5 Supply LCD driver supply voltages The voltages must satisfy the following relationship VDD ¡Ã V0 ¡Ã V1 ¡Ã V2 ¡Ã V3 ¡Ã V4 ¡Ã V5 ¡Ã VEE Name I/O Description C CR R O I O RC Oscillator ¥¡) Internal clock ¥¢) External clock FS I Frequency Selection When the frame frequency is 70Hz, the oscillation frequency should be as following table. Oscillator KS0708 CR CR Rf : 47k¥Ø Cf : 20pF CfRf KS0708 CR CR OPEN Open FS - Oscillation Frequency 1 fose = 430 kHz 0 fosc = 215kHz External clock

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 6M/M-96-D001 97-09-19 Microprocessor Interface Name I/O Description CS1B I First Chip(S1 ~ S64) Select input. Data input/output is enabled via E, RS, RW, and DB[0:7]when CS1B = Low. CS2B I Second Chip(S65 ~ S128) Select input. Data input/output is enabled via E, RS, RW, and DB[0:7] when CS2B = Low. RS I Register Selection - HIGH : The data in DB[7:0] is display data - LOW : The data in DB[7:0] is control data RW I Read or Write E Enable signal. DB0 ~ DB7 I/0 Data Bus [0 ~ 7] - Bi-directional data bus RW Description H Data appears at DB< 7:0 > when E = High. L Display data DB < 7:0 > can be written at falling edge of E. RW Description H Read data in DB< 7:0 > appears the while E is high level. L Display data DB < 7:0 > is latched at falling edge of E. Name I/O Description RESETB I Reset input - Chip is initialized when RESETB is LOW Reset

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 7M/M-96-D001 97-09-19 LCD Driver Outputs Name I/O Description C1 ~ C64 O LCD driver common output S1 ~ S128 O LCD driver segment output PCLK2 I Phase of internal shift clock (CLK2) ADC I Address Control signal of Y address counter. SHL I Selection of data shift direction PCLK2 Phase of Internal Shift Clock (CLK2)

0 Data shift at the falling edge of CLK2

1 Data shift at the rising edge of CLK2

ADC Segment output direction SHL Data shift direction H C1 ¡æ C2 ¡æ C3 .... C62 ¡æ C63 ¡æ C64 L C64 ¡æ C63 ¡æ C62 .... C3 ¡æ C2 ¡æ C1

Table 1. Relationship between Chip Select pins and Read/Write Operation through the 8-bit I/O buffer(DB0 TO DB7). RS, RW and E identify the type of parallel data transfer to be made as shown in table 2. Table 2. Microprocessor Interface

ation. When low, KS0708 can accept the data or instruction. DB7 indicates busy flag of the KS0708. Figure 1. Busy timing This section explains how the timing generation circuit operates.

• Signal generation to display start line counter and display data latch circuit.
• LCD AC signal(M) generation.

lines of each page directly through DB0 to DB7. Figure 2. RAM-to-LCD data transfer

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 11M/M-96-D001 97-09-19 Page address Line address SEGMENT OUTPUT(S1~S64) DATA BUS SEGMENT OUTPUT(S65~S128) Line address Page address S S S S S S S S S S S S S S S S 0000 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 000 001 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 001 010 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 010 011 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 011 100 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 100 101 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 101

Figure 3. Display Data RAM

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 14M/M-96-D001 97-09-19 Data Tramsfer To match the timing of the display data RAM and registers to that of the controlling microprocessor, KS0708 uses an internal data bus and bus buffer. When the microprocessor reads the contents of display data RAM, the data for the initial read cycle is first stored inthe bus buffer (dummy read cycle). On the next read cycle, the data is read from the bus buffer onto the microprocessor bus. At the same time, the next block of data is transferred from RAM to the bus buffer. Otherwise, when the microprocessor write data to display data RAM. the data is written to RAM atfer the falling edge of £àE£§. Therefore, it is necessary to check Busy Flag to write or read the next data. (refer to Figure4, 5) Page Address Register The 3-bit Page Address register provides the page address to display data RAM (refer to Figure 3). The microprocessor issues Set Page Address instruction to change the page and to access another page. Column Address Counter The column address counter is a 6-bit presettable counter that provides column address to display data RAM (refer to Figure 3). It is incremented by 1 automatically after execution of each Read/Write Data instruction. The column address counter loops the values 0 to 127, and it is independent of page address register. The ADC pin is issued to change the relationship between RAM Column address and display seg- ment output. Display Start Line Register The display start line register stores the line address of display data RAM that corresponds to the first (nor- mally the top) line(COM1) of liquid crystal display(LCD) panel. See Figure 3. When displaying contents in display data RAM on the LCD panel, 6-bit data(DB[5:0]) of the Set Display Start Line is latched in display start line register. Latched data are transferred to the line address counter just before COM1 is active High, presetting the line address counter. The line counter is then incremented on the display latch clock signal once for every display line. It is used for vertical scrolling of the liquid crystal display screen.

LCD driver circuit has 192 outputs of 128 segment outputs, 64 common outputs for LCD driving. display data and internal AC signal. Table 4. Relationship between data for each input signal and the LCD drive output. low, following procedure occurs. at DB4. Refers to Read Status of ¢©INSTRUCTION DESCRIPTION¢©. The conditions of power supply at initial power up are shown in table 3. Table 5. Power supply initial Conditions. Figure 6. Reset Timing

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 16M/M-96-D001 97-09-19 INSTRUCTION DESCRIPTION Instruction Table Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Read display data 1 1 Read data Reads data (DB[0:7]) from display data RAM to the data bus. Write display data 1 0 Write data Writes data(DB[0:7]) into display data RAM. After writing instruction, column address is incremented by 1 automatically. Status Read 0 1 BUSY 0 ON/ OFF RE- SET 0 0 0 0 Reads status BUSY -0 : Ready -1 : In operation ON/OFF -0 : Display ON -1 : Display OFF RESET -0 : Normal -1 : Reset Set Column Address 0 0 0 1 Column address (0 ~ 63) Sets the Column address at the Column address counter Set Display Start Line 0 0 1 1 Display Start Line (0 ~ 63) Indicates the display data RAM displayed at the top of the screen. Set Page Address 0 0 1 0 1 1 1 Page (0 ~ 7) Sets the Page address at the Page address register. Display ON/OFF 0 0 0 0 1 1 1 1 1 0/1 Controls the display on or off. Internal status and display RAM data is not affected. L:OFF, H:ON

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 17M/M-96-D001 97-09-19 Instructions ¡á Read Display Data Reads 8-bit data display data RAM area specified by column address and page address. As the column address is incremented by 1 automatically after each read operation, the microprocessor can continue to read data of multiple words. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 Read data ¡á Write Display Data Writes 8-bit data in display data RAM. As the column address is incremented by 1 automatically after each write operation, the microprocessor can continue to write data of multiple words. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 Write data ¡á Read Status Indicates the internal status conditions of the device to the microprocessor. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY 0 ON/OFF RESET 0 0 0 0 Flag Description BUSY The device is busy due to internal operation or reset. Any instruction is rejected until BUSY goes Low. ON/OFF Indicates whether the display is on or off. When goes Low, the display is on. When goes High, the display is off. This is the opposite of Display ON/OFF instruction. RESET Indicates the initialization is in progress by RESETB signal. When Low, the chip is in active. When High, the chip is being reset.

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 18M/M-96-D001 97-09-19 ¡á Set Page Address Sets the page address of display RAM from the microprocessor into the page address register. Along with Column address register, Page address register assigns the address of the display RAM to be written to or read from display data. Changing the address doesn¢¥t affect the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 1 X2 X1 X0 X2 X1 X0 Page 0 0 0 0 0 0 1 1 : : : : 1 1 1 7 ¡á Set Column Address Sets the Column address of display RAM from the microprocessor into the Column address register. When the microprocessor reads or writes display data to or from display RAM, the address are automati- cally incremented. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 Y5 Y4 Y3 Y2 Y1 Y0 Y5 Y4 Y3 Y2 Y1 Y0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 19M/M-96-D001 97-09-19 ¡á Set Display Start Line Sets the line address of display RAM to determine the display start line. The display data on the specified line of the display RAM is displayed at the top row COM1 of LCD panel. It is followed by the higher number of lines in ascending order corresponding to the determined duty cycle. When this instruction changes the display start line address, the LCD panel can be scrolled. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB0 DB0 0 0 1 1 Z5 Z4 Z3 Z2 Z1 Z0 Z5 Z4 Z3 Z2 Z1 Z0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 ¡á Display ON/OFF Turns the display ON or OFF. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB0 DB0 0 0 0 0 1 1 1 1 1 D0 D0 = 1 : Display ON D0 = 0 : Display OFF

Figure 7. Application Diagram1

When ADC = L, connects chip select pins(CS1B,CS2B) as following. Figure 8. Application Diagram 2

When ADC = L, connects chip select pins (CS1B, CS2B) as following. Figure 9. Application Diagram 3

Figure 10. Application Diagram 4

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 24M/M-96-D001 97-09-19 SPECIFICATIONS Absolute Maximum Ratings Parameter Symbol Rating Unit Note Operating voltage VDD -0.3 ~ +7.0 V Supply Voltage VEE VDD-19.0 ~ VDD+0.3 *4 Driver Sypply Voltage VLCD VEE-0.3 ~ VDD+0.3 *2 Note : *1. Based on Vss = 0V *2. VLCD = VDD - VEE *3. Applies to SHL, FS, PCLK2, CR, RESETB, ADC, CS1B, CS2B, E, RW, RS and DB0 ~ DB7. *4. Voltage level VDD ¡Ã V0 ¡Ã V1 ¡Ã V2 ¡Ã V3 ¡Ã V4 ¡Ã V5 ¡Ã VEE Temperature Characteristics Parameter Symbol Rating Unit Note Operating temperature Topr -30 ~ +85 Storage temperature Tstg -55 ~ +125

64COM/128SEG DRIVE FOR DOT MATRIX LCD KS0708 25M/M-96-D001 97-09-19

Electrical Characteristics

Item Symbol Condition Min Typ Max Unit Note Operating Voltage VDD - 4.5 - 5.5 V Input High Voltage VIH1 - 0.7VDD - VDD *1 VIH2 - 2.0 - VDD *2 Input Low Voltage VIL1 - 0 - 0.3VDD *1 VIL2 - 0 - 0.8 *2 Output High Voltage VOH IOH = -200uA 2.4 - - Output Low Voltage VOL IOL = 1.6mA - - 0.4 Input Leakage Current ILKG VIN = VSS ~ VDD -1.0 - +1.0 uA Tri-state Leakage Current ITSL VIN = VSS ~ VDD -5.0 - +5.0 *5 Driver Input Leakage Current IDLKG VIN = VEE ~ VDD -10 - +10 *6 Operating Current IDD1 During Display - - 0.8 mA IDD2 During Access - - 1.0 *8 On resistance COM RONC VDD - VEE = 17V ¡¾ILOAD = 0.1mA - - 1.5 k§Ù SEG RONS - - 7.5 *10 Oscillation frequency fosc Ta=25¡É, VDD=5V Rf = 47k§Ù ¡¾ 2% Cf = 20pF ¡¾ 5% 315 450 585 KHz Note : *1. FS, CR, ADC, SHL, PCLK2, RESETB *2. CS1B, CS2B, E, RW, RS, DB0 ~ DB7 *3. DB0 ~ DB7 *4. Excepted DB0 ~ DB7 *5. DB0 ~ DB7 at High Impedence *7. C = 20pF, R = 47 k§Ù, fose = 450 KHz, DB0 ~ DB7 = VDD, Output = No Load *8. Excepted Clock = 430KHz, RAM Access Cycle = 1MHz