KS0655 SAMSUNG | Alldatasheet
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120 / 128 CHANNEL TFT - LCD GATE DRIVER November . 1999. Ver. 0. 1 Prepared by: Jae il Byeon keri g ma@samsung.co.kr KS0655 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
KS 0655 120 / 128 CH ANNEL TFT-LCD GATE DRIVER KS0655 Specification Revision History Version Content Date 0.0 Original Aug .1999 0.1 The contents of page 9 , 10, 13 and 14 have been modified Nov .1999
KS 0655 120 / 128 CH ANNEL TFT-LCD GATE DRIVER INTRODUCTION The KS0655 is a TFT-LCD gate driver having 120 / 128 outputs. It can drive TFT panel gate ON voltage up to 40 V. It can operate within the logic voltage 3.0 to 5.5 V.
FEATURES
- 120 / 128 outputs
- Maximum TFT panel gate ON voltage = 40 V
- Bi-directional shift register
- Logic supply voltage = 3.0 to 5.5 V
- TCP
128 Shift Register DO/I
128 Ouput Buffer
Figure 1. Block Diagram
Figure 2. Pin Assignments
120 / 128 CH ANNEL TFT-LCD GATE DRIVER KS 0655 PIN DESCRIPTIONS Symbol Pin Name I / O Description DI/O DO/I Start pulse input/output I / O When these inputs operate as the input, the start pulse data is read at the rising edge of shift clock, CPV. When these inputs operate as the output, the start pulse output is the next chip ’s start pulse input. The output pulse is generated at the falling edge of the 128th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation. (Input = DO/I and output = DI/O) U/D Shift direction control input I When U/D = H, DI/O → G001 → …… → G128 → DO/I When U/D = L, DO/I → G128 → …… → G001 → DI/O CPV Shift clock input I The shift register operates in synchronization with the rising edge of this input 120/128 Output selection input I This input selects the number of available outputs When SEL = L, 128 output mode When SEL = H, 120 output mode(G61 - G68 are disabled) OE1 OE2 OE3 Output enable input I This input controls the state of the driver outputs. When OE = H, the driver output is fixed to VOFF. When OE = L, the driver output is VGG or VOFF corresponding to the data. G001 to G128 Driver output O The output signals change in synchronization with the rising edge of shift clock input, CPV. The amplitude of the driver output is VGG - VOFF. VOFF Gate off voltage I This input is TFT-LCD gate off voltage. VLO Logic input low voltage I This input operates as the reference to the level conversion of the other input. The other logic input range: VDD - VLO VSS Negative power supply I This input is logic and driver ground. Always, has negative potential. VGG Driver positive power supply I The TFT gate ON voltage is VGG - VOFF. VDD Logic positive power supply I This is the voltage source for internal logic operation.
If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded. It is desirable to use this product within the range of the absolute maximum ratings. The power supplying order is as follows. Table 2. Recommended Operation Ratings
Table 3. DC Characteristics
- When U/D = H, DO/I used, and when U/D = L, DI/O used.
- Input swing voltage = VDD to VDD - 3.3 V
Table 4. AC Characteristics
Figure 3. AC Timing Diagram
voltage to the TFT-LCD panel depending on the pulse of the shift register. Table 5. The Relationship between U/D and the S tart P ulse Input / O utput
the data of the shift register. Table 6. The Relationship between OE and the O utput L evel
The driver negative power supply, VSS, can be any value between VLO and VLO - 15V. Figure 4. Example of Voltage Biasing
Figure 5. Recommended Timing
Figure 5. Recommended Timing (Continued)
120 / 128 CH ANNEL TFT-LCD GATE DRIVER KS 0655 NOTES