KS0652 SAMSUNG | Alldatasheet

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  • 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER KS

6 BIT 300 / 309 CHANNEL TFT - LCD SOURCE DRIVER

August . 1999. Ver. 0. 0 Prepared by: Dae-Young, Ahn Mail: jesus9@samsung.co.kr KS0 652 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.

KS 0652 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER KS0 652 Specification Revision History Version Content Date 0.0 Original Aug. 1999

KS 0652 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER INTRODUCTION The KS0652 is a 300 / 309 channel output, TFT-LCD source driver for an 64 gray-scale LCD panel. Data input is based on digital input consisting of 6 bits by 3 dots, which can realize a full-color display of 260,000 color by output of 64 values gamma-corrected. This device has an internal D/A (digital-to-analog) converter for each output and 18 (9-by-2) reference voltages. Because the output dynamic range is as large as 6.0 - 12.6 Vp-p, it is unnecessary to operate level inversion of the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side, output gray-scale voltages with different polarity can be output to the odd number output pins and the even output pins. KS0652 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel connection conveniently. Maximum operation clock frequency is 55 MHz at 2.7 V logic operation , single edge and it can be applied to the TFT-LCD panel of SVGA to XGA standard.

FEATURES

  • TFT active matrix LCD source driver LSI
  • 64 gray-scale is possible through 18 (9-by-2) reference voltages and D/A converter
  • Dot inversion display is possible
  • CMOS level input
  • Compatible with gamma-correction
  • Input of 6bits (gray-scale data) by 3 dots (R,G,B)
  • Logic supply voltage: 2.7 - 3.6 V
  • LCD driver supply voltage: 6.4 - 13.0 V
  • Output dynamic range: 6.0 - 12.6 Vp-p
  • Maximum operating frequency: fMAX = 55 MHz (internal data transmission rate at 2.7 V operation)
  • Output: 300 / 309 outputs
  • TCP

6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER KS 0652

Figure 1. KS0652 Block Diagram

Figure 2. KS0652 Pin Assignments

Symbol Pin Name Description VDD1 Logic power supply 2.7 - 3.6 V VDD2 Driver power supply 6.4 - 13.0 V VSS1 Logic ground Ground (0 V) VSS2 Driver ground Ground (0 V) Y1 - Y309 Driver outputs The D/A converted 64 gray-scale analog voltage is output. D0<0:5> - D2<0:5> Display data input The display data is input with a width of 18 bits, gray-scale data (6 bits) by 3 dots (R,G,B) DX0: LSB, DX5: MSB SHL Shift direction control input This pin controls the direction of shift register in cascade connection. The shift direction of the shift registers is as follows. SHL = H: DIO1 input, Y1 → Y309, DIO2 output SHL = L: DIO2 input, Y309 → Y1, DIO1 output DIO1 Start pulse input / output SHL = H: Used as the start pulse input pin SHL = L: Used as the start pulse output pin DIO2 Start pulse input / output SHL = H: Used as the start pulse output pin SHL = L: Used as the start pulse input pin POL Polarity input POL = H: The reference voltage for odd number outputs are VGMA1 – VGMA9 and those for even number outputs are VGMA10 – VGMA18 POL = L: The reference voltage for odd number outputs are VGMA10 – VGMA18 and those for even number outputs are VGMA1 – VGMA9 CLK2 Shift clock input Refer to the shift register's shift clock input. The display data is loaded to the data register at the rising edge of CLK2. CLK1 Latch input Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLK1 input, clears the internal shift register contents. After 1 pulse input on start, operates normally. CLK1 input timing refers to the "Relationships between CLK1 start pulse (DIO1, DIO2) and blanking period" of the switching characteristic waveform. Outputs the gray-scale data at rising edge. VGMA1 VGMA18 Gamma corrected power supplies Input the gamma corrected power supplies from external source. VDD2 > VGMA1 > VGMA2 > ……… > VGMA17 > VGMA18 > VSS2 Keep gray-scale power supply unchanged during the gray-scale voltage output. SELT Output selection input SELT = H: 300 Output (Y151 - Y159 are disabled) SELT = L: 309 Output TESTB Test input TESTB = H: Normal operation mode TESTB = L: Test mode (OP AMP CUT-OFF, Rpu = 30k Ω )

the falling edge of DIO1 (or DIO2). Output pin can be adjusted to an extended screen by cascade connection. except DIO1 and DIO2 are connected together in each device. except DIO2 and DIO1 are connected together in each device. Figure 3. Relationship between Shift Direction and Output Data

Figure 4. Gamma Correction Curve

Table 1. Resistor Strings (R0 - R63, unit: ΩΩ )

Table 2. Relationship between Input Data and Output Voltage Value

Table 2. Relationship between Input Data and Output Voltage Value (Continued)

absolute maximum rated conditions for extended periods may affect device reliability. Table 4. Recommended Operation Conditions ( Ta = -20 to 75 °°C , VSS1 = VSS2 = 0 V)

0 V )

1 . Vyo is the output voltage of analog output pins Y1 to Y309. Vx is the voltage applied to analog output pins Y1 to Y309. 2 . CLK1 period is defined to be 20 µs at fCLK2 = 33 MHz, data pattern = 101010(checkerboard pattern), Ta = 25 °C . Figure 5. Yout Load Condition

Table 6. AC Characteristics 2 . The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.

Figure 6. Waveforms

Figure 7. Waveforms