KS0647 SAMSUNG | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 15
Technical content
Datasheet sections
256 CHANNEL TFT-LCD GATE DRIVER
November . 1999. Ver. 0. 1 Prepared by: Jae il Byeon keri g ma@samsung.co.kr KS06 47 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
KS 0647 256 CH. TFT-LCD GATE DRIVER KS0 647 Specification Revision History Version Content Date 0.0 Original Aug .1999 0.1 The contents of page 9, 10 and 13 have been modified Nov .1999
KS 0647 256 CH. TFT-LCD GATE DRIVER INTRODUCTION The KS0647 is a TFT-LCD gate driver having 256 outputs. It can drive TFT panel gate ON voltage up to 40 V. It can operate within the logic voltage 3.0 to 5.5 V.
FEATURES
- 256 outputs
- Maximum TFT panel gate ON voltage = 40 V
- Bi - directional shift register
- Logic supply voltage = 3.0 to 5.5 V
- TCP
256 Shift Register DO/I
256 Ouput Buffer
Figure 1. Block Diagram
Figure 2. Pin Assignments
256 CH. TFT-LCD GATE DRIVER KS 0647 PIN DESCRIPTIONS Symbol Pin Name I / O Description DI/O DO/I Start pulse input/output I / O When these inputs operate as the input, the start pulse data is read at the rising edge of shift clock, CPV. When these inputs operate as the output, the start pulse output is the next chip ’s start pulse input. The output pulse is generated at the falling edge of the 256th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation. (Input = DO/I and output = DI/O) U/D Shift direction control input I When U/D = H, DI/O → G001 → …… → G256 → DO/I When U/D = L, DO/I → G256 → …… → G001 → DI/O CPV Shift clock input I The shift register operates in synchronization with the rising edge of this input OE1 OE2 OE3 Output enable input I These inputs control the state of the driver outputs. When OE = H, the driver output is fixed to VSS2. When OE = L, the driver output is VGG or VSS2 corresponding to the data. G001 to G256 Driver output O The output signals change in synchronization with the rising edge of shift clock input, CPV. The amplitude of the driver output is VGG - VSS2. VSS2 Driver negative power supply I The input is internally connected to the logic ground, VSS1. The input operates as the TFT panel gate OFF voltage. VLO Logic input low voltage I Logic input range: VDD - VLO VGG Driver positive power supply I The TFT gate ON voltage is VGG - VSS2. VDD Logic positive power supply I 3.0 to 5.5 V VSS1 Logic negative power supply I The logic negative power supply, VSS1, is internally connected to the driver negative power supply, VSS2.
If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded. It is desirable to use this product within the range of the absolute maximum ratings. The power supplying order is as follows. Table 2. Recommended Operation Ratings
Table 3. DC Characteristics
- DI/O, DO/I, CPV, OE1, OE2, OE3, U/D used.
- When U/D = H, DO/I used, and when U/D = L, DI/O used.
- Input swing voltage = VDD t o VDD - 3.0 V
Table 4. AC Characteristics
Figure 3. AC Timing Diagram
CPV and stored in the first shift register. CPV and the pulse of the last register (G1 or G256) is transferred to the next IC. Table 5. The relationship between U/D and the start pulse input / output is “ L ” , the level of the output is VSS2. But, when OE is “ H ” , the voltage level of the output is VSS2 irrespective of the data of the shift register. Table 6. The voltage level of the output
The driver negative power supply, VSS2, can be any value between VLO and VLO - 15V. And VSS2 is internally connected to the logic negative power supply, VSS1. Figure 4. Example of Voltage Biasing
Figure 5. Recommended Timing
256 CH. TFT-LCD GATE DRIVER KS 0647 NOTES