KS0641 SAMSUNG | Alldatasheet
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- 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER KS0641
6 BIT 300 / 309 CHANNEL TFT - LCD SOURCE DRIVER
November . 1999. Ver. 0. 1 Prepared by: Sangho Park mrno1 @samsung.co.kr KS0641 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
KS 0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER KS0641 Specification Revision History Version Content Date 0.0 Original Aug .1999 0.1 The content of page 21 has been modified Nov .1999
KS 0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER INTRODUCTION The KS0641 is a 300 channel or 309 channel output, TFT - LCD source driver for 64 gray scale displays. Data input is based on digital input consisting of 6 bits by 3 dots, which can realize a full-color display of 260,000 colors by output of 64 values gamma -corrected. This device has an internal D/A ( D igital-to- A nalog) converter for each output and 9 or 11 external power supplies. KS0641 can be adopted to larger panel, and SHL ( S hift D irection S election) pin makes use of the LCD panel connection conveniently. Maximum operation clock frequency is 55 MH z at a 3.3 V logic operation . I t can be applied to the TFT - LCD panel of SV GA, XGA standards.
FEATURES
- TFT active matrix LCD source driver LSI
- 64 gray scale is possible through 9 or 11 external power supply and D/A converter
- L ine inversion display is possible
- CMOS level input
- Compatible with gamma-correction
- L ogic supply voltage: 3.0 - 5.5 V
- LCD driver supply voltage: 3.0 - 5.5 V
- Output dynamic range: 2.6 - 5.1 Vp-p
- Maximum operating frequency: fMAX = 55 MHz (internal data transmission rate at 3.3 V operation)
- O utput: 300 / 309 outputs
- TCP
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER KS0641
Figure 1. KS0641 Block Diagram
Figure 2. KS0641 Pin Assignments
Symbol Pin Name Description VDD1 Logic power supply 3.0- 5.5 V VDD2 Driver power supply 3.0 - 5.5 V VSS1 Logic ground Ground (0 V) VSS2 Driver ground Ground (0 V) Y1 – Y 309 Driver outputs The D/A converted 6 4 gray scale analog voltage is output. D0<0: 5 > - D 2 <0: 5 > Display data input The display data is input with a width of 18 bits, gray-scale data ( 6 bits) by 3 dots (R,G,B) DX0: LSB, DX 5 : MSB SHL Shift direction control input This pin controls the direction of shift register in cascade connection. The shift direction of the shift registers is as follows. SHL = H: DIO1 input, Y1 → Y 309 , DIO2 output SHL = L: DIO2 input, Y 309 → Y1, DIO1 output DIO1 Start pulse input / output SHL = H: Used as the start pulse input pin. SHL = L: Used as the start pulse output pin. DIO2 Start pulse input / output SHL = H: Used as the start pulse output pin. SHL = L: Used as the start pulse input pin. CLK2 Shift clock input Refer to the shift register's shift clock input. the display data is loaded to the data register at the rising edge of CLK2. CLK1 Latch input Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLK1 input, clears the internal shift register contents. After 1 pulse input on start, operates normally. CLK1 input timing refers to the "Relationships between CLK1 start pulse (DIO1, DIO2) and blanking period" of the switching characteristic waveform. SELT 300 / 309CH output control input This pin controls 300CH or 309CH output. SELT = H: 309CH output → Y151 to Y159 are useless. SELT = L: 300CH output. → Y151 to Y159 are useless. This pin is internally pulled-up.(Rpu = 30 k Ω ) VGMA1 VGMA1 1 Gamma corrected power supplies Input the gamma corrected power supplies from external source. VDD2 ≥ VGMA1 > VGMA2 > ……… > VGMA 10 > VGMA 11 ≥ VSS2 Keep gray-scale power supply unchanged during the gray-scale voltage output. TEST B Test input TEST B = H : Normal operation mode TEST B = L : Test mode (OP AMP CUT-OFF) This pin is internally pulled-up.(Rpu = 30 k Ω )
KS 0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER OPERATION DESCRIPTION DISPLAY DATA TRANSFER When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the data of 300 / 309 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the next rising edge of CLK2 after the falling edge of DIO1 (or DIO2). EXTENSION OF OUTPUT Output pin can be adjusted to an extended screen by cascade connection. (1) SHL = "L" Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins except DIO1 and DIO2 are connected together in each device. (2) SHL = "H" Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins except DIO2 and DIO1 are connected together in each device.
Figure 3. Relationship between Shift Direction and Output Data Figure 4. Gamma Correction Curve
Table 2. Relationship between Input Data and Output Voltage Value:
Table 2. Relationship between Input Data and Output Voltage Value (Continued)
Table 3. Relationship between Input Data and Output Voltage Value:
Table 3. Relationship between Input Data and Output Voltage Value (Continued)
Table 4. Relationship between Input Data and Output Voltage Value:
Table 4. Relationship between Input Data and Output Voltage Value (Continued)
Table 5. Relationship between Input Data and Output Voltage Value:
Table 5. Relationship between Input Data and Output Voltage Value (Continued)
absolute maximum rated conditions for extended periods may affect device reliability. Table 7. Recommended Operation Conditions ( Ta = -20 to 75 °°C , VSS1 = VSS2 = 0 V)
- Vyo is the output voltage of analog output pins Y1 to Y309. Vx is the voltage applied to analog output pins Y1 to Y309.
- CLK1 period is defined to be 30 µs at fCLK2 = 30 MHz, data pattern = 101010 , (checkerboard pattern), Ta = 25 °C
- Input condition (VIH = 0.7 VDD1, VIL = 0.3 VDD1)
- The value is specified when the drive voltage value reaches the target output voltage level of 90%
- The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
Figure 5. Waveforms
Figure 6. Waveforms