KS0123 SAMSUNG | Alldatasheet
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PAGE 1 OF 44Modified on May/04/2000 DIGITAL VIDEO ENCODER The KS0123 multi-standard video encoder converts CCIR 656 8-bit multiplexed digital component video into analog baseband signals. It outputs composite video (CVBS) and S-Video simultaneously at three analog output pins. The encoder implements Macrovision revision 6.0 anti- taping scheme. Additionally, it contains a color subcarrier genlock to support analog/digital video splicing. The video outputs conform to either SMPTE 170M (NTSC) or CCIR 624 (PAL) standards.
FEATURES
- Macrovision revision 6.0 anti-taping support
- 8-bit parallel CCIR 656 CbYCr input format
- Synchronizes to CCIR 656 AVE time reference codes for horizontal and vertical timing generation in slave mode operation
- Generates HSYN and FIELD signals in master mode operation
- Programmable subcarrier frequency, SCH phase, and synchronous field display to support MPEG II picture-coding-extension
- Optional subcarrier genlock to analog f sc_ref refer- ence
- 650 kHz or 1.3 MHz chrominance bandwidth selec- tion
- Support NTSC, PAL, PAL-M and PAL-N
- Switchable pedestal with gain compensation
- Selectable 37 nsec YC delay pre-compensation
- Video outputs meet SMPTE 170M or CCIR 624 spec KS0123 Data Sheet
44 PLCC
PD[7:0] Demux and Sync extract Interpolator 4:2:2/4:4:4 10-bit DACChroma Modulator Sync & Blank insert Subcarrier Synthesizer Video Timing Gen D/A Ref. RESET PXCK SDA SCL SA1 SA2 Host Interface JTAGTDI TMS TCK TDO Genlock Interface INT LPF LPF Y B-Y R-Y C Y CVBS Analog Interface CSync Clamp GenlockSC_FSC SC_REF PALID HSYN FIELD 10-bit DAC 10-bit DAC General purpose I/O
ORDERING INFORMATION
Device Package Temperature Range KS0123 44 PLCC 0°~+70°C
- 27 MHz DAC conversion rate
- Triple 10-bit DAC’s for simultaneous S-video and composite output
- 2 -wire serial host interface
- 8 general purpose I/O pins
- JTAG test interface
- Single 5 V supply with power down mode
- 44-pin PLCC package Application
- Settop Box Video Encoding
- MPEG Playback
- Multimedia
The Encoder is shown in a typical settop box application. Figure 1. Typical Application
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 3 OF 44 Modified on May/04/2000 PIN DESCRIPTION Pin Name Pin # Type Description CLOCK INPUT PXCK 25 I 27 MHz clock input. TTL/CMOS. PIXEL DATA PORT PD7 - PD0 38-44, 3 I Pixel data inputs. TTL/CMOS. GENERAL PURPOSE PORT AND OTHER SIGNALS SC_REF 8 I Subcarrier reference input. TTL. D7/PAL_ID 9 I/O General Purpose I/O Port 7 or PAL_ID input. TTL/CMOS. D6/SC_SYNC 10 I/O General Purpose I/O Port 6 or SC_SYNC input. TTL/CMOS. D5 11 I/O General Purpose I/O Port 5. TTL/CMOS. D4 12 I/O General Purpose I/O Port 4. TTL/CMOS. D3/HSYN 14 I/O General Purpose I/O Port 3 or HSYN output. TTL/CMOS. D2/FIELD 15 I/O General Purpose I/O Port 2 or FIELD output. TTL/CMOS. D1/CLAMP 16 I/O General Purpose I/O Port 1 or CLAMP output. TTL/CMOS. D0/CSYN 17 I/O General Purpose I/O Port 0 or CSYN output. TTL/CMOS. SERIAL MICROPROCESSOR PORT SDA 6 I/O Serial data I/O. Open drain. SCL 7 I Serial clock input. SA1 5 I Slave address select. TTL. SA2 4 I Slave address select. TTL. RESET RESET 22 I Master reset input. TTL. VIDEO OUTPUTS CVBS 30 O Composite video output. Y 32 O Luminance output. C 35 O Chrominance output. DAC REFERENCE AND COMPENSATION VREF 27 I/O Voltage reference I/O. Connect a 0.1 µF capacitor to VSSA. BYPASS 33 I/O Compensation capacitor. Connect a 0.1 µF capacitor to VDDA. RREF 28 I/O Current setting resistor.
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 4 OF 44 Modified on May/04/2000 JTAG PORT TDI 19 I Data input port. TTL. TMS 20 I Scan select input. TTL. TCK 21 I Scan clock input. TTL. TDO 18 O Data output port. CMOS. POWER VDD 1,23,37 +5V Digital power supply. VDDA 26,34 +5V Analog power supply. GROUND VSS 2,13,24,36 0V Digital ground. VSSA 29,31 0V Analog ground. PIN DESCRIPTION (Continued) Pin Name Pin # Type Description
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 5 OF 44 Modified on May/04/2000 PIN CROSS REFERENCE Numerical Order by Pin Number Alphabetical Order by Pin Name Pin # Name Pin # Name Pin # Name Pin # Name
1 VDD 12 D4 23 VDD 34 VDDA
2 VSS 13 VSS 24 VSS 35 C
3 PD0 14 D3/HSYN 25 PXCK 36 VSS
4 SA2 15 D2/FIELD 26 VDDA 37 VDD
5 SA1 16 D1 27 VREF 38 PD7
6 SDA 17 D0 28 RREF 39 PD6
7 SCL 18 TD0 29 VSSA 40 PD5
8 SC_REF 19 TD1 30 CVBS 41 PD4
9 D7/PAL_ID 20 TMS 31 VSSA 42 PD3
10 D6/SC_SYNC 21 TCK 32 Y 43 PD2
11 D5 22 RESET 33 BYPASS 44 PD1
Name Pin # Name Pin # Name Pin # Name Pin # BYPASS 33 PD0 3 SA1 5 VDD 37 C 35 PD1 44 SA2 6 VDDA 26 CVBS 30 PD2 43 SCL 7 VDDA 34 D0 17 PD3 42 SC_REF 8 VREF 27 D1 16 PD4 41 SDA 6 VSS 2 D2/FIELD 15 PD5 40 TCK 21 VSS 13 D3/HSYN 14 PD6 39 TDI 19 VSS 24 D4 12 PD7 38 TDO 18 VSS 36 D5 11 PXCK 25 TMS 20 VSSA 29 D6/SC_SYNC 10 RESET 22 VDD 1 VSSA 31 D7/PAL_ID 9 RREF 28 VDD 23 Y 32
onto a color subcarrier and added to the processed luminance components to form the composite video (CVBS). additional external phase delay. Figure 2. Logic Diagram
Control (HANC) codes. The relationships of the digital video with analog timing are show in Figure 3. the leading edge of the analog line synchronization pulse, this time being specified between half-amplitude points. Figure 3. 656 Data Format and Timing Relationship
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 8 OF 44 Modified on May/04/2000 Timing Reference Codes Each video line can have two timing reference codes, one at the beginning of the data block (start of active video SAV) and one at the end (end of active video EAV) as shown in Figure 3. Each timing reference code consists of a four byte sequence in the form FF, 00, 00 and XX as shown in Table 1. The first three words are fixed, the fourth byte contains field and line blanking information. The encoder decodes the video timing reference code that indicates the end of active video (EAV). The EAV code shall contain the F (field) and V (blanking) bits as specified in CCIR 656. This information applies to the following video line. The encoder ignores the start of active video (SAV) timing code. The encoder uses the F bit for synchronization purposes. The transition of F bit is used to indicate the start of a new field. The polarity is also used to indicate odd and even. Additional field information is supplied by the ancillary data. The V bit is not used for synchronization. A V of ‘1’ indicates line blanking. Certain lines and half lines are blanked regardless of the state of the V bit. In general if the V bit is high, then the encoder blanks the line (Figure 10 and Figure 11). Table 1: Video Timing Reference Codes Bit # 7(MSB) 6 5 4 3 2 1 0(LSB) HEX First 1 1 1 1 1 1 1 1 FF Second 0 0 0 0 0 0 0 0 00 Third 0 0 0 0 0 0 0 0 00 Fourth 1 F V H P3 P2 P1 P0 XX Notes: F = V = H = P3 - - 0 during field 1 1 during field 2 0 elsewhere 1 during field blanking 0 in SAV 1 in EAV P0: Protection bits (not used by the encoder)
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 9 OF 44 Modified on May/04/2000 Horizontal Ancillary Data Sequence (HANC) The ancillary data contains additional timing information about the following video line. Table 2 shows the sequence of the ancillary data. The HANC data, if present, should immediately follow the EAV code. The encoder decodes the ancillary data if the ancillary data type code (TT) matches the data ID code stored in the internal ANCDID register (index 07h). The LSB of the ancillary data is a parity bit. The video encoder assumes that the data is error free and always ignores this bit. The ancillary data header (ANC) consists of three bytes which indicate the start of the ancillary data. This is in accordance with CCIR 656. The data type code is used to specify the ancillary data type. The encoder compares this value with the value programmed into the ANCDID register. If the two match, the encoder will process the ancillary data, otherwise the encoder will ignore the ancillary data. The field number bits are used by the encoder to program the field counter. The field number will be loaded to the counter if SVF/ is low and the ancillary timing reference enable (ATMEN) bit is ‘1’. Table 2: Ancillary Data Sequence Word ID Description B7 B6 B5 B4 B3 B2 B1 B0 ANC(2) Ancillary Data Header 0 0 0 0 0 0 0 0 ANC(1) 1 1 1 1 1 1 1 1 ANC(0) 1 1 1 1 1 1 1 1 TT Data Type TT6 TT5 TT4 TT3 TT2 TT1 TT0 P Reserved (R) (R) (R) (R) (R) (R) (R) P (R) (R) (R) (R) (R) (R) (R) P FIELD Field number and synchronous video flag (R) (R) (R) SVF/ F2 F1 F0 P PH(1) Subcarrier Instantaneous Phase PHV PH12 PH11 PH10 PH9 PH8 PH7 P PH(0) PH6 PH5 PH4 PH3 PH2 PH1 PH0 P FR(4) Subcarrier Frequency FRV (R) (R) FR31 FR30 FR29 FR28 P FR(3) FR27 FR26 FR25 FR24 FR23 FR22 FR21 P FR(2) FR20 FR19 FR18 FR17 FR16 FR15 FR14 P FR(1) FR13 FR12 FR11 FR10 FR9 FR8 FR7 P FR(0) FR6 FR5 FR4 FR3 FR2 FR1 FR0 P Note: 1. P = odd parity bit 2. R = reserved bit; ignored by video encoder
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 10 OF 44 Modified on May/04/2000 The subcarrier instantaneous phase is a 13-bit integer which defines the phase of the reference subcarrier at the synch tip. The subcarrier frequency synthesizer phase will be reset to this number at the synch tip when both HANC datum PHV and control register APHEN are ‘1’s. The MPEG II system allows the 27 MHz clock frequency to vary to prevent the input buffer from overflow or underflow. When this happens the color subcarrier frequency will shift if the addend of numerical oscillator is not adjusted accordingly. If control register bit AFREN is ‘1’ the subcarrier synthersizer will select the latched HANC’s subcarrier frequency data (FR) as the addend instead of the programmable register (0x8-0xb) (Figure 6). The FR is latched if HANC datum FRV = ‘1’. and the HANC control register’s AFREN bit is set. The FR’s value should be calculated using the equation where Fsc is the desired color subcarrier frequency, Ck is the clock frequency, and NINT is the nearest integer. Table 3: Definition of Subcarrier Instantaneous Phase subcarrier phase # phase value 8191 ([3600 / 8192]) * 8191 FRNIN T 232 Fsc =
4 shows the frequency responses. Figure 4. Luminance Filter Frequency Response
control (Reg 0Ch - 0Dh), and genlock functions to support digital/analog video multiplexing. Figure 6. Fsc Synthersizer to the encoder via the HANC data. The frequency and phase values are updated during the synch tip. 4 fsc. An external PAL_ID signal is required to control the PAL phase alternation. The PLL has 2 kHz pull in range.
activate the PAL_ID input, the register value of [DDR7, GENEN, FORMAT] must be set to [0, 1, 01] or [0, 1, 10]. operations the SCH phase can be adjusted via SCHM and SCHB registers to compensate external phase delay. data definition is shown in Table 2. ‘1’s and the reserved register 0x83 must be set to 0x18. Figure 9. Master Mode Video Interface Timing
Figure 10. NTSC Vertical Interval
Figure 11. PAL-B, G, H, I, N Vertical Interval
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 18 OF 44 Modified on May/04/2000 Internal Test Ramp Signal Generation The modulated ramp test signal is enabled through the host interface by setting the RAMPEN bit high. Additionally the PDEN must be set to zero to disable the pedestal and reserved registers 0x10 and 0x11 be set to ‘0’s as well. The ramp signal can be used for differential gain and phase measurements. The luminance component ramps from blanking level (0 IRE) to maximum white (100 IRE). The chroma has 40 IRE constant amplitude. Macrovision Anti-taping The Macrovision anti-taping revision 6 for PPV application is implemented. For more information please contact Samsung LA Design Center. Power on Reset The reset line is an active low signal that is used to initialize the device. Setting RESET low sets all internal state machines and control registers to their initial conditions, disables all digital and analog outputs (high impedance), and places the encoder in a power-down mode. The reserved register (0x10 - 0x1f) must be set to zero manually for proper operation.
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 19 OF 44 Modified on May/04/2000 General Purpose I/O Port and Other Signals Pins D7 through D0 form a general purpose I/O port where some pins have a dual function. The list below indicates the pin functionality. The directions of the I/Os are controlled by the DDR register. The CSYN (composite sync) output is shared with D0 pin, and is programmed with the DDR0 and CSDIS control bits as shown below. The CLAMP output is shared with D1 pin, and is programmed with the DDR1 and CLMDIS control bits as shown below. Table 5: General Purpose I/O Functions Pin Function D7 / PAL_ID General purpose I/O port; also used as the PAL_ID (PAL phase identification) signal input in the analog genlock mode. (see page15) D6 / SC_SYNC General purpose I/O port; also used as the SC_SYNC (subcarrier sync) signal input.(see page15) D5 - D4 General purpose I/O ports only. D3/HSYN General purpose I/O port in slave mode. HSYN output in Master mode.(see page15) D2/FIELD General purpose I/O port in slave mode. FIELD output in Master mode.(see page15) D1/CLAMP General purpose I/O port; also used as the CLAMP (clamp gate) output signal. D0/CSYN General purpose I/O port; also used as the CSYN (composite sync) output signal. Table 6: Control of Pin D0/CSYN DDR0 reg. CSDIS reg. GPP0 read value Effect of a GPP0 write on D0/CSYN Configuration
0 X Logic state applied to D0 no effect general purpose input
1 1 not defined outputs GPP0 logic state general purpose output 1 0 not defined no effect CSYN output Table 7: Control of Pin D1/CLAMP DDR1 reg CLMDIS reg GPP1 read value Effect of a GPP1 write on D1/CLAMP Configuration
0 X Logic state applied to D1 no effect general purpose input
1 1 not defined outputs GPP1 logic state general purpose output 1 0 not defined no effect CLAMP output
Figure 14. Reconstruction Filter for Double Ended Termination
to high) conditions. When both lines are high, the bus is considered to be free. Figure 15. Serial Bus Timing
W = 1). Figure 16 explains the data transfer operations. Figure 16. Typical Write and Read Operations to Table 8 for the possible slave addresses.
Figure 17. Serial Port Timing Parameters indicates the order in which the register data is loaded and read. The scan is 23 registers long. input. The test data output (TDO) is referred to the falling edge of TCK.
1 RESET
9 PD1 17 D6
2 PXCK 10 PD0 18 D5
3 PD7 11 SA2 19 D4
4 PD6 12 SA1 20 D3
5 PD5 13 SDA 21 D2
6 PD4 14 SCL 22 D1
7 PD3 15 SC_REF 23 D0
8 PD2 16 D7
The JTAG test port timing is shown below, refer to the timing tables at the end of this data sheet for the values. Figure 18. JTAG Test Port Timing
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 26 OF 44 Modified on May/04/2000 CONTROL REGISTERS The encoder is controlled by a set of registers which allow adjustment of its operating parameters. The registers are written to and read from via the serial bus interface. Unless otherwise specified, all registers are read/write registers. The suffix “h” denotes hex numbers. In the detailed register description, the default value is followed by an “*”. Table 10: Control Registers Index Mnemonic Default Description 00h PIDC 91h Part ID Register C (read only) 01h PIDB 88h Part ID Register B (read only) 02h PIDA 79h Part ID Register A (read only) 03h REVID 01h Part Revision Number (read only) 04h GCR 00h Global Control Register 05h VOCR 00h Video Output Control Register 06h HANC 00h Horizontal Ancillary Data Control Register 07h ANCDID 00h Ancillary Data ID Register 08h FREQD* 43h Subcarrier Frequency Byte 3 (MSBs) 09h FREQC* E0h Subcarrier Frequency Byte 2 0Ah FREQB* F8h Subcarrier Frequency Byte 1 0Bh FREQA 3Eh Subcarrier Frequency Byte 0 (LSBs) 0Ch SCHM 00h Subcarrier Phase Offset MSBs 0Dh SCHL 00h Subcarrier Phase Offset LSBs 0Eh GPP 00h General Purpose Port 0Fh DDR 00h General Purpose Port Data Direction Control 10-FFh Reserved * double buffer registers; newly loaded FREQD-B’s values will not take effect until FREQA has been updated.
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 27 OF 44 Modified on May/04/2000 Part ID Register Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h PIDC PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 01h PIDB PID15 PID14 PID13 PID12 PID11 PID10 PID09 PID08 02h PIDA PID07 PID06 PID05 PID04 PID03 PID02 PID01 PID00 PID[23:00] Chip part ID number. This is a read only set of registers. The numbers contained in the registers are: PIDA = 79h PIDB = 88h PIDC = 91h. Part Revision ID Number Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 03h REVID REVID7 REVID6 REVID5 REVID4 REVID3 REVID2 REVID1 REVID0 REVID Chip revision ID number. This read only register is used to indicate the silicon revision level number.
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 28 OF 44 Modified on May/04/2000 Global Control Register Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04h GCR 4FSCS GENEN YCDLY RMPEN YCDIS CDIS FMT1 FMT0 4FSCS Subcarrier select. 1 SC_REF frequency equals 4 times color subcarrier frequency. 0 SC_REF frequency.* GENEN Genlock (to external reference) mode enable.
1 The encoder will lock its internal subcarrier synthesizer to an external reference subcarrier
input. 0 Normal operation.* YCDLY Luma to chroma delay. This may be used to compensate for luma and chroma group delay variations of the external analog lowpass filter 1 The luminance signal is delayed by 37 nS relative to the chrominance signal. 0 Normal operation.* RMPEN Modulated ramp enable. 1 The encoder outputs a modulated ramp for differential phase and gain measurements. 0 Normal operation.* YCDIS Y/C output disable. 1 The Y and C outputs are disabled, and in a high impedance state. 0 Normal operation.* CDIS Composite output disable. 1 The CVBS output is disabled, and in a high impedance state. 0 Normal operation.* FMT Video format select. Note: the subcarrier frequency, pedestal level, and chroma bandwidth are programmed individually and are independent of the format register. 00 NTSC.* 01 PAL-B,G,H,I,N(Argentina). 10 PAL-M. 11 reserved.
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 29 OF 44 Modified on May/04/2000 Note: when SYNDIS=BURDIS=LUMDIS=CHRDIS=1, then the encoder outputs fixed DC at the blanking level. Video Output Control Register Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05h VOCR CSDIS CLMDIS CHRBW SYNDIS BURDIS LUMDIS CHRDIS PEDEN CSDIS Composite sync (COMPS) output disable. Control depends on the state of the DDR0 bit. See Table CLMDIS Clamp gating signal (CLAMP) output disable. Control depends on the state of the DDR1 bit. See Table 6. CHRBW Chroma bandwidth select. 1 Chrominance bandwidth is 1.3 MHz. 0 Chrominance bandwidth is 650 kHz.* SYNDIS Sync disable. When active, the horizontal and vertical sync pulses are disabled, and the encoder will output blanking level during this time. Active video and color burst are not affected. 1 Disable active. 0 Normal operation.* BURDIS Chroma burst (color burst) disable. Chroma data at the output is not affected by this register. 1 The chroma reference burst output is disabled. 0 Normal operation, burst is enabled.* LUMDIS Luminance input disable. Color burst and sync are not affected by this register. 1 Luminance data into the IC are forced to black level. 0 Normal operation. Incoming luminance data (Y) is enabled.* CHRDIS Chroma input disable. The color burst output is not affected by this register. 1 Chroma data into the IC is suppressed, enabling monochrome operation. 0 Normal operation. Incoming chroma (C) data is enabled.* PEDEN Pedestal (setup) enable. When active, a 7.5 IRE (nominal) pedestal is inserted into the output video for lines 23-262 and 286-525 only. The gain factors are adjusted to keep chrominance from exceeding prescribed levels. Lines 1-22 and 263-285 don’t contain setup. This register is valid for NTSC and PAL-M only. 1 Active (use only for NTSC and PAL-M). 0 Pedestal (setup) is disabled for all lines. The black and blanking levels are the same.*
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 30 OF 44 Modified on May/04/2000 Horizontal Ancillary Data (HANC) Control Register Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06h HANC Reserved NOLCK FIELD2 FIELD1 FIELD0 AFREN APHEN ATMEN Reserved Reserved. Do Not Use. NOLCK Genlock status. Read only. NOLCK is valid only when GENEN = 1. 1 Indicates that lock has not been achieved. 0 Indicates that the internal subcarrier synthesizer is locked to the external reference.* FIELD2-0 Field identification number Read only. These 3 bits indicate the digital field number.
000 Field 1
001 Field 2
010 Field 3
011 Field 4
100 Field 5
101 Field 6
110 Field 7
111 Field 8
AFREN Ancillary frequency data enable. When GLKEN = 1 (genlock to external reference), the encoder may assume that AFREN will be set to 0 by the firmware. In this case, the FREQ register value will be controlled by the genlocking circuit.
1 The encoder programs the subcarrier FREQ register from the ancillary data stream
(depending on the state of the FRV bit). 0 The FREQ register is programmed through the microprocessor interface.* APHEN Ancillary phase data enable. When GENEN = 1 (genlock to external reference), the encoder may assume that APHEN will be set to 0 by the firmware. In this case, the PHASE register value will be controlled by the genlocking circuit.
1 The encoder programs the subcarrier PHASE register from the ancillary data stream
(depending on the state of the PHV bit). 0 A value of 0 is used for the PHASE register.* ATMEN Ancillary timing reference data enable.
1 The encoder uses the timing reference data contained in the ancillary data stream (FIELD
and SVF/). 0 The ancillary timing reference data is ignored.*
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 31 OF 44 Modified on May/04/2000 Ancillary Data ID Register Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 07h ANCDID ANCD7 ANCD6 ANCD5 ANCD4 ANCD3 ANCD2 ANCD1 PARITY ANCD[7:1] The seven bits, ANCD7 through ANCD1, determine the data ID. The encoder uses the data ID to determine if the ancillary data it is receiving is meant for the encoder. PARITY Bit 0 is an odd parity bit for the ancillary data ID byte mentioned above. The encoder does not use this bit. Subcarrier Frequency Register Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 08h FREQD FRQ31 FRQ30 FRQ29 FRQ28 FRQ27 FRQ26 FRQ25 FRQ24 09h FREQC FRQ23 FRQ22 FRQ21 FRQ20 FRQ19 FRQ8 FRQ7 FRQ16 0Ah FREQB FRQ15 FRQ14 FRQ13 FRQ12 FRQ11 FRQ10 FRQ09 FRQ08 0Bh FREQA FRQ07 FRQ06 FRQ05 FRQ04 FRQ03 FRQ02 FRQ01 FRQ00 FRQ[31:00] These registers hold the 32 bit subcarrier frequency value. The FREQD-B registers are double buffered; the newly loaded msb values will not take effect until the lsb (FREQA) has been written. Subcarrier Phase Offset Register Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0Ch SCHM SCH15 SCH14 SPH13 SCH12 SCH11 SCH10 SCPH9 SCPH8 0Dh SCHL SCH07 SCH06 SCH05 SCH04 SCH03 SCH02 SCH01 SCH00 SPH[15:00] These registers hold the static subcarrier phase offset. This is used to adjust the phase of the subcarrier relative to the 50% point of the leading edge of hsync (SCH phase). The nominal value is 0. This register is used to compensate for delays external to the encoder.
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 32 OF 44 Modified on May/04/2000 General Purpose Port Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0Eh GPP GPP7 GPP6 GPP5 GPP4 GPP3 GPP2 GPP1 GPP0 GPP7 - GPP0 Registers GPP7 through GPP0 are used to read and write to I/O pins D0 through D7. The direction of flow of these pins is set by the data direction register. Note that pins D7, D6, D1, and D0 are shared with other signals. GPP7 = D7 I/O Pin. GPP6 = D6 I/O Pin. GPP5 = D5 I/O Pin. GPP4 = D4 I/O Pin. GPP3 = D3 I/O Pin. GPP2 = D2 I/O Pin. GPP1 = D1 I/O Pin. GPP0 = D0 I/O Pin. General Purpose Port Data Direction Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0Fh DDR DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 DDR7 - DDR0 Registers DDR7 through DDR0 are used to control the direction of data flow of I/O pins D0 through D7. Setting DDR(i) (where i = 7 to 0) to a low will make that pin an input. Setting DDR(i) high will make that pin an output. DDR7 = Data direction control for pin D7. DDR6 = Data direction control for pin D6. DDR5 = Data direction control for pin D5. DDR4 = Data direction control for pin D4. DDR3 = Data direction control for pin D3. DDR2 = Data direction control for pin D2. DDR1 = Data direction control for pin D1. DDR0 = Data direction control for pin D0.
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 33 OF 44 Modified on May/04/2000 ABSOLUTE MAXIMUM RATINGS Notes: 1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to VSS. 3. Forcing voltage must be limited to a specified range. 4. Current is specified as conventional current, flowing into the device. RECOMMENDED OPERATING CONDITIONS Unless otherwise specified, all specifications shall be met over the operating temperature range (0 to 70 oC, case), with a digital supply voltage (VDD) of 5.00 VDC ± 5% and analog supply voltage (VDDA) of 5.00 VDC ± 5%. Characteristics Symbol Min Max Unit Supply Voltage (Measured to GND) VDD -0.5 +7.0 V Digital Input Applied Voltage2 VI GND-0.5 VDD+0.5 V Digital Input Forced Current3,4 AI -100 100 mA Digital Output Applied Voltage2 VO GND-0.5 VDD+0.5 V Digital Output Forced Current3,4 AO -100 100 mA Digital Short Circuit Duration (single high output to VSS) TDSC 1 sec Analog Short Circuit Duration (single output to VSSA) TASC infinite sec Ambient Operating Temperature Range Ta -60 +130 °C Storage Temperature Range Tstg -65 +150 °C Junction Temperature Tj +150 °C Soldering Temperature (10 sec., 1/4” from pin) Tsol +300 °C Vapor Phase Soldering (1 min.) Tvsol +220 °C Storage Temperature Tstor -65 +150 °C Characteristics Symbol Min Typ Max Unit Supply Voltage VDD 4.75 5 5.25 V Ambient Operating Temperature Range Ta 0 70 °C
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 34 OF 44 Modified on May/04/2000 Notes: 1.Maximum IDDD and IDDA with VDD = VDDA = +5.25 VDC and TA = 0 to 70 oC. D/A converters loaded with RL = 75 Ω . 2. IDDQ when RESET = HIGH, CDIS = YCDIS = HIGH (DACs disabled). DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Total Power Supply Current (Digital Plus Analog1, FPXCK = 27 MHz) IDD 160 mA Total Power Supply Current (DACs Disabled2, FPXCK = 27 MHz) IDDQ 110 mA Digital Input Voltage, Logic HIGH TTL Compatible Inputs VIH 2.0 VDD V Digital Input Voltage, Logic HIGH Serial Port (SDA, SCL) VIH 0.7 VDD V Digital Input Voltage, Logic LOW TTL Compatible Inputs VIL VSS 0.8 V Digital Input Voltage, Logic LOW Serial Port (SDA, SCL) VIL VSS 0.3 V Digital Input Current, Logic HIGH (VIN= 4.0 V) IIH 10 µA Digital Input Current, Logic LOW (VIN=0.4 V) IIL -10 µA Digital Input Capacitance(f=1MHz,VIN=2.4 V) CIN 7 pF Digital Output Voltage, Logic HIGH CMOS Compatible Outputs (IOH=-1 mA) VOH 3.7 VDD V Digital Output Voltage Logic LOW CMOS Compatible Outputs (IOL=4.0 mA) VOL VSS 0.4 V Digital Output Voltage Logic LOW Serial Port (SDA) (IOL=3.0 mA) VOL1 VSS 0.4 V Digital Output Voltage Logic LOW Serial Port (SDA) (IOL=6.0 mA) VOL2 VSS 0.6 V Hi-Z Leakage Current, HIGH (VDD=Max, VIN=VDD) IOZH 10 µA Hi-Z Leakage Current, LOW (VDD=Max, VIN=VSS) IOZL -10 µA Digital Input Capacitance (TA=25 oC, F=1 MHz) CI 8 pF Digital Output Capacitance (TA=25 oC, F=1 MHz) CO 10 pF
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 35 OF 44 Modified on May/04/2000 Note: Timing reference points are at the 50% level. Digital CLOAD < 40 pF. PIXEL DATA PORT Characteristics Symbol Min Typ Max Unit Master Clock Rate (PXCK input) FPXCK 26.9999 27.0 27.0001 MHz Pixel Rate (FPCK = FPXCK /2) FPCK 13.5 Mpps PXCK Pulse Width, HIGH TPWH;PXCK 10 18.5 ns PXCK Pulse Width, LOW TPWL;PXCK 14.5 18.5 ns PXCK Rise Time (10% to 90% points) TRP TBD ns PXCK Fall Time (10% to 90% points) TFP TBD ns PD7-0 Setup Time TSU;PD 5 ns PD7-0 Hold Time THD;PD 3 ns Process Delay (from PD input to DAC inputs) TPD 48 PXCX Periods
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 36 OF 44 Modified on May/04/2000 Note: 1. All timing values are referred to VIH MIN and VIL MAX levels. 2. Timing specifications have been obtained by scaling the Philips I2C Fast Mode Bus specs by 80%. 3. The nominal FSCL to be used by this device is: FSCL = (FPXCK/56) = (27.0MHz/56) = 482.143 KHz. SERIAL MICROPROCESSOR PORT Characteristics Symbol Min Typ Max Unit SCL Clock Frequency (FPXCK = 27.0 MHz) FSCL Note 3 500 kHz SCL Clock LOW period TLOW 1.0 µs SCL Clock HIGH period THIGH 0.48 µs SDA & SCL input rise time TR 240 ns SDA & SCL input fall time TF 240 ns SDA output fall time from VIH MIN to VIL MAX; bus capacitance = 10 pF to 400 pF. Up to 3 mA current at VOL1. TOF1 200 ns SDA output fall time from VIH MIN to VIL MAX; bus capacitance = 10 pF to 400 pF. Up to 6 mA current at VOL2. TOF2 200 ns Bus free time between a STOP and START condition. TBUF 1.0 µs Hold time for START or repeated START condition. After this period, the first clock pulse is generated. THD;STA 0.48 µs Setup time for a repeated START condition. TSU;STA 0.48 µs Data Setup Time TSU;DAT 80 ns Data Hold Time THD;DAT 0 0.72 µs Setup Time for a STOP condition TSU;STO 0.48 µs SDA output load capacitance CB 400 pF
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 37 OF 44 Modified on May/04/2000 Note: Timing reference points are at the 50% level. Digital CLOAD < 40 pF. Note: Timing reference points are at the 50% level. Digital CLOAD < 40 pF. JTAG INTERFACE Characteristics Symbol Min Typ Max Unit Test Clock (TCK) Rate FTCK 10 MHz TCK Pulse Width, LOW TPWLTCK 10 ns TCK Pulse Width, HIGH TPWHTCK 10 ns Test Port Setup Time (TDI, TMS) TSTP 10 ns Test Port Hold Time (TDI, TMS) THTP 0 ns Output Delay, TCK to TDO Valid TDOTP 30 ns Output Hold Time, TCK to TDO Valid THOTP 5 ns MISCELLANEOUS DIGITAL SIGNALS Characteristics Symbol Min Typ Max Unit RESET/ Active (LOW) Time TSR 1 µs SC_SYNC Setup Time TSU;SC_SYNC 10 ns SC_SYNC Hold Time THD;SC_SYNC 0 ns PAL_ID Setup Time TSU;PAL_ID 10 ns PAL_ID Hold Time THD;PAL_ID 0 ns PAL_ID Duration TDUR;PAL_ID 9 PXCK periods
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 38 OF 44 Modified on May/04/2000 Notes: Timing reference points are at the 50% level. Analog CLOAD < 10 pF Digital CLOAD < 40 pF. GENLOCK PERFORMANCE ANALOG (DAC) OUTPUTS Characteristics Symbol Min Typ Max Unit DAC Resolution RES 10 bits Power Supply Rejection Ratio (Full scale output) CBYPS = 0.1µF, f = DC to 1MHz, VRIP = 100 mVp-p PSRR TBD dB Voltage Reference Output VRO 1.112 1.235 1.359 V VREF Output Impedance ZR 1000 Ω DAC Gain Factor KDAC 10.31 10.85 11.39 KDAC Imbalance Between DACs KIMBAL -5 +5 % DAC Reference Current (RREF = Nom.) IREF 1.569 mA Reference Resistor (VRO = Nom.) RREF 787 Ω Blanking Level Output Voltage (NTSC and PAL modes) VBLANK 0.300 V Video Output Compliance Voltage VOC -0.3 1.6 V Video Output Resistance ROUT 15 kΩ Video Output Capacitance (IOUT=0 mA, f=1 MHz) COUT 15-25 pF Total Output Load Resistance RL 75 Ω DAC Output Current Risetime (10% to 90% of full scale) TR 2 ns DAC Output Current Falltime (90% to 10% of full scale) TF 2 ns Analog Output Delay TDOV 20 ns Parameter Units Locking Range +2 kHz SC_REF Duty Cycle 50 + 10% Lock Time 40 lines maximum Jitter 2 deg. p-p maximum
Figure 14. The test methods and test signals meet the requirements of NTC Report No. 7 or EIA/TIA-250. A
1.0 IRE
1 IRE
Chroma/Luma Delay Inequality.
0.5 IREp-p
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 40 OF 44 Modified on May/04/2000 Notes: 1. Noise level is unified weighted, 10 kHz to 5.0 MHz bandwidth, with Tilt Null ON measuring using VM700 “Measure Mode”. A trap at the color burst frequency may be used. 2. Noise level is unified weighted, 10 kHz to 5.0 MHz bandwidth, measured using VM700 “Auto Mode”. Short Time Waveform Distortion STWD 100 IRE Step, 125 ns rise time (NTC-7 COmposite) 1 % SD Line-by-Line DC Offset LDCOFF 10% / 90% APL Bounce -1 1 IRE Dynamic Gain DYNG -1 1 IRE VIDEO PERFORMANCE CHARACTERISTICS Test Name Symbol Test Waveform Min Typ Max Unit
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 42 OF 44 Modified on May/04/2000 below the top signal layer. A low impedance ground path from the device is essential to proper operation and isolation. Use one solid ground plane under the ENCODER, do not split the ground plane. The power plane is next with additional signal planes following. Surface mount passive components can be placed on the under side (solder side) of the final signal plane. Mounting passive components (which could not be located close to the ENCODER on the top signal layer) directly under the device should provide superior performance. A four layer PC board is sufficient for most applications, but noisy densely populated designs may require more layers. The output video connectors should be located close to the ENCODER. Orient the package so that short leads can be used. The crystal oscillator components should also be mounted very close to the oscillator pins. The edge rates of clocks and other high speed digital signals should be limited to reduce ringing and noise. Termination with a small series damping resistor (~15 ohms, depends on trace and board characteristics), located at the driving end of a long transmission line, may reduce ringing.
KS0123 Data Sheet MULTIMEDIA VIDEO PAGE 43 OF 44 Modified on May/04/2000 NOTES:
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