KS0118C SAMSUNG | Alldatasheet
Document overview
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Technical content
The KS0118C is a CMOS integrated circuit designed for the GEN LOCK and ND Conversion. It is a Monolithic IC that enabled an analog NTSC composite video signal to digitize at a clock rate that is synchronized and locked to the incoming video horizontal line frequency. It includes clamping function, 8-bit digitizing and creation of a line locked sampling clock. It is possible to correspond to the video signal system of LDP by the use of KA9413, KA 9414-D ICS together, which is designed for the Digital Video Signal Processor. ORDERING IN FORMATION
FEATURES
- NTSC Video Signal Input
- Line-locked Sync and Clock Generation
- Line to Line Jitter < 20 nsec
- Differential Gain 2% Differential Phase 2 O
- Programmable Sample Clock Frequency from 25 to 30 MHz
- Built-in 8 Bit CMOS Analog to Digital Converter
- Programmable Gain Control and Automatic DC Offset Control for Video Signal Input
- Programmable PLL Time Constants for Tracking Different Input Types
- Correctly Tracks Line Drop-outs
- Provides a Microprocessor 3 Wire Serial Interface
- Built-in Decimation Filter Single Power Supply: +5V Device Package Operating Temperature KS0118C 80-QFP-1420C -20/GCE ~+75/GCE 80-QFP-1420C
Fig. 1 CLAMP 8 BIT ADC PHASE DET/ PLL FILTERDTO JITTER REDUCTION CRYSTAL DRIVER SERIAL MICOM INTERFACE 19 25 27 SFRS SCLK SDAT XTL1 XTL2 VIN SYNC DETECTOR DIGITAL OFFSET CONTROL LPF PIXEL COUNTER OUTPUT TIMING DECIMATION FILTER CVBS<0:7> LOCK VS SLICE FSMP
Fig. 2 KS0118 64 63 62 61 60 59 58 57 56 55 54 53 52 51 49 48 47 46 45 44 43 42 41 1 3 5 6 7 8 9 10 11 12 14 15 18 20 21 22 23 24 2 4 13 16 17 19 VRB VRT CREF1 VDD (A) CAGC VIN GND NC RREF GND VDD (A) RVCO CREF2 GND NC NC RCPLL RSTB NC XTL1 XTL2 VDD (A) VDD (A) GND NC NC SYG FRZ FSMP LDP SFRS NC V DD GND NC NC NC NC NC NC SLICE VS NC NC NC LOCK SDAT NC SCLK NC NC NC NC NC NC NC NC NC NC NC GND V DD (A) GND CVBS7 GND VDD NC NC NC NC NC V DD VDD CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0
Pin No Symbol I/O Description RCPLL RSTB NC XTL1 XTL2 V DD (A) VDD (A) GND NC NC SYG NC FRZ V DD GND FSMP LDP NC SFRS NC NC NC NC NC SCLK NC SDAT NC NC NC NC NC NC NC LOCK NC NC NC VS SLICE I/O I I O O I O I I I I/O O O O External Filter Pin for Analog PLL System Reset Signal Input (Active Low) No Connection Pin1 for External Crystal Oscillator Pin2 for External Crystal Oscillator + 5V Supply Voltage for Analog Domain + 5V Supply Voltage for Analog Domain Ground No Connection No Connection Line Locked Horizontal Sync Signal No Connection Connect this Pin to + 5V for proper Operation + 5V Supply Voltage for Digital Domain Ground Freq. & Phase compensated Sample Clock used for ADC Connect this Pin to + 5V for proper Operation No Connection Frame Signal for Serial Data Interface No Connection No Connection No Connection No Connection No Connection Clock Signal Input for Serial Data Interface No Connection Serial Data in Serial Interface No Connection No Connection No Connection No Connection No Connection No Connection No Connection High when the GENLOCK is locked & in Tracking State No Connection No Connection No Connection Vertical Sync Signal Output Sync level. Low when CVBS < 32. This Signal is not Line locked
PIN DESCRIPTION (Continued) Pin No Symbol I/O Description NC NC NC NC NC V DD GND CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 GND V DD VDD VDD (A) GND NC NC NC NC VRB VRT CREF1 V DD (A) CAGC VIN GND NC RREF GND V DD (A) RVCO CREF2 GND NC NC O O O O O O O O I/O I/O I/O I I I/O I/O I/O No Connection No Connection No Connection No Connection No Connection + 5V Supply Voltage for Digital Domain Ground
8 Bit Composite Video Baseband Signal
+ 5V Supply Voltage for Digital Domain + 5V Supply Voltage for Digital Domain + 5V Supply Voltage for Digital Domain Ground No Connection No Connection No Connection No Connection Bottom Voltage Reference for ADC Top Voltage Reference for ADC Decoupling Pin for Reference Voltage +5V Supply Voltage for Analog Domain Capacitor for Offset Control Analog NTSC Video Signal Input (1Vpp) Ground No Connection Current Setting Pin for Internal Analog Circuitry Ground + 5V Supply Voltage for Analog Domain Current Setting Pin for Analog VCO Decoupling Pin for Reference Voltage Ground No Connection No Connection
ELECTRICAL CHARACTERISTICS
(Ta = 25/GCE , unless otherwise specified) Characteristic Symbol Value Unit Supply Voltage Voltage on any Digital Pin Operating Temperature Storage Temperature V DD VPIN TOPR TSTG -0.5 ~+7.0 GND ~ V DD - 20 ~ + 75 -55 ~ +125 V V /GCE /GCE Characteristic Symbol Test Conditions Min Typ Max Unit Digital Input High Voltage V IH VDD = 4.75V 4.0 - - V Digital Input Low Voltage V IL VDD = 5.25V - - 1.0 V Digital Output High Voltage V OH VDD = 4.75V 4.0 - - V Digital Output Low Voltage V OL VDD = 5.25V - - 1.0 mA Static Power Current l CCS VDD = 5.25V 34 74 94 mA Dynamic Power Current I CCD VDD = 5.25V 140 - 200 mA Serial uP I/O Set-up Time t US XTL = 24.576MHz - - 10 ns Serial uP I/O Hold Time t UH XTL = 24.576MHz - - 10 ns Differential Phase DP - - 2.0 - deg Differential Gain DG - - 2.0 - % Signal to Noise Ratio SNR - 35 - - dB uP Maximum Data Rate f MPU VDD = 4.75V 5.0 - - MHz Frequency Lock Range FLT XTL = 24.576MHz 28.60 - 28.66 MHz
Fig. 3. KS0118 64 63 62 61 54 53 52 51 50 49 46 45 44 43 42 41 1 3 4 5 6 7 8 9 10 12 14 18 19 20 21 22 23 23 13 17 60 59 58 57 56 55 48 47 GND 0.1/G7F 0.1/G7F 0.1/G7F 15/G7D 10/G7F 2.4K 0.1/G7F 3nF 33pF 30K GND V11 120 200 V25 0.1/G7F V DD (A) 22/G7F 0.1/G7F 22/G7F V DD (A) 33pF10K GND VDD (A)VDD GND 0.1uF 22uF 0.1uF 22uF V DD GND X-TAL 24.576MHz 0.1/G7F 22/G7F V DD GNDGND 22/G7F 0.1/G7F VDD VDD (A) 0.1/G7D 22/G7FV DD (A) RTSB FSMP VIN
APPLICATION INFORMATION
- GENERAL DESCRIPTION The KS0118C implements the funtions of an 8 Bit ADC, Analog Clamp, Analog PLL Clock Generator and Digital Timing Generation. Throuth the use of VLSl technology, the KS0118C combines analog circuits with digital signal processing to obtain locking characteristics not achievable by ordinary methods. The KS0118C uses 1 external frequency reference to create many different programmable line lock sampling clocks. 2. ANALOG TO DIGITAL CONVERTER The KS0118C uses a two step, 8 bit and auto zero ADC to digitize the analog video input. The VRT and VRB pins are the top and bottom reference voltage for the ADC. These references are generated internally but required 0.1/GD3 decoupling capacitors to ground. 3. EXTERNAL FREQUENCY REFERENCE The KS0118C requires an external stable frequency reference to generate the sampling clock. Although a wide range of frequency will work with the GENLOCK, it is recommended that 24.576MHz be used as the reference. This can be derived from a standard crystal or an external clock. 4. ANALOG PHASE LOCK LOOP The KS0118C has an internal PLL used for producing the sampling clock. This PLL requires an external loop filter at pin 1 (RCPLL) as shown in the application circuit. The ground connections for this filter should be placed close to pin 78, while the inputs should be located close to pin 1. The PLL also requires an external resistor to converter the voltage of the RCPLL node to a current for use by the internal VCO. The voltage of the pin 76 (RVCO) will track RCPLL Although the absolute voltage of these pins depends on many factors, it will be between 0.75 and 4.50 voltalge. The voltage will exhibit the standard characteristics of an analog PLL.
Fig. 4 Data Path Propagation Delay and Key Timing Signals Fig. 5 Digitized Code Levels tDD tDSYS tDSLICE tDSVS ADC CODE = 32 VIN FSMP CVBS SLICE VS 100IRE
40 IRE
CODE = 224.234 160 ( 170 ) CODES BLANK LEVEL CODE = 84
64 63 62 61 54 53 52 51 50 49 46 45 44 43 42 41 1 3 4 5 6 7 8 9 10 12 14 18 19 20 21 22 23 23 13 17 KS9411 15 16 KS9411 KS9411 60 59 58 57 56 55 48 47 GND 0.1/G7F 0.1/G7F 0.1/G7F 15/G7D 10/G7F 2.4K 0.1/G7F 3nF 33pF 30K GND V11 120 200 V25 0.1/G7F VDD (A) 22/G7F 0.1/G7F 22/G7F VDD (A) 33pF10K GND VDD (A) VDD GND 0.1uF 22uF 0.1uF 22uF VDD GND X-TAL 24.576MHz 0.1/G7F 22/G7F VDD GNDGND 22/G7F 0.1/G7F VDD VDD (A) 0.1/G7D 22/G7FVDD (A) Composit Video Si gnal input ( 1Vpp ) from KA9411 KA9413 KA9413 KA9413