KS0108B SAMSUNG | Alldatasheet

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KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION

100 QFP

The KS0108B is a LCD driver LSl with 64 channel output for dot matrix liquid crystal graphic display system. This device consists of the display RAM, 64 bit data latch 64 bit drivers and decoder logics. It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix Iiquid crystal driv- ing signals corresponding to stored data.The KS0108B composed of the liquid crystal display system in combina- tion with the KS0107B (64 common driver)

FEATURES

  • Dot matrix LCD segment driver with 64 channel output
  • Input and Output signal - Input: 8 bit parallel display data Control signal from MPU Splitted bias voltage (V1R, V1L, V2R, V2L, V3R. V3L, V4R, V4L) - Output: 64 channel waveform for LCD driving.
  • Display data is stored in display data RAM from MPU.
  • Interface RAM - Capacity: 512 bytes (4096 bits) - RAM bit data: RAM bit data = 1:ON RAM bit data- = 0:OFF
  • Applicable LCD duty: 1/32~1/64
  • LCD driving voltage: 8V~17V(VDD-VEE)
  • Power supply voltage: + 5V±10% Driver Controller COMMON SEGMENT KS0107B Other KS0108B MPU
  • High voltage CMOS process.
  • 100QFP and bare chip available.

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD BLOCK DIAGRAM INPUT REGISTER BUSY INSTRUCTION DECODER Y-COUNTER Y-DECODER X-DECODER LCD DRIVER DATA LATCH DISPLAY DATA RAM 512¡¿8=4096 bits DISPLAY ON/OFF OUTPUT REGISTER I/O BUFFER DISPLAY START LINE REGISTER Z DECODER PAGE SELECTOR 646 S64 S63 S2 S1 V5R V3R V2R V0R M V5L V3L V2L V0L FRM CL ADC RSTB E RS R/W CS3 CS2B CS1B CLK2CLK1DB<0:7>

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD Fig.2. 100QFP Top View 123456789101112131415161718192021222324252627282930 807978777675747372717069686766656463626160595857565554535251 100 ADC M VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 DB1 DB0 VSS V3L V2L V5L V0L VEE1 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 DB2 DB3 DB4 DB5 DB6 DB7 NC NC NC CS3 CS2B CS1B RSTB R/W RS CL CLK2 CLK1 E FRM KS0108B

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD PIN DESCIPTION PIN (NO) SYMBOL INPUT/OUTPUT DESCRIPTION 73, 8 VDD VSS VEE1.2 Power For internal logic circuit (+5V±10%) GND (0V) For LCD driver circuit VSS=0V, VDD=5V¡¾10% VDD-VEE=8V~17V VEE1 and VEE2 is connected by the same voltage. 74, 7 76, 5 77, 4 75, 6 V0L, V0R V2L, V2R V3L, V3R V5L, V5R Power Bias supply voltage terminals to drive the LCD. CS1B CS2B CS3 Input Chip selection In order to interface data for input or output The terminals have to be CS1B=L, CS2B=L, and CS3=H. 2 M Input Alternating signal input for LCD driving. 1 ADC Input Address control signal of Y address counter. ADC=L→ DB<0:7>=0→ Y63→ S64 DB<0:7>=63→ Y0→ S1 100 FRM Input Synchronous control signal. Presets the 6-bit Z counter and syncronizes the common signal with the frame signal when the frame signal becomes high. 99 E Input Enable signal. write mode (R/W=L) → data of DB<0:7> is latched at the falling edge of E. read mode (R/W=H) → DB<0:7> appears the reading data while E is at high level. CLK1 CLK2 Input 2 phase clock signal for internal operation. Used to execute operations for input/output of display RAM data and others. 96 CL Input Display synchronous signal. Display data is latched at rising time of the CL signal and increments the Z-address counter at the CL falling time. 95 RS Input Data or Instruction. RS=H→ DB<0:7> : Display RAM Data RS=L→ DB<0:7> : Instruction Data 94 R/W Input Read or Write. R/W=H → Data appears at DB<0:7> and can be read by the CPU while E=H, CS1B=L, CS2B=L and CS3=H. R/W=L¡æDisplay data DB<0:7> can be written at falling of E when CS1B=L, CS2B=L and CS3=H. 79~86 DB0~DB7 Input/Output Data bus. There state I/O common terminal. Select Level Non-Select Level V0L(R), V5L(R) V2L(R), V3L(R)

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD PIN DESCRIPTION (continued) PIN (NO) NAME INPUT/OUTPUT DESCRIPTION 72~9 S1~S64 Output LCD Segment driver output. Display RAM data 1:ON Display RAM data 0:OFF (Relation of display RAM data & M) 93 RSTB Input Reset signal. When RSTB=L, (1) ON/OFF register becomes set by 0. (display off) (2) Display start line register becomes set by 0 (Z-address 0 set, display from line 0) After releasing reset, this condition can be changed only by instruction. 87~89 NC No connection.(open) MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Note Operating Voltage VDD -0.3~+7.0 V *1 Supply Voltage VEE VDD-19.0~VDD+0.3 V *4 Driver Supply Voltage VB -0.3~VDD+0.3 V *1,3 VLCD VEE-0.3~VDD+0.3 V *2 Operating Temperature TOPR -30~+85 °C Storage Temperature TSTG -55~+125 °C *1. Based on VSS=0V. *2. Applies the same supply voltage to VEE1 and VEE2. VLCD=VDD-VEE. *3. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0~DB7. *4. Applies V0L(R), V2L(R), V3L(R) and V5L(R). Voltage level: VDD≥V0L=VOR≥V2L=V2R≥V3L=V3R≥V5L=V5R≥VEE. M DATA Output Level L L V2 H V0 H L V3 H V5

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD

ELECTRICAL CHARACTERISTICS

DC Characteristics (VDD=4.5~5.5V, VSS=0V, VDD-VEE=8~17V, Ta=-30~+85°C) Characteristic Symbol Condition Min Typ Max Unit Note Input High Voltage VIH1 - 0.7VDD - VDD V *1 VIH2 - 2.0 - VDD V *2 Input Low Voltage VIL1 - 0 - 0.3VDD V *1 VIL2 - 0 - 0.8 V *2 Output High Voltage VOH IOH=-200µA 2.4 - - V *3 Output Low Voltage VOL IOL=1.6mA - - 0.4 V *3 Input Leakage Current ILKG VIN=VSS~VDD -1.0 - 1.0 µA *4 Three-state(OFF) Input Current ITSL VIN=VSS~VDD -5.0 - 5.0 µA *5 Driver Input Leakage Current IDIL VIN=VEE~VDD -2.0 - 2.0 µA *6 Operating Current IDD1 During Display - - 100 µA *7 IDD2 During Access Access Cycle=1MHz - - 500 µA *7 On Resistance RON VDD-VEE=15V ¡¾ILOAD=0.1mA - - 7.5 KΩ *8 *1. CL, FRM, M, RSTB, CLK1, CLK2 2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7 3. DB0~DB7 4. Excepted DB0~DB7 5. DB0~DB7 at High lmpedance 6. V0L(R), V2L(R), V3L(R), V5L(R) 7. 1/64 duty, FCLK=250KHZ, Frame Frequency=70HZ, Output: No Load 8. VDD~VEE=15.5V V0L(R)>V2L(R)=VDD-2/7 (VDD-VEE)>V3L(R)=VEE+2/7(VDD-VEE)>V5L(R) AC Characteristics (VDD=5V±10%, VSS=0V, Ta=-30°C~+85°C) (1) Clock Timing Characteristic Symbol Min Typ Max Unit CLK1, CLK2 Cycle Time tCY 2.5 - 20 µS CLK1 ‘LOW’ Level Width tWL1 625 - - CLK2 ‘LOW’ Level Width tWL2 625 - - CLK1 ‘HIGH’ Level Width tWH1 1875 - - ns CLK2 ‘HIGH’ Level Width tWH2 1875 - - CLK1-CLK2 Phase Difference tD12 625 - - CLK2-CLK1 Phase Difference tD21 625 - - CLK1, CLK2 Rise Time tR - - 150 CLK1, CLK2 Fall Time tF - - 150

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD (2) Display Control Timing Characteristic Symbol Min Typ Max Unit FRM Delay Time tDF -2 - +2 us M Delay Time tDM -2 - +2 us CL ‘LOW’ Level Width tWL 35 - - us CL ‘HIGH’ Level Width tWH 35 - - us CLK1 CLK2 tF tR tCY tWH1 tWL1 tD12 tD21 0.7VDD 0.3VDD 0.7VDD 0.3VDD tF tF tWH2 tCY Fig 1. External clock waveform tWLL tWL 0.7V DD 0.3V DD 0.7V DD 0.3V DD 0.7V DD 0.3V DD tWH tDF tDF tDM Fig 2. Display control signal waveform CL FRM M

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD (3) MPU Interface Chatacteristic Symbol Min Typ Max Unit E Cycle tC 1000 - - ns E High Level Width tWH 450 - - ns E Low Level Width tWL 450 - - ns E Rise Time tR - - 25 ns E Fall Time tF - - 25 ns Address Set-Up Time tASU 140 - - ns Address Hold Time tAH 10 - - ns Data Set-Up Time tSU 200 - - ns Data Delay Time tD - - 320 ns Data Hold Time (Write) tDHW 10 - - ns Data Hold Time (Read) tDHR 20 - - ns E R/W CS1B-CS3,RS DB0-7 Fig 3. MPU write timing 2.0V 0.8V tC tWL tWH tR tF tASU tAH tASU tAH tDSU tDH 0.8V 2.0V

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD E R/W CS1B-CS3,RS DB0-7 Fig 3. MPU write timing tC tWL tWH tK tF tASU tASU tAH tAH tD tDH

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD APPLICATION CIRCUIT 1.1/64 duty common driver(KS0107B) interface circuit VOR,VOL V5R,V5L V1R,V1L V4R,V4L VEE VDD SHL FS MS PCLK2 DS2 DS1 VSS KS0107B DIO1 DIO2 M FRM CLK1 CLK2 CL2 CL C64 R CR C RSTB DB7 DB0 E RS R/W CS3 CS2B CS1B VDD ADC VOR,VOL V5R,V5L V2R,V3L V3R,V3L VEE1, VEE2 VSS KS0108BM FRM CLK1 CLK2 CL2 Open Open S1 S64 SEG1 SEG64 LCD COM1 COM64 VEE VDD Rf Cf from MPU VDD VEE VSS VDD VEE

arily before writing it into display RAM. status data (busy check) can read out. RAM, it needs dummy read. But status read is not needed dummy read. Reset can be initialized system by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occured.

  1. Display start line register become set by 0.(Z-address 0)

instruction can be accepted. The Conditions of power supply at initial power up are shown in table 1. Table 1. Power Supply Initial Conditions

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 5. Busy flag Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in internal operating. When busy flag is low, KS0108B can accept the data or instruction. DB7 indicates busy flag of the KS0108B. 6. Display On/Off Flip-Flop The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on segment output terminals regardless of display RAM data. The display on/off flip-flop can changes status by instruction. The display data at all segment disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read instruction. The display on/off flip-flop synchronized by CL signal. 7. X Page Register X page register designates page of the internal display data RAM. It has not count function. An address is set by instruction. 8. Y address counter Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased by 1 automatically by read or write operations of display data. 9. Display Data RAM Display data RAM stores a display data for liquid crystal display. To express on state dot matrix of liquid crystal display, write data 1. The other way, off state writes 0. Display data RAM address and segment output can be controlled by ADC signal. ADC=H¢¡ DB<0:7>=0 - Y-address 0 - A0 - S1 DB<0:7>=63 - Y-address 63 - A63 - S64 ADC=L¢¡ DB<0:7>=0 ~ Y-address 63 - A63 - S64 ADC terminal connect the VDD or VSS. 10. Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of the liquid crystal display screen.

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD DISPLAY CONTROL INSTRUCTION The display control instructions control the internal state of the KS0108B. Instruction is received from MPU to KS0108B for the display control. The following table shows various instructions. Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Display ON/OFF L L L L H H H H H L/H Controls the display on or off. Internal status and display RAM data is not affected. L:OFF, H:ON Set Address L L L H Sets the Y address in the Y address counter. Set Page ( X address) L L H L H H H Sets the X address at the X address register. Display Start Line L L H H Indicates the display data RAM displayed at the top of the screen. Status Read L H B U S Y L O N O F F R E S E T L L L L Read status. BUSY L: Ready H: In operation ON/OFF L: Display ON H: Display OFF RESET L: Normal H: Reset Write Display Data H L Writes data (DB0:7) into display data RAM. After writing intruction, Y address is increased by 1 automatically. Read Display Data H H Reads data (DB0:7) from display data RAM to the data bus. Y address (0~63) Page (0~7) Display start line (0~63) Write Data Read Data

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 2. Timing diagram (1/64 duty)

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 3. LCD Panel interface application circuit KS0108B NO. 8 S1 S64 KS0108B NO. 2 S1 S64 KS0108B NO. 1 S1 S64 S1 S64 NO.16 KS0108B S1 S64 NO.10 KS0108B S1 S64 NO.9 KS0108B COM1 LCD PANEL (128x480 dots) COM2 COM3C1 COM64 COM128 COM67 COM66 COM65 KS0107B (Master) KS0107B (Master) C64 C64

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD PAD DIAGRAM (0,0) X Y CHIP SIZE : 4090¡¿4020 PAD SIZE : 100¡¿100 UNIT : ¥ìm 3 2 1 100 99 98 97 96 95 94 93 92 91 90 86 85 84 83 82 81 80 79 78 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5130KS0108B * “KS0108B” Marking : easy to find the PAD No.30

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD PAD LOCATION PAD NAME PAD NAME PAD NAME PAD NUMBER PAD NUMBER PAD NUMBER COORDINATECOORDINATECOORDINATE YY XXYX 791 916 1041 1166 1310 1435 1559 1684 1809 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1882 1882 1882 1882 1882 1882 1882 1882 1882 1412 1277 1142 1007 882 757 632 507 382 NC NC NC 245 120 -130 -255 -380 -505 -630 -755 -880 -1005 VEE1 V0L V5L V2L V3L VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CS3 CS2B CS1B RSTB R/W RS CL CLK2 CLK1 E FRM 100 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1379 -1239 -1099 -959 -834 -709 -584 -459 -334 -209 -84 166 291 416 541 666 -687 -562 -437 -312 -187 -62 187 312 437 562 687 812 937 1062 1187 1487 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 1845 1845 1845 1809 1684 1559 1434 1309 1165 1040 915 790 665 540 415 290 165 -84 -209 -334 -459 -584 -709 -834 -959 -1099 -1239 -1379 -1845 -1845 -1845 -1845 -1845 -1140 -1275 -1410 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1487 -1187 -1062 -937 -812 ADC M VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39