KS0104

KS0084 SAMSUNG | Alldatasheet

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KS0083/84 CMOS DIGITAL INTEGRATED CIRCUIT 80-CHANNEL SEGMENTICOMMON DRIVER FOR DOT MATRIX LCD 100 QFP S0083/84 is a graphic type LCD driver LSI which is fabricated by CMOS process for high voltage. In case of segment driver, can be selected 4 bit, 1 bt data transfer or chip select mode, KS0084 is reverse type of KS0083 FUNCTION City, + DOT MATRIX LCD DRIVER with 80 channel output. Hh ts + bias voltage (V3, Vs, Vss)

FEATURES

+ Power supply voltage: -SV+10% + LCD driving voitage: -24V(typ) (Vee) + Interface type 1 | type 2 | type 3 ksoveaes |ksoewves/ KS0108 Kso104 | * 100QFP and bare chip available BLOCK DIAGRAM u Sor CBO CI | = “wQ ro ae oa: a LT [se Ds seme Piece ous {Her [| seme ae e | Ae Leo Ps] ntfs] | a Fig. 1 KS0083/84 functional block diagram. ——— eee Pie monne 2 191

KS0083/84 CMOS DIGITAL INTEGRATED CIRCUIT ——— PIN CONFIGURATION SFiS isdidiidisiidissssssissas AIESISaLISSISIS A SIEGE SIBIS IEEE lees ele V5 (By , 150) SC50 Vee 6 O 149] SCan Fes Bg [43)SCae Eo [e4 147} SC47 » BS 146) SCoe Voo Bi ae}SCus cuxt B7] 44} SCae e Ba [63] C43

00 Ba AA SCa2

vs Bi ks0083 a}sca Dt, (By 40) Vss Dt 2] 139} SCoo Or BF [38] C30 on Bal [37}SCae nc ps} 96] SC37 CLK2 bal SS} SC, Ves [97] [34] SC3s v, Ba 153) SC3e Ps (99) 3]SCs3 $C; 100 © 131] SCaz HN} 1) Le Gdddsesdsigidddaadsdddddisdsss Fig. 2. 100 QFP Top View i SEE EEE ——_i 422

KS0083/84 CMOS DIGITAL INTEGRATED CIRCUIT ee PIN CONFIGURATION GIISSSSSSSS SF SsFGSFFFGGGSRGEEES joo] fro) {5)f 77] Pre] frs] fr] 3) 72] [75] f70) feo] fee) fer) (ee) fos) fos] (63) [22] [or] fe] (59) [56] [57] [56] [5s] [54] (=9]/>2] [21] sofa O [ejscx Ps [ee] 49] SCa3 V«[e3] [6] scx Vss [aa [+7] seas cure as} [et] Soe ne [ee] 145] SCsr Drs [7] 144] $Can Die [86] 143] SCxe 13[89] 42] $0 Dua KS0084 [+5] vas Ves [31 [+3] sca bo [22} [39] SC er [93] 38]SCe cui [24] BT Ste Ven [93 ps] sc mse} [25] SCxe E07] [34] 9Cer Fes [sa] /33|SCe Vee [oo] }32]SCea vaioqd ©) 31} 8Cxa SSessaasseesi sisi sd asd sss ssiss Fig.3 1000FP Top View. eS atte we

KS0083/84 CMOS DIGITAL INTEGRATED CIRCUIT ttt SES PIN FUNCTIONAL DESCRIPTION Input i Pi Description Interface SC1-SCoo LCO driver output terminals (80 Channel} cD (100, 1-39, 41-80) | Vs{40,90,97) GND (OV) Power Power supply Vee (82) LCD driving Votage (-24V) Supply Voo(86) Internal Logic driving Voltage Vs, Val81, 98) Bias Voltage input for LCD drive: Non-select Level (Must maintain Power VSS>V3>V4>VEE} oe FCS, PS Input | Mode Select inputs. {refer to application circuit) |#3.20) ~ Chip | | mn aoe me [BE [U |_H [Seamereaiver | <itpanbaingut| | | |W | 1 [Seomentamver |tbesefainat | x | || [_H[_¥ [Canmondiver|Sefainet [0 | 0 | ~ Incase of serial input mode, Dit is data input pin and DO is data output pin = Incase of 4 bit parallel input mode, Data input and output are; Dh | Sci, 8Cs,..8Crr_| Dl | SCz, SCs, ..SCre [be | Scs,S6r...s0m | Om | $c, $6a SC | “bit Deta shit direction 1 bit Date shitt | BeSS5SSS Ss tses sess r7v77777te eee53 tre | ERE SAREE eat at ee | | PEL FTES) ARR Nets tte \\ me eal meer | i om = Incase of the common driver, the data transfer clock is CLK2 = Non-used data input pins are sat to Vss or Vo to minimize current consumption i PS ja

KS0083/84 CMOS DIGITAL INTEGRATED CIRCUIT A Ann PIN FUNCTIONAL DESCRIPTION (continuec Input mm se | EO, &l input Input/Output for Chip Select, controller (84, 68) output | 1) EO becomes low by (CLK1, CLK2} timing. or | 2) When "HIGH" date is Input to El, the device becomes select | KS0083/84 mode and reads input data at CLK2 falling timing. | Symchronized at the tall of CLK2. Input data is shifted, | 3) Alter reading 80 input datafequivalent to 80 CLK2 clock cycle | H In the serial mode or 20 CLK2 clock cycles in the 4 bit paralle mode}, EO autornatically becomes HIGH level and data read- j Ing is complete. EO is reset 1.5 cycles tater, 4) When two or more devices are used in the chip select mode, | EO of each stage is connected to El of the next stage. {1} EO of af device connected is reset and device becomes non-select state and waits for El input after the previous | th (2) When *HIGH’ level is input to the first El in the cascade | connection, the first device performs the operations in 2) and 3). (3) When El of the second device Is connected to DO of the | | first device, the second device perform the operations 2} | and 3) after the first device. This operation is repeated in | the same method subsequently M85) "| input LCD waveform AC conversion signal input | foe ce ee te pon-sdecy |"H[ ve || comet ; oo | Te | ve | | wert] [_ a TAT ano | j (segment signal drive mode) (common signal drive mode) cuxien : srfommenneaes | corsober ‘CLK2{96) input | Clock pulse input terminal for data shirt controler Di1~D14(91-94) Input | Display data input from the LCD controtir LSI, controller in case of the common driver mode or serial input mode, supplu | the input data to Dit and DI2-DIS have to be set to VSS level or VDD jevel. abut | OO hgh line cp wands remanas NC No Connection : | ne Pec 125

KS0083/84 CMOS DIGITAL INTEGRATED CIRCUIT MAXIMUM ABSOLUTE LIMIT (r.=25°C) [____@haractedatic ST Symbot_ [vee ut a CE vege v wp vag [ww | ono 10 _—| parang temperate Tox = Sloage tere Tas *Voltage greater than above may damage to the circuit. Maximum absolute limits are those values beyond which permanent damage to the device may occur. These are stress ratings only and functional operation of the device beyond them is not implied.Long exposure to these conditions may affect device reliability. DC CHARACTERISTICS (voo= -5V+ 10%, Vss=OV, Vee= -24V+3V, Ta=25°C) [Charteris | Stet [Test nao [ine [Me Unt] [eo peat omnes | | | 100 _| a vouge [tow [wep ee 0 | cuba [Hom [vow [ue-ommk Sip mow | | | votuge [tow | va [roamed emt |v Votage [vor [extn trowase || [10 |v | descending (V+SCi) oe _ | lon=0.08mA for each SCi es ee ee u = ee ee cunent | Ow | ho | = es es Pirsig > ELECTRONICS mm 7964142 0021979 Sbb

(Voo= —5 V+ 10%, Vss=OV, Vee=—24V43V; T= +25°C) (1) Segment driver; 1. bit serial data input (PS=LOW, FCS=LOW) (refer to: fig. 3) | Characteristic ‘Symbol Test condition Max Unit | [Clock cycle time le 300 High level twee 4 | Clock pulse width = gh fev | __tw se ~ Low level tw _| 130 Set up time D before CLK24 Tt 70 es a — | Meeime mate cunat ef so | lock margin time ! (trom CLK14 to CLK24) - | tr | - 20 ns Clock margin time 2NOTE 1 (trom CLK2s to CLK14) _ toe 200 Clock margin time 3 : | | (from CLK2t to CLK11) 7 ‘ca ‘a Clock rise/fall time - ptt 50 Output Delay | C.=15pF 230 ft C= 150 - SO High level latch clock width | town o 130 NOTE 2 |__Overlap time of CLK2 "L" and CLK1"H" | toy 130 | (2) segment driver; 4 bit data input (PS=High, FCS=LOW) (reter to: fig 4.) Clock cycle time te 500 ligh level 3 Clock pulse wisth [ Monlevel | tw f 280 —— | Low level | tw _ 230 Set-up time D before CLK24 Tt 70 Hold time D after CLK2s i th T 50 (from CLK14 to CLK24) ter 20 ns Clock margin time 2 NOTE 1 (from CLK2} to CLKIY) tee - 200 Clock margin time 3 j 20 | (from CLK2t to CLK1t) Ss | Clock rise/fall time tot 50 | Output Delay _ | to _C.=15pF 7 230 | High level latch clock width {tw 130 | NOTE2 {___Overiap time of CLK2 “L" and CLK1 “H” | tov | 130 | L_Qveriap time of CUK2 “th and CUT MH” toy | tO PSimsunad ” ELECTRONICS @™ 7964142 0021980 258

(3) Common Driver (PS=HIGH, FCS=HIGH) (refer to: fig 5) Clock cycle time te 1000 [ iH | Clock pulse width High level ‘wn ee oe Set-up time D before CLK+ tsu 70 ns Clock rise/fall time teste | 59 | (4) segment driver 2; 1 bit serial data input (PS=LOW, FCS=HIGH) (reter to: fig 6) Characteristic Symbol_| Test condition | Min | Max | Unit Clock cycle time __ te __ | 380 ligh level 171 Clock pulse width High level ‘wa ° Low level tw | | Set-up time D before CLKt [teu } _ 70 i Hold time O after CLKt ty _ 50 | cack magntme1 {from CLK14 to CLK24) , mf ; 20 ns Clock margin time 2 NOTE 1 \\ 200 | (from CLK2# to CLK14) & | Clock margin time 3 | (trom CLK2t to CLK11) tos 20 \\ Clock rise/fall time tet i 50 | Output delay _ to CL=15pF | 230 | i High level latch clock with town 130 | NOTE2 level latch clock with fw _) i Overtap time of | CLK2 “L" and CLK1 “H” tov 130 note (input frequency, VO reference level; 0.8 Voo. 0.2 Voo) 1: Valid time {internal shift register) 25 (teX1.S}(tor}(tea} AX 3) SSeS ELECTRONICS @™ 7964142 0021981 114 On

KS0083/84 CMOS DIGITAL INTEGRATED CIRCUIT nn TIMING DIAGRAM cuKe “ im | os ain. re 9 | Tsu {we 00 > . . | 2 toy i a tes, ter | cuKt tow - Fig. 3 Segment driver (1 bit serial input) Ava. cuK2 tom * | | | | | te j | tow ‘eo tw | too ies cuKt { EO to cs cy Fig. 4. 4-bit input segment driver <= . ELECTRONICS mm 7564142 0021982 OSO

KS0083/84 CMOS DIGITAL INTEGRATED CIRCUIT TIMING DIAGRAMS (Continued) CLK2 twa al i teu ty 00 a a x Fig. 5. Common driver CLK2 fw 0.2Vo0 0.8Vc0 +E | oh f 3 Lo] ter a oy {i> a \\ LIT] te [| [| ‘ce os EO L} rank to to to Fig. 6. Segment driver (1 bit serial data input) <= ° ELECTRONICS mm 7964142 0021983 11? mbH NA OOCLIT TT

APPLICATION CIRCUIT . Mode Select 1. segment driver 1; 1 bit serial data input (FCS=L, PS=L) 2. segment driver; 4 bit data input (FCS=L, PS=H) LCD PANEL LCD PANEL are: ae: Sy SC, 3Cy5C Do Sy-SCa0 from LCD SC0 Seo from LCD moaned >-o—101, 0083/84 O9—Jh KS008/84 Dd--~ jel KS0083/84 Eof— EI KS0083/84 Eof--- contoler “Diepiay controter Dy Diz ls Dla | Dl; Dip Dis Dl, are o 111 TTI _ ° ee es ° es Ge Display data 3. segment driver 2; 1 bit serial data input (FOS=H, PS=L) 4. common driver (FCS=H, PS=H) from LCDS, 6 controler ” Display data Poh SC LOD PANEL. sgossree Oo Lep PANEL Dh ge 4s oni Roma SC, SC, Eom ia from LoD +SCeg, oa = Display data - ELECTRONICS M@ 7964242 0021984 923

KS0083/84 CMOS DIGITAL INTEGRATED CIRCUIT APPLICATION CIRCUIT -5V 2 -5V | »10 83 BB tied ath | pnok z ono] | a a [= - ee g ead | [TT Yss5 3 Caan mn a i LS 8uncl bree eon] | ||| a : | . sa084 i088 + ' eo: of | ono ey f¥ a 3 z se Peeaosy] f= vereaoosy ning HS Lit Uti Seyg akes BE 3 é 5 = 288s SECTRONS 7964142 0021985 SLT om

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