KS0070

KS0070B SAMSUNG | Alldatasheet

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KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INTRODUCTION KS0070B is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It is capable of displaying 1 or 2 lines with the 5 × 7 format or 1 line with the 5 × 10 dots format. FUNCTIONS

• Character type dot matrix LCD driver & controller
• Internal driver: 16 common and 8 0 segment signal output
• Easy interface with 4-bit or 8-bit MPU
• Display character pattern: 5 × 7 dots format (192 kinds) & 5 × 10 dots format (32 kinds)
• The special character pattern is directly programmable by the character generator RAM.
• A customer character pattern is programmable by mask option.
• It can drive a maximum of 80 characters by using the KS0065B or KS0063B externally.
• Various instruction functions
• Built-in automatic power on reset
• Driving method is A-type (Line inversion)

FEATURES

• Internal Memory - Character Generator ROM (CGROM): 8,320 bits ( 192 characters × 5 × 7 dot s ) & (32 characters x 5 × 10 dots) - Character Generator RAM (CGRAM): 64 × 8 bits (8 characters × 5 × 7 dot s ) - Display Data RAM (DDRAM): 80 × 8 bits (80 characters max.)
• Low power operation - Power supply voltage range: 2.7 to 5.5 V (VDD) - LCD Drive voltage range: 3.0 to 1 0 .0 V (VDD to V5)
• Supply voltage for display: 0 to −5 V (V5)
• Programmable duty cycle: 1/ 8 , 1/ 11, 1/16
• Internal oscillator with an external resisto r
• B are chip or bumped chip available

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD BLOCK DIAGRAM Parallel to serial Data conversion circuit Character Generator ROM (CG ROM) 8320 bits Character Generator RAM (CG RAM) 512 bits Cursor Blink Control Circuit Busy Flag Data Register (DR) Instruction Register (IR) Instruction Decoder (ID) Display Data RAM (DD RAM) 640 bits Input Output Buffer 888 8 8 80 bit shift Register 80 bit Latch Circuit Segment Driver Address Counter (AC) 8 7 VDD GND DB0-DB3 DB4-DB7 R/W RS E SEG1- SET80 D 16 bit Shift Register 16-bit common Driver7 Timing Generation Circuit OSC2 OSC1

16 COM1-

M

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PIN CONFIGURATION 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 100 101 102 KS0070B NC TEST DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD E R/W RS D M CLK2 CLK1 NC NC NC SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 NC SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 V SS OSC2 OSC1 NC SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 NC

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD CONFIGURATION 1) NORMAL TYPE PAD CONFIGURATION 1 0 3 S E G 5 9 1 0 4 S E G 5 8 1 0 5 S E G 5 7 1 0 6 S E G 5 6 1 0 7 S E G 5 5 1 0 8 S E G 5 4 1 0 9 S E G 5 3 1 1 0 S E G 5 2 1 1 1 S E G 5 1 1 1 2 S E G 5 0 1 1 3 S E G 4 9 1 1 4 S E G 4 8 1 1 5 S E G 4 7 1 1 6 S E G 4 6 1 1 7 S E G 4 5 1 1 8 S E G 4 4 1 1 9 S E G 4 3 1 2 0 S E G 4 2 1 2 1 S E G 4 1 1 2 2 S E G 4 0 1 2 3 S E G 3 9 1 2 4 S E G 3 8 1 2 5 S E G 3 7 1 2 6 S E G 3 6 1 2 7 S E G 3 5 1 2 8 S E G 3 4

70 COM 5

71 COM 6

72 COM 7

73 COM 8

74 COM9

75 COM1 0

76 COM1 1

77 COM 12

78 COM 13

79 COM 14

80 COM 1 5

81 COM 16

82 SEG80

83 SEG79

84 SEG78

85 SEG77

89 SEG 7 3

90 SEG 72

99 SEG 63

100 SEG 62

101 SEG 61

67 COM2

68 COM3

69 COM4

Y X(0, 0) CHIP SIZE: 3920 × 5070 PAD SIZE: 100 × 100 UNIT: µm 8 7 SEG75 SEG33 2 OSC2 36 OSC1 37

66 COM1

86 SEG76

102 SEG60

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) MIRROR TYPE PAD CONFIGURATION 1 0 3 S E G 3 4 1 0 4 S E G 3 5 1 0 5 S E G 3 6 1 0 6 S E G 3 7 1 0 7 S E G 3 8 1 0 8 S E G 3 9 1 0 9 S E G 4 0 1 1 0 S E G 4 1 1 1 1 S E G 4 2 1 1 2 S E G 4 3 1 1 3 S E G 4 4 1 1 4 S E G 4 5 1 1 5 S E G 4 6 1 1 6 S E G 4 7 1 1 7 S E G 4 8 1 1 8 S E G 4 9 1 1 9 S E G 5 0 1 2 0 S E G 5 1 1 2 1 S E G 5 2 1 2 2 S E G 5 3 1 2 3 S E G 5 4 1 2 4 S E G 5 5 1 2 5 S E G 5 6 1 2 6 S E G 5 7 1 2 7 S E G 5 8 1 2 8 S E G 5 9

70 SEG1

71 SEG2

72 SEG3

73 SEG4

74 SEG5

75 SEG6

76 SEG7

77 SEG8

78 SEG9

79 SEG10

80 SEG11

81 SEG12

82 SEG13

83 SEG14

84 SEG15

85 SEG16

88 SEG19

89 SEG20

90 SEG21

91 SEG22

92 SEG23

93 SEG24

94 SEG25

95 SEG26

96 SEG27

97 SEG28

98 SEG29

99 SEG30

100 SEG31

101 SEG32

67 OSC1

68 OSC2

69 VSS

Y X(0, 0) CHIP SIZE: 3920 × 5070 PAD SIZE: 100 × 100 UNIT: µm

87 SEG18

86 SEG17

102 SEG33

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD COORDINATE 1) NORMAL TYPE PAD COORDINATE PAD NO . PAD NAME COORDINATE PAD NO . PAD NAME COORDINATE PAD NO PAD NAME COORDINATE PAD NO . PAD NAME COORDINATE X Y X Y X Y X Y

1 NC - - 24 SEG11 -1794 -581 47 CLK1 - 530 -2 369 70 COM 5 1794 - 1831

2 SEG 33 -1794 2 169 25 SEG10 -1794 - 706 48 CLK2 -405 -2369 71 COM 6 1794 -1 706

3 SEG 32 -1794 2 044 26 SEG9 -1794 - 831 49 M -280 -2369 72 COM 7 1794 -1 581

4 SEG 31 -1794 1 919 27 SEG8 -1794 - 956 50 D -155 -2369 73 COM 8 1794 - 1456

5 SEG 30 -1794 1 794 28 SEG7 -1794 -1 081 51 RS -30 -2369 74 COM9 1794 -1 331

6 SEG 2 9 -1794 1 669 29 SEG6 -1794 -1 206 52 RW 95 -2369 75 COM1 0 1794 - 1206

7 SEG 28 -1794 1544 30 SEG5 -1794 -1 331 53 E 220 -2369 76 COM 11 1794 - 1081

8 SEG 27 -1794 1419 31 SEG4 -1794 -1 456 54 VDD 345 -2369 77 COM 12 1794 - 956

9 SEG 26 -1794 1294 32 SEG3 -1794 -1 581 55 DB0 470 -2369 78 CO M13 1794 - 831

10 SEG 25 -1794 1169 33 SEG2 -1794 -1 706 56 DB1 595 -2369 79 COM 14 1794 - 706

11 SEG 2 4 -1794 1044 34 SEG1 -1794 -1 831 57 DB2 720 -2369 80 CO M1 5 1794 - 581

12 SEG 23 -1794 919 35 VSS -1794 -1 956 58 DB3 845 -2369 81 COM 16 1794 - 456

13 SEG 22 -1794 794 36 OSC2 -1794 -2 106 59 DB4 970 -2369 82 SEG80 1794 - 331

14 SEG 21 -1794 669 37 OSC1 -1794 -2 231 60 DB5 1095 -2369 83 SEG79 1794 - 20 6

15 SEG 20 -1794 544 38 NC - - 61 DB6 1220 -2369 84 SEG78 1794 -81

16 SEG 1 9 -1794 419 39 NC - - 62 DB7 1345 -2369 85 SEG77 1794 44

17 SEG 18 -1794 294 40 NC - - 63 TEST 1470 -2369 86 SEG 76 1794 169

18 SEG17 -1794 169 41 NC - - 64 NC - - 87 SEG 75 1794 294

19 SEG16 -1794 44 42 V1 -1 155 -2 369 65 NC - - 88 SEG 74 1794 419

20 SEG15 -1794 -81 43 V2 - 1030 -2 369 66 COM1 1794 -2331 89 SEG 73 1794 544

21 SEG14 -1794 -206 44 V3 -9 05 -2369 67 COM2 1794 - 2206 90 SEG 72 1794 669

22 SEG13 -1794 -331 45 V4 - 780 -2369 68 COM3 1794 - 2081 91 SEG 71 1794 794

23 SEG12 -1794 -456 46 V5 - 655 -2369 69 COM4 1794 - 1956 92 SEG7 0 1794 919

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD NO. PAD NAME COORDINATE PAD NO. PAD NAME COORDINATE PAD NO. PAD NAME COORDINATE PAD NO. PAD NAME COORDINATE X Y X Y X Y X- Y-

93 SEG69 1794 1044 102 SEG60 1794 2169 111 SEG51 563 2369 120 SEG42 -562 2369

94 SEG68 1794 1169 103 SEG59 1563 2369 112 SEG50 438 2369 121 SEG41 -687 2369

95 SEG67 1794 1294 104 SEG58 1438 2369 113 SEG49 313 2369 122 SEG40 -812 2319

96 SEG66 1794 1419 105 SEG57 1313 2369 114 SEG48 188 2369 123 SEG39 -937 2369

97 SEG65 1794 1544 106 SEG56 1188 2369 115 SEG47 63 2369 124 SEG38 -1062 2369

98 SEG64 1794 1669 107 SEG55 1063 2369 116 SEG46 -62 2369 125 SEG37 -1187 2369

99 SEG63 1794 1794 108 SEG54 938 2369 117 SEG45 -187 2369 127 SEG36 -1312 2369

100 SEG62 1794 1919 109 SEG53 813 2369 118 SEG44 -312 2369 127 SEG35 -1437 2369

101 SEG61 1794 2044 110 SEG52 688 2369 119 SEG43 -437 2369 128 SEG34 -1562 2369

NORMAL TYPE PAD COORDINATE (CONTINUED)

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) MIRROR TYPE PAD COORDINATE PAD NO . PAD NAME COORDINATE PAD NO . PAD NAME COORDINATE PAD NO PAD NAME COORDINATE PAD NO . PAD NAME COORDINATE X Y X Y X Y X Y

1 NC - - 24 COM15 -1794 -581 47 DB2 -720 -2 369 70 SEG1 1794 - 1831

2 SEG60 -1794 2 169 25 COM14 -1794 - 706 48 DB1 -595 -2369 71 SEG2 1794 -1 706

3 SEG61 -1794 2 044 26 COM13 -1794 -831 49 DB0 -470 -2369 72 SEG3 1794 -1 581

4 SEG62 -1794 1 919 27 COM12 -1794 -956 50 VDD -345 -2369 73 SEG4 1794 - 1456

5 SEG63 -1794 1 794 28 COM11 -1794 -1081 51 E -220 -2369 74 SEG5 1794 -1 331

6 SEG64 -1794 1 669 29 COM10 -1794 -1206 52 RW -95 -2369 75 SEG6 1794 - 1206

7 SEG65 -1794 1544 30 COM9 -1794 -1331 53 RS 30 -2369 76 SEG7 1794 - 1081

8 SEG66 -1794 1419 31 COM8 -1794 -1456 54 D 155 -2369 77 SEG8 1794 - 956

9 SEG67 -1794 1294 32 COM7 -1794 -1 581 55 M 280 -2369 78 SEG9 1794 - 831

10 SEG68 -1794 1169 33 COM6 -1794 -1 706 56 CLK2 405 -2369 79 SEG10 1794 - 706

11 SEG69 -1794 1044 34 COM5 -1794 -1 831 57 CLK1 530 -2369 80 SEG11 1794 - 581

12 SEG70 -1794 919 35 COM4 -1794 -1 956 58 V5 655 -2369 81 SEG12 1794 - 456

13 SEG71 -1794 794 36 COM3 -1794 -2081 59 V4 780 -2369 82 SEG13 1794 - 331

14 SEG72 -1794 669 37 COM2 -1794 -2206 60 V3 905 -2369 83 SEG14 1794 - 20 6

15 SEG73 -1794 544 38 COM1 -1794 -2331 61 V2 1030 -2369 84 SEG15 1794 -81

16 SEG74 -1794 419 39 NC - - 62 V1 1155 -2369 85 SEG16 1794 44

17 SEG75 -1794 294 40 NC - - 63 NC - - 86 SEG17 1794 169

18 SEG76 -1794 169 41 TEST -1470 -2369 64 NC - - 87 SEG18 1794 294

19 SEG77 -1794 44 42 DB7 -1345 -2 369 65 NC - - 88 SEG19 1794 419

20 SEG78 -1794 -81 43 DB6 -1220 -2 369 66 NC - - 89 SEG20 1794 544

21 SEG79 -1794 -206 44 DB5 -1095 -2369 67 OSC1 1794 -2231 90 SEG21 1794 669

22 SEG80 -1794 -331 45 DB4 -970 -2369 68 OSC2 1794 -2106 91 SEG22 1794 794

23 COM16 -1794 -456 46 DB3 -845 -2369 69 VSS 1794 - 1956 92 SEG23 1794 919

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD NO. PAD NAME COORDINATE PAD NO. PAD NAME COORDINATE PAD NO. PAD NAME COORDINATE PAD NO. PAD NAME COORDINATE X Y X Y X Y X Y

93 SEG24 1794 1044 102 SEG33 1794 2169 111 SEG42 562 2369 120 SEG51 -563 2369

94 SEG25 1794 1169 103 SEG34 1562 2369 112 SEG43 437 2369 121 SEG52 -688 2369

95 SEG26 1794 1294 104 SEG35 1437 2369 113 SEG44 312 2369 122 SEG53 -813 2369

96 SEG27 1794 1419 105 SEG36 1312 2369 114 SEG45 187 2369 123 SEG54 -938 2369

97 SEG28 1794 1544 106 SEG37 1187 2369 115 SEG46 62 2369 124 SEG55 -1063 2369

98 SEG29 1794 1669 107 SEG38 1062 2369 116 SEG47 -63 2369 125 SEG56 -1188 2369

99 SEG30 1794 1794 108 SEG39 937 2369 117 SEG48 -188 2369 127 SEG57 -1313 2369

100 SEG31 1794 1919 109 SEG40 812 2369 118 SEG49 -313 2369 127 SEG58 -1438 2369

101 SEG32 1794 2044 110 SEG41 687 2369 119 SEG50 -438 2369 128 SEG59 -1563 2369

MIRROR TYPE PAD COORDINATE (CONTINUED)

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD DESCRIPTION Pad No. (Normal/Mirror) Input/ Output Name Description Interface VDD (54/50) - Power supply For logical circuit (+3 V, + 5 V) Power Supply VSS(35, 69) 0 V (GND) V1 ~ V5 (42~46/62~58) Bias voltage level for LCD driving. SEG1 ~ SEG80 (34~2, 128~82/ 70~128, 2~22) Output Segment output Segment signal output for LCD drive. LCD COM 1 ~ COM 16 ( 66 ~ 81/38 ~ 23 ) Output Common output Common signal output for LCD drive. LCD OSC1,OSC2 (37,36 /67,68 ) Input (OSC1) / Output (OSC2) Oscillator When using internal oscillator, connect external Rf resistor. If external clock is used, connect it to OSC1. External resistor/ oscillator (OSC1) CLK1,CLK2 ( 47 ,48/57,56 ) Out put Extension driver Latch (CLK1) /Shift (CLK2) clock E ach outputs extension driver latch clock and extension driver shift clock. Extension driver M (4 9/55 ) Output Alternated signal for LCD driver output Outputs the alternating signal to convert LCD driver waveform to AC. Extension driver D ( 5 0 /54 ) Output Display data interface Output extension driver data (the 4 1st dot's data) Extension driver RS (51/53) Input Register select Used as register selection input. When RS = "1", Data register is selected. When RS = "0", Instruction register is selected. MPU RW (52/52) Input Read/Write Used as read/write selection input. When RW = "1", read operation. When RW = "0", write operation. MPU E (53/51) Input Read/Write enable Used as read. Write enable signal. MPU DB0~DB3 (55~58/49~46) Input Output Data bus 0~7 When 8-bit bus mode, used as low order bidirectional data bus. During 4-bit bus mode open these pins. MPU DB4~DB7 (59~62/45~42) When 8-bit bus mode, used as high order bidirectional data bus. In case of 4-bit bus mode, used as both high and low order. DB7 used for Busy Flag output. MPU TEST (63/41) Input Test Pin This pin must be fixed to VDD or open. –

This chip has both kinds of interface type with MPU: 4-bit bus and 8-bit bus. 4-bit bus and 8-bit bus are selected by the DL bit in the instruction register. ing into RAM, is done automatically. After MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. To select a register, use RS input pin in 4-bit/8-bit bus mode. Table 1. Various Kinds of Operations According to RS and R/W bits. (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not "1".

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Address Counter (AC) The Address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "0" and R/W = "1", AC can be read through ports DB0~DB6. Display Data RAM (DDRAM) DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. (Refer to Fig-1.) Fig-1. DDRAM Address 1) 1-line display In the case of a 1-line display, the address range of DDRAM is 00H ~ 4FH. An Extension driver will be used. Fig-2 shows the example when a 40-segment extension driver is added. 2) 2-line display In the case of a 2-line display, the address range of DDRAM is 00H ~27H and 40H ~ 67H. An Extension driver will be used. Fig-3 shows the example when a 40 segment extension driver is added. AC6 AC5 AC4 AC3 AC2 AC1 AC0 MSB LSB

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Fig-2. 1-line ´ 24ch. Display With 40 SEG. Extension Driver. Fig-3. 2-line ´ 24ch. Display With 40 SEG. Extension Driver. 17 18 19 20 21 22 23 24 10 11 12 13 14 15 16 17 17 18 19 20 21 22 23 24 11 12 13 14 15 16 17 18 17 18 19 20 21 22 23 24 0F 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D OE OF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E COM1 COM8 SEG1 KS007 0B SEG 8 0 COM1 COM8 COM8 SEG1 (After Shift Left) (After Shift Right) COM1 KS007 0B SEG1 KS007 0B SEG1 SEG80 Extension Driver (40SEG) SEG40 SEG1 Extension Driver (40SEG) SEG40 SEG1 Extension Driver (40SEG) SEG40 17 18 19 20 21 22 23 24 10 11 12 13 14 15 16 17 50 51 52 53 54 55 56 57 17 18 19 20 21 22 23 24 11 12 13 14 15 16 17 18 51 52 53 54 55 56 57 58 17 18 19 20 21 22 23 24 0F 10 11 12 13 14 15 16 4F 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D OE OF 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E COM1 COM8 COM1 COM8 COM10 (After Shift Left) COM9 KS007 0B SEG1 KS007 0B SEG1 SEG80 SEG1 Extension Driver (40SEG) SEG40 SEG1 Extension Driver (40SEG) SEG40 COM1 COM8 SEG80 SEG1 KS007 0B SEG80 (After Shift Right) COM1 COM8 COM9 COM10 SEG1 Extension Driver (40SEG) SEG40

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD CGROM (Character Generator ROM) CGROM has a 5 × 7-dot 192 character pattern, and a 5 × 10-dot 32 character pattern (Refer to Table 2). CGRAM (Character Generator RAM) CGRAM has up to 5 × 8-dot 8 characters. By writing font data to CGRAM, user defined characters can be used (Refer to Table 3). Timing Generation Circuit Timing generation circuit generates clock signals for the internal operations. LCD Driver Circuit LCD Driver circuit has 16 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to an 80-bit segment latch serially, and then stored to an 80-bit shift latch. When each com is selected by a 16-bit common register, segment data is also output through the segment driver from an 80-bit segment latch. In the case of a 1-line display mode, COM1 ~ COM8 have 1/8 duty or COM1 ~ COM11 have a 1/11 duty. In a 2-line display mode, COM1 ~ COM16 have a 1/16 duty ratio. Cursor/Blink Control Circuit It controls cursor/blink ON/OFF at cursor position.

Table 2. CGROM Character Code Table

Table 3. Relationship Between Character Code (DDRAM) and Character Pattern (CGRAM)

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INSTRUCTION DESCRIPTION Outline To overcome the speed difference between the internal clock of KS0070B and the MPU clock, KS0070B performs internal operations by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus (Refer to Table 5 ). Instruction can be divided largely into four kinds: (1) KS0070B function set instructions ( set display methods, set data length, etc.) (2) address set instructions to internal RAM (3) data transfer instructions with internal RAM (4) others . The address of the internal RAM is automatically increased or decreased by 1. * NOTE: During internal operation, Busy Flag (DB7) is read "1". Busy Flag check must be preceded by the next instruction. When you make an MPU program with checking the Busy Flag (DB7), it must be necessary 1/2 Fosc for executing the next instruction by falling E signal after the Busy Flag (DB7) goes to "0".

Contents

1) Clear Display Clear all the display data by writing "20H" (space code) to all DDRAM addresses, and set the DDRAM addresses to "00H" in the AC (address counter). Return cursor to original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). 2) Return Home Return Home is the cursor return home instruction. Set DDRAM address to "00H" in the address counter. Return cursor to its original site and return display to its orig- inal status, if shifted. Contents of DDRAM does not change. 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 × RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 3) Entry Mode Set Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = “1”, cursor/blink moves to right and DDRAM address is increased by 1. When I/D = “0”, cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when reading from or writing to CGRAM. SH: Shift of entire display When DDRAM is in read (CGRAM read/write) operation or SH = “0”, shift of entire display is not performed. If SH = “1” and in DDRAM write operation, shift of entire display is performed according to I/D value (I/D = “1” : shift left, I/D = “0” : shift right). 4) Display ON/OFF Control Control display/cursor/blink ON/OFF 1-bit register. D : Display ON/OFF control bit When D = “1”, entire display is turned on. When D = “0”, display is turned off, but display data remains in DDRAM. C : Cursor ON/OFF control bit When C = “1”, cursor is turned on. When C = “0”, cursor disappears in current display, but I/D register retains its data. B : Cursor Blink ON/OFF control bit When B = “1”, cursor blink is on, which performs alternately between all the “1” data and display characters at the cursor position. When B = “0”, blink is off. 0 0 0 0 0 0 0 1 I/D SH 0 0 0 0 0 0 1 D C B RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Without writing or reading the display data, shift right/left cursor position or display. During 2-line mode display, cursor moves to the 2nd line after the 40st digit of the 1st line. Note that display shift is performed simultaneously in all the lines. When displayed data is shifted repeatedly, each line shifts individually. When display shift is performed, the contents of the address counter are not changed. Table 4. Shift Patterns According to S/C and R/L bits When DL = “1”, it means 8-bit bus mode with MPU. When 4-bit bus mode, it needs to transfer 4-bit data in two parts. When N = “0”, it means 1-line display mode. When N = “1”, 2-line display mode is set. When F = “1”, 5 × 10 dots format display mode.

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 7) Set CGRAM Address Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. 8) Set DDRAM Address Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When in 1-line display mode (N = 0), DDRAM address is from “00H” to “4FH”. In 2-line display mode (N = 1), DDRAM address in the 1st line is from “00H” to “27H”, and DDRAM address in the 2nd line is from “40H” to “67H”. 9) Read Busy Flag & Address This instruction shows whether KS0070B is in internal operation or not. If the resultant BF is “1”, it means the internal operation is in progress and you have to wait until BF is Low. Then the next instruction can be performed. In this instruction you can also read the value of the address counter. 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 10) Write data to RAM Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction : DDRAM address set, and CGRAM address set. RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. 11) Read data from RAM Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not performed before this instruction, the data that is read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In the case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction; It also transfers RAM data to the output data register. After read operation the address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. * In the case of RAM write operation, after this AC is increased/decreased by 1 like read operation. At this time, AC indicates the next address position, but you can read only the previous data by the read instruction. 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Table 5. Instruction Table for executing the next instruction by falling E signal after the Busy Flag (DB7) goes to “0”.

Description

(fosc = 270 kHz) RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display 0 0 0 0 0 0 0 0 0 1 Write “ 20H ” to DDRAM and set DDRAM address to “ 00H ” from AC. 1.53 ms Return Home 0 0 0 0 0 0 0 0 1 × Set DDRAM address to “ 00H ” from AC and return cursor to its original position if shifted. 1.53 ms Entry Mode Set 0 0 0 0 0 0 0 1 I/D SH Assign cursor moving direction and enable the shift of entire display . 39 µs Display ON/ OFF Control 0 0 0 0 0 0 1 D C B Set display (D), cursor (C), and blinking of cursor (B) on/off control bit. 39 µs Cursor or Display Shift 0 0 0 0 0 1 S/C R/L × × Set cursor moving and display shift control bit, and the direction, without changing of DDRAM data. 39 µs Function Set 0 0 0 0 1 DL N F × × Set interface data length (DL : 4-bit/8- bit), numbers of display line (N : 1-line/ 2-line, Display font type (F:0 ...) 39 µs Set CGRAM Address 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 39 µs Set DDRAM Address 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39 µs Read Busy flag and Address 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Whether during internal operation or not can be known by reading BF. The contents of address counter can also be read. 0 µs Write Data to RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM (DDRAM/CGRAM). 43 µs Read Data from RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM (DDRAM/CGRAM). 43 µs

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INTERFACE WITH MPU 1) Interface with 8-bit MPU When interfacing data length are 8-bit, transfer is performed all at once through 8 ports, from DB0 to DB7. An Example of the timing sequence is shown below. Fig-4. Example of 8-bit Bus Mode Timing Diagram 2) Interface with 4-bit MPU When interfacing data length are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first, higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then the lower 4-bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed in two parts. Busy Flag outputs “1” after the second transfer are ended. Example of timing sequence is shown below. Fig-5. Example of 4-bit Bus Mode Timing Diagram R S R / W E D B 7 I n t e rn a l s ig n a l B u s y B u s yD A T A D A T A I n t e rn a l o p e r a tio n B u s y F la g C h e c k B u s y F la g C h e c k B u s y F la g C h e c kIN S T R U C T IO N IN S T R U C T IO N N o B u s y R S R /W E D B 7 In te rn a l s ig n a l B u s y In te rn a l o p e ra tio n B u s y F la g C h e c k B u s y F la g C h e c kIN S T R U C T IO N IN S T R U C T IO N N o B u s y D 3D 7A C 3A C 3D 3D 7

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD APPLICATION INFORMATION ACCORDING TO LCD PANEL 1) LCD Panel: 16 characters × 1-line format ( 5 × 7 dots + 1 cursor line 1/4 bias, 1/8 duty) 2) LCD Panel: 16 characters × 1-line format (5 × 10 dots + 1 cursor line 1/4 bias, 1/11 duty) KS0070B COM1 COM7 COM8 . . . SEG1 SEG10 SEG78 SEG80 . . . SEG79 ... KS0070B COM1 COM10 COM11 . . . SEG1 SEG10 SEG78 SEG80 . . . SEG79 ...

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 3) LCD Panel : 16 character × 2-line format: (5 × 7 dots + 1 cursor line 1/5 bias, 1/16 duty) 4) LCD Panel : 32 character × 1-line format: ( 5 × 7 dots + 1 cursor line 1/5 bias, 1/16 duty) KS0070B COM7 COM8 . . . SEG1 SEG10 SEG80 COM1 COM15 COM16 . . . COM9 COM7 COM8 . . . COM1 SEG1 SEG10 SEG80 COM16 . . . COM9 KS0070B

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 5) LCD Panel : 8 character × 2-line format: ( 5 × 7 dots + 1 cursor line 1/4 bias, 1/8 duty) KS0070B COM7 COM8 . . . COM1 SEG1 SEG10 SEG40 . . . SEG41 SEG50 SEG80

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD APPLICATION CIRCUIT GND or Other voltageTo MPU LCD Panel KS0070B SC1 − SC40 DL1 FCS SHL1 SHL2 VSS VDD DL2 DL1 DR2 CL1 CL2 M V E E V V V V V V SC1 − SC40 V E E V V V V V V SC1 − SC40 V E E V V V V V V DL2 DL1 DR2 CL1 CL2 M DL1 M DL2 DR2 CL1 CL2 DL1 FCS SHL1 SHL2 VSS VDD DL1 FCS SHL1 SHL2 VSS VDD VDD S1 − S80 C1 − C16 D VSS M CLK1 CLK2 VDD DB0 − DB7 OSC1 OSC2 K S 0 0 6 5 B K S 0 0 6 5 B K S 0 0 6 5 B V L C D ( 1 /5 b ia s ) * When KS0065B is externally connected to the KS0070B, you can increase the number of display digits up to 80 characters

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD BIAS VOLTAGE DIVIDE CIRCUIT INITIALIZING When the power is turned on, KS0070B is initialized automatically by the power on reset circuit. During the initialization, the following instructions are executed, and BF(Busy Flag) is kept “1”(busy state) to the end of initialization. (1) Display Clear instruction Write “20H” to all DDRAM (2) Set Functions instruction DL = 1 : 8-bit bus mode N = 0 : 1-line display mode F = 0 : 5 × 7 font type (3) Control Display ON/OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF (4) Set Entry Mode instruction I/D = 1 : Increment by 1 SH = 0 : No entire display shift 1) 1/4 bias, 1/8 OR 1/11 duty 2) 1/5 bias, 1/16 OR 1/11 duty VDD KS0070B VDD R R R R GND OR OTHER VOLTAGE VDD KS0070B VDD R R R R GND OR OTHER VOLTAGE R

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD FRAME FREQUENCY 1) 1/8 duty cycle A) A-type Waveform Item Clock / Frequency Line selection period 400 clocks Frame frequency 84.4 Hz 1 2 3 4 7 8 1 2 3 7 8 VDD 1-line selection period COM1 . . . * fosc=270 kHz (1 clock = 3.7 µs)

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) 1/11 duty cycle A) A-type Waveform 3) 1/16 duty cycle A) A-type Waveform Item Clock / Frequency Line selection period 400 clocks Frame frequency 61.4 Hz Item Clock / Frequency Line selection period 200 clocks Frame frequency 84.4 Hz 1 2 3 4 10 11 1 2 3 10 11 VDD 1-line selection period COM1 . . . * fosc=270 kHz (1 clock = 3.7 µs) 1 2 3 4 15 16 1 2 3 15 16 VDD 1-line selection period COM1 . . . * fosc=270 kHz (1 clock = 3.7 µs)

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INITIALIZING BY INSTRUCTION 1) 8-bit interface mode Power on Wait for more than 30 ms after VDD rises to 4.5 v Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N F × × Wait for more than 39 µs Display ON/OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C B Wait for more than 39 µs Clear Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 Wait for more than 1.53 ms Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D SH Initialization end N 0 1 - line mode 1 2 - line mode F 0 5 × 7 dots 1 5 × 10 dots D 0 display off 1 display on C 0 cursor off 1 cursor on B 0 blink off 1 blink on I/D 0 decrement mode 1 increment mode S H 0 entire shift off 1 entire shift on Condition: fosc=270 kHz

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) 4-bit interface mode Power on Wait for more than 30 ms after Vdd rises to 4.5 v Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 X X X X 0 0 0 0 1 0 X X X X 0 0 N F X X X X X X Wait for more than 39 µs Display On/Off Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 1 D C B X X X X Wait for more than 39 µs Clear Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 0 0 0 1 X X X X Wait for more than 1.53 ms Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 0 1 I/D SH X X X X Initialization end N 0 1 - line mode 1 2-line mode F 0 5 × 7 Dots 1 5 × 10 Dots D 0 display off 1 display on C 0 cursor off 1 cursor on B 0 blink off 1 blink on I/D 0 decrement mode 1 increment mode SH 0 entire shift off 1 entire shift on Condition: fosc=270 kHz

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD EXAMPLE OF INSTRUCTION AND DISPL A Y CORRESPONDENCE 1. Power supply on: Initialized by the internal power on reset circuit . RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LCD DISPLAY 2. Function Set: 8-bit, 2-line, 5 × 7 dot RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 0 X X 3. Display ON/OFF Control: Display/Cursor on /Blink off RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 1 1 0 _ 4. Entry Mode Set: Increment RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 1 0 _ 5. Write Data to DDRAM: Write S RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 1 0 0 1 1 S_ 6. Write Data to DDRAM: Write A RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 0 0 0 0 1 SA_ 7. Write Data to DDRAM: Write M RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 0 1 1 0 1 SAM_ 8. Write Data to DDRAM: Write S RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 1 0 0 1 1 SAMS_

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 9. Write Data to DDRAM: Write U RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 1 0 1 0 1 SAMSU_ 10. Write Data to DDRAM: Write N RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 0 1 1 1 0 SAMSUN_ 11. Write Data to DDRAM: Write G RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 0 0 1 1 1 SAMSUNG_ 12. Set DDRAM Address: 40H RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 0 0 0 0 SAMSUNG 13. Write Data to DDRAM: Write K RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 0 1 0 1 1 SAMSUNG 14. Write Data to DDRAM: Write S RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 1 0 0 1 1 SAMSUNG KS_ 15. Write Data to DDRAM: Write 0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 1 1 0 0 0 0 SAMSUNG KS0_ 16. Write Data to DDRAM: Write 0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 1 1 0 0 0 0 SAMSUNG KS00_

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 17. Write Data to DDRAM: Write 7 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 1 1 0 1 1 1 SAMSUNG KS007_ 18. Write Data to DDRAM: Write 2 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 1 1 0 0 1 0 SAMSUNG KS0072_ 19. Cursor or Display Shift: Cursor shift left RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 0 X X SAMSUNG KS007 2 20. Write Data to DDRAM: Write 0 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 1 1 0 0 0 0 SAMSUNG KS0070_ 21. Entry Mode Set: Ent ir e Display shift Enable RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 1 1 SAMSUNG KS0070_ 22. Write Data to DDRAM: Write B RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 0 0 0 0 1 0 AMSUNG S0070B_ 23. Return Home RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 × S AMSUNG KS0070B 24. Clear Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD MAXIMUM ABSOLUTE RATE Maximum Absolute Power Ratings * NOTE: Voltage greater than above may damage the circuit (VDD > V1 > V2 > V3 > V4 > V5) Temperature Characteristics Item Symbol Unit Value Power supply voltage(1) V DD V -0.3 to + 7.0 Power supply voltage(2) V LCD V VDD -15.0 to V DD + 0.3 Input voltage V IN V -0.3 to V DD + 0.3 Item Symbol Unit Value Operating temperature Topr °C -30 to + 85 Storage temperature Tstg °C -55 to + 125

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ELECTRICAL CHARACTERISTICS

Item Symbol Condition Min Typ Max Unit Operating Voltage V DD - 4.5 - 5.5 V Supply Current IDD1 ceramic resonator fosc = 250 kHz 0.7 1.0 mA IDD 2 Resistor oscillation external clock operation fosc = 270 kHz - 0.4 0.6 Input Voltage (1) (except OSC1) V IH1 - 2.2 - V DD V V IL1 - -0.3 - 0.6 Input Voltage ( 2 ) (OSC1) V IH 2 - V DD -1.0 - V DD V Output Voltage (1) (DB0 to DB7) V OH1 IOH = -0. 205 mA 2.4 - - V V OL1 IOL = 1.2 µA - - 0.4 Output Voltage (2) (except DB0 to DB7) V OH2 IO = -40 µA 0. 9 V DD - - V V OL2 IO = 40 µA - - 0. 1 V DD Voltage Drop Vd COM IO = + 0.1 mA - - 1 V Vd SEG - - 1 Input Leakage Current IIL V IN = 0 V to V DD -1 - 1 µA Low Input Current IIN V IN = 0 V, V DD = 5 V (PULL UP) - 5 0 -125 -250 Internal Clock (external Rf) fIC Rf = 91 k Ω + 2% (V DD = 5 V) 190 270 350 kHz External Clock fEC 150 2 5 0 350 kHz duty 45 50 55 % tr, tf - - 0.2 µs LCD Driving Voltage V LCD V DD -V 5 (1/5, 1/4 Bias) 4.6 - 10.0 V (V DD = 4.5V to 5.5V, Ta = -30 to +85 °C)

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD * LCD Driving Voltage (next page) Item Symbol Condition Min Typ Max Unit Operating Voltage V DD - 2.7 - 4.5 V Supply Current IDD1 ceramic resonator fosc = 250 kHz - 0.3 0.5 mA IDD2 Resistor oscillation external clock operation fosc = 270 kHz - 0.17 0.3 Input Voltage (1) (except OSC1) V IH1 - 0.7V DD - V DD V V IL1 - -0.3 - 0.4 Input Voltage ( 2 ) (OSC1) V IH2 - 0.7V DD - V DD V V IL2 - - 0.2V DD Output Voltage (1) (DB0 to DB7) V OH1 IOH = -0.1 mA 2.0 - - V V OL1 IOL = 0.1 mA - - 0.4 Output Voltage (2) (except DB0 to DB7) V OH2 IO = -40 µA 0.8V DD - - V V OL2 IO = 40 µA - - 0.2V DD Voltage Drop Vd COM IO = + 0.1 mA - - 1 V Vd SEG - - 1.5 Input Leakage Current IIL V IN = 0 V to V DD -1 - 1 µA Low Input Current IIN V IN = 0 V, V DD = 3 V (PULL UP) -10 -50 -120 Internal Clock (external Rf) fIC Rf = 75 k Ω + 2% (V DD = 3 V) 190 250 350 kHz External Clock fEC 125 270 350 kHz duty 45 50 55 % tr, tf - - 0.2 µs * LCD Driving Voltage V LCD V DD -V 5 (1/5, 1/4 Bias) 3.0 - 10.0 V

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD * LCD Driving Voltage POWER DUTY 1/8, 1/11 DUTY 1/16 DUTY BIAS 1/4 BIAS 1/5 BIAS V DD V DD V DD V1 V DD - V LCD /4 V DD - V LCD /5 V2 V DD - V LCD /2 V DD - 2V LCD /5 V3 V DD - V LCD /2 V DD - 3V LCD /5 V4 V DD - 3V LCD /4 V DD - 4V LCD /5 V5 V DD - V LCD V DD - V LCD

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD AC Characteristics Mode Item Symbol Min Typ Max Unit Write Mode (Refer to Fig- 6 ) E Cycle Time tc 500 - - ns E Rise / Fall Time tr,tf - - 2 5 E Pulse Width (High, Low) tw 2 2 0 - - R/W and RS Setup Time tsu1 40 - - R/W and RS Hold Time th1 10 - - Data Setup Time tsu2 6 0 - - Data Hold Time th2 10 - - Read Mode (Refer to Fig- 7 ) E Cycle Time tc 500 - - ns E Rise / Fall Time tr,tf - - 2 5 E Pulse Width (High, Low) tw 2 20 - - R/W and RS Setup Time tsu 40 - - R/W and RS Hold Time th 10 - - Data Output Delay Time tD - - 120 Data Hold Time tDH 20 - - Mode Item Symbol Min Typ Max Unit Write Mode (Refer to Fig- 6 ) E Cycle Time tc 1400 - - ns E Rise / Fall Time tr,tf - - 2 5 E Pulse Width (High, Low) tw 400 - - R/W and RS Setup Time tsu1 60 - - R/W and RS Hold Time th1 20 - - Data Setup Time tsu2 140 - - Data Hold Time th2 10 - - Read Mode (Refer to Fig- 7 ) E Cycle Time tc 1400 - - ns E Rise / Fall Time tr,tf - - 2 5 E Pulse Width (High, Low) tw 400 - - R/W and RS Setup Time tsu 60 - - R/W and RS Hold Time th 20 - - Data Output Delay Time tD - - 360 Data Hold Time tDH 5 - - (V DD = 4.5 to 5.5 V, Ta = -30 to +85 o C) (V DD = 2.7 to 4.5 V, Ta = -30 to +85 o C)

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Fig-6. Write Mode Timing Diagram Mode Item Symbol Min Type Max Unit Interface Mode with Extension Driver (Refer to Fig-8) Clock Pulse Width (High, Low) tw 80 0 - - ns Clock Rise / Fall Time tr,tf - - 100 Clock Setup Time tSU1 500 - - Data Setup Time tSU2 300 - - Data Hold Time tDH 300 - - M Delay Time tDw -1000 - 1000 (V DD = 2.7 to 5.5 V, Ta = -30 to +85 o C) th1 tw V IH1 tr tSU2 th2 tf th1 V IL1 Valid Data tc V IL1 tSU1 V IL1 V IH1 V IL1 V IH1 V IL1 V IH1 V IL1 V IH1 V IL1 V IL1 RS R/W E DB0~DB7

KS0070B 16COM / 80SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Fig-7. Read Mode Timing Diagram Fig-8. Interface Mode with Extension Driver Timing Diagram th tw V IH1 tr tDH tf th V IL1 Valid Data tc V IL1 tSU V IH1 V IH1 V IL1 V IH1 V IL1 V IH1 V IL1 V IH1 V IL1 V IH1 RS R/W E DB0~DB7 tD CLK1 CLK2 D M V OH2 tr tW tf V OL2 V OH2 tW V OL2 t SU1 V OH2 V OL2 tW t SU1 tDM V OL2 t DH V OH2 V OH2 V OL2