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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
July. 1999. Ver. 1.3 Prepared by: Tae- Kwang, Park parktk@samsung.co.kr KS00 40 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD KS00 40 Specification Revision History Version Content Date 0.0 Original Mar. 199 8 1.0 1) Changed function MPU interface pin & method are changed. DDRAM extended style is changed from horizontal to vertical. Reference voltage can be selected between internal V REF and V DD by REF pin. 2) Removed function Horizontal display shift function is removed. 3) Added function Double height character display function Center mode display function CGRAM full graphic function Line cursor function Vertical shift by character & first line fix and vertical shift function 4-bit interface mode 4) Changed pin name DT1 → DUMMY (Not connected) DT0 → REF (Reference voltage selection) DIRC → MI (6800- / 8080-series selection) DIRS → IF (8- / 4- bit interface length selection) RES → RESET (H/W reset) RW → RW_WR (Read / Write selection in 6800-series, Write enable in 8080-series) E → E_RD (Read / Write enable in 6800-series, Read enable in 8080-series) COMS1, 2 → COMI1, 2 (Common icon) SEGS1 ~ SEGS4 → SEGI1 ~ SEGI4 (Segment icons) Jun. 199 8 1.1 1 ) Changed pin name VC5ON → TEST3 ( Connect to VSS ) TMPS0 → TEST4 ( Connect to VSS) TMPS1 → TEST5 ( Connect to VSS) 2) DC Spec changed IDD (3V): 150 µA Max . → 180 µA Max . IDD (5V): 250 µA Max . → 280 µA Max . 3) P ower ON / OFF sequence is a dded. Apr.1999 1. 2 Page 1, 3, 23: CGROM character size is changed from 8,192 to 8,160. Page 63, 64: V REF Item, REF = H → REF = L Jun .1999 1.3 Page 6 : X-coordinates are changed (Pad No.206 to 246) Jul .1999
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD KS00 40
The KS0040 is a LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can display 1 to 4 lines of 8 characters with 16 x 16 dots format. So it is suitable for display of Asian characters such as Korean, Chinese and Japanese. Also 8 x 16 dot half size alphanumeric characters can be displayed. And it can display 64 x 128 dots graphic LCD using internal CGRAM. Voltage converter (2 to 4 times), voltage regulator and voltage follower & bias circuit s are built in the IC.
FEATURES
− Common outputs: 64 common + 1 common for icon − Segment outputs: 128 segment + 4 segment for icon Applicable Duty Ratios Display size Duty Contents of outputs 1 - line x 8 characters 1/17 1 x 8 characters + 16 x 4 vertical icons + 128 horizontal icons 2 - line x 8 characters 1/33 2 x 8 characters + 32 x 4 vertical icons + 128 horizontal icons 3 -l ine X 8 characters 1/49 3 x 8 characters + 48 x 4 vertical icons + 128 horizontal icons 4 - line X 8 characters 1/65 4 x 8 characters + 64 x 4 vertical icons + 128 horizontal icons On-chip Display Data RAM − Full-size Character Generator ROM (FCGROM): 2,088,960 bits (8,160 characters x 16 x 16 dot) − Half-size Character Generator ROM (HCGROM): 16,384 bits (128 characters x 8 x 16 dot) − Character Generator RAM (CGRAM): 8,192 bits (32 characters x 16 x 16 dot) − Display Data RAM (DDRAM): 1,024 bits (64 characters x 2 byte) − Icon RAM (ICONRAM): 384 bits (128 horizontal icons + 64 x 4 vertical icons) Microprocessor Interface − 8- / 4- bit parallel interface mode: 6800-series, 8080-series − Serial interface mode: 4 pin s clock synchronous serial interface Function Set − Various instruction sets: vertical dot-by-dot display shift, double height character, power control , etc. − COM / SEG bi-directional − H /W reset On-chip Analog Circuit − Automatically adjusted oscillator circuit by duty set − Electrical volume for contrast control (64 steps) − Voltage converter (2 to 4 times) / voltage regulator ( temperature coefficient = -0.05%/ o C ) / voltage follower & bias circuit Operating Voltage Range − Supply voltage (V DD ): 2.4 to 5.5V − LCD driving voltage (V LCD = V0 - V SS ) = 13.0V
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD Low Power Consumption − Sleep mode operation ( V DD = 3V: 5uA M ax .) − Normal mode operation ( V DD = 3V, V0 = 9V: 1 5 0uA T yp .) Package Type − Gold bumped chip or TCP
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD KS 00 40
Figure 1. Block Diagram
Figure 2. Pad Configuration
Table 2. Pad Center Coordinates
Table 2. Pad Center Coordinates (Continued)
Table 2. Pad Location (Continued)
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD PIN DESCRIPTION POWER SUPPLY Table 3 . Pin Description Name I/O Description VDD Power supply Connect to MPU power supply pin VSS Power 0V (GND) Bias voltage level for LCD driving Voltages have the following relationship: V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS When the on-chip power circuit is active, these voltages are generated according to the state of LCD bias, as following table. LCD bias V1 V2 V3 V4 1/9 bias (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0 1/8 bias (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0 1/7 bias (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0 1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0 I/O LCD DRIVER SUPPLY Table 3 . Pin Description (Continued) Name I/O Description CAP1+ Capacitor1+ connect for the internal voltage converter CAP1- Capacitor1- connect for the internal voltage converter CAP2+ Capacitor2+ connect for the internal voltage converter CAP2- Capacitor2- connect for the internal voltage converter CAP3+ Capacitor3+ connect for the internal voltage converter CAP3- O Capacitor3- connect for the internal voltage converter V OUT I/O Voltage converter output VR I V0 voltage adjustment pin which is valid only when using external resistors REF I Select the reference voltage of internal voltage regulator REF = "High": The reference voltage of internal voltage regulator is the voltage of V DD . REF = "Low": The reference voltage of internal voltage regulator is the internal V REF (2.0V).
Table 3 . Pin Description (Continued) Name I/O Description CK I External clock input It must be fixed to "High" or “Low” when the internal oscillation circuit is used. In case of external clock mode, used as the clock input and OSC bit should be OFF. MI I Select the kinds of the MPU to interface When MI = "High": 6800-series MPU interface mode When MI = "Low": 8080-series MPU interface IF I Select the interface bit length when parallel interfacing (PS = "High") When IF = "High": 8-bit interface mode When IF = "Low": 4-bit interface mode PS I Select Interface mode with the MPU When PS = "High": parallel interface mode When PS = "Low": serial interface mode MPU INTERFACE Table 3 . Pin Description (Continued) Name I/O Description RESET I Hardware reset input Initialization is performed by edge sensing (rising or falling) of the RESET signal. CSB I Used as chip selection input When CSB = "High", not selected When CSB = "Low", selected RS I Used as register selection input When RS = "High", data register When RS = "Low", instruction register RW_W R I When MI = "High"(6800-series MPU interfacing), used as read (RW_WR = "High") / write (RW_WR = "Low") selection input (R/W). When MI = "Low "(8080-series MPU interfacing), used as write enable input (WR). E_RD I When MI = "High"(6800-series MPU interfacing), used as read/write enable input (E). When MI = "Low "(8080-series MPU interfacing), used as read enable input (RD). DB0 to DB7 I/O When 8-bit interface mode, DB0 to DB7 are used as bi-directional data bus pin. When 4-bit interface mode, only DB4 to DB7 are used as data input pin and DB0 to DB3 are not used. When serial mode, DB6 (SCL) is used as serial clock input pin, DB7 (SI) is used as serial data input pin and the others are not used.
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD LCD DRIVER OUTPUT Table 3 . Pin Description (Continued) Name I/O Description COM1 to COM64 O Common signal output for character display COMI1, COMI2 O Common signal output for horizontal icon display These are the same signal but the name is different. SEG1 to SEG128 O Segment signal output for character display SEGI1 to SEGI4 O Segment signal output for vertical icon display TEST PIN Table 3 . Pin Description (Continued) Name I/O Description TEST1 to TEST 5 I Test pin Connect these to "Low". NOTE: DUMMY - These pins should be opened (floated).
Table 4. Various K inds of MPU Interface NOTE: “*” - Don’t care ("High", "Low" or "Open") . NOTE: Read operation is not permitted to 4-bit or serial interface mode.
the DR / IR selection is latched at the rising edge of the 8th serial clock (SCL). Figure 5. Timing D iagram of S erial D ata T ransfer
Table 5. RAM Map
bit "High" in system register set instruction. DDRAM address is set by the address counter (AC) as a hexadecimal number. Figure 6. Normal Mode DDRAM Address (EXT = " Low " )
Figure 7. Extended Mode DDRAM Address (EXT = " High " )
Character Generator RAM (CGRAM) CGRAM is used for user defined character pattern. It can generate 32,16 X 16 dots full-size fonts include cursor position. The capacity of CGRAM can support bitmap graphics 128 X 64 dot. To use the character pattern in CGRAM write the character code into DDRAM like table 6. Table 6 . Relationship b etween Character Code (DDRAM) and Character Pattern (CGRAM) CGRAM address CGRAM data (A0 = 0) CGRAM data (A0 = 1)Character code (DDRAM data) R R R R 3 2 1 0 A A A A A A 6 5 4 3 2 1 D D D D D D D D 7 6 5 4 3 2 1 0 D D D D D D D D 7 6 5 4 3 2 1 0 Pattern n umber 0000h 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 Pattern 1 : : : : : : 001Fh 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 Pattern 32
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD Table 7 . Example for Bitmap Graphic by CGRAM CGRAM address CGRAM data (A0 = 0) CGRAM data (A0 = 1) Pattern numberCharacter code (DDRAM data) R R R R 3 2 1 0 A A A A A A 6 5 4 3 2 1 D D D D D D D D 7 6 5 4 3 2 1 0 D D D D D D D D 7 6 5 4 3 2 1 0 0000h 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 Pattern 1 0001h 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 Pattern 2 : : : : : : Character DisplayCGRAM1 CGRAM3 CGRAM0 CGRAM2 Fig ure 8 . Example for Bitmap Display with Character
(*16) (*15) (*6) (*5) (*4) (*3) (*2) (*1) (*1024) (*1023) (*1014) (*1013) (*1012) (*1011) (*1010) (*1009) Fig ure 9 . Relationship between CGRAM Full Graphic Mode Data Writing and Display Pattern (FG = "High") During CGROM full graphic mode, CGRAM data is written from (*1) to (*1024) by 8-bit length Table 8 . The Order of CGRAM Data Writing
ICONRAM enable to display icons. Table 9. Relationship between ICONRAM A ddress and D isplay P attern
Figure 10. Relationship between Icon P attern D ata and COM / SEG L ine (When DIRC = 0, DIRS = 0) Figure 11. Relationship between Icon Pattern Data and COM / SEG Line (When DIRC = 1, DIRS = 1)
selected positions are always ON without regard to cursor position. are always ON without regard to cursor position. Table 10. Relationship between CGROM A ddress and Font P attern (KS0040-00 Font)
Table 11. KS0040 - 00 Font ( KSC5601 C ode) Map
Table 11. KS0040F00 Font ( KSC5601 C ode) Map (Continued)
consumption by reducing current to almost resting current level.
- Liquid C rystal D isplay O utput
- DDRAM, CGRAM, ICONRAM and register written information are saved.
- Operation mode is retained the same as it was prior to execution of the sleep mode.
All internal circuits are stopped.
- Power C ircuit and O scillation C ircuit
The built-in supply circuit and the oscillation circuit are turned OFF automatically by using the sleep command. ICONRAM is transferred to 128-bit segment latch serially by 8-bits unit, and then it is stored to 128-bit shift latch. segment icon latch. KS0040 has common and segment bi-directional function to help various panel application s . Table 12. SEG Data Shift Direction Table 13. COM Data Shift Direction
Figure 14. Vertical Dot-by-Dot Shift -u p ( d own) Example
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD INSTRUCTION DESCRIPTION Outline To overcome the speed difference between internal clock of KS0040 and MPU clock, KS0040 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read / write and data bus. Instruction can be divided four kinds, (1) System register set instructions (power control, contrast value set, etc.) (2) Internal RAM access instructions (RAM select, RAM address set, data read / write, etc.) (3) Display control instructions (vertical shift, double height character , etc.) (4) O thers The address of internal RAM is automatically increased or decreased by 1. NOTE : Every instruction takes one cycle execution time, so to execute the next instruction, minimum E cycle time ( tc) must be kept.
Table 14. Instruction table
Description
NOP 0 0 (Hex) 0 0 0 0 No operation Return home 0 1 (Hex) - - - - Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed Display control 0 2 (Hex) D CC LC REV Display (D), c haracter c ursor (CC), line c ursor (LC), B/W r everse d isplay (REV) ON / OFF control Power save mode 0 3 (Hex) - - - SLP Sleep mode (SLP) ON / OFF control Contrast increment / decrement 0 4 (Hex) - - - CID Contrast increment (CID = 1) or d ecrement (CID = 0) Vertical shift 0 5 (Hex) - - CD UD Vertical c haracter (CD = 1), d ot (CD = 0) s hift -u p (UD = 1), d own (UD = 0) Double height character 0 6 (Hex) - EN DH1 DH0 Double height character enable (EN) at selected line (DH1 , DH0). R3 R2 R1 R0 Selected RAM / register 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 DDRAM ICONRAM CGRAM page 0 CGRAM page 7 RAM select / system register set 0 7 (Hex) R3 R2 R1 R0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 Power control register Contrast control register Environment control register Function control register RAM address set 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 DD / CG / ICON RAM address setting, one of 3 RAM is selected by RAM select instruction. Write data 1 D7 D6 D5 D4 D3 D2 D1 D0 DD / CG / ICON RAM and system register data write Read data 1 D7 D6 D5 D4 D3 D2 D1 D0 DD / CG / ICON RAM and system register data read NOTE: " - " - Don’t care
Table 15. System Register Values
RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 - - - - Set DDRAM address to "00h" into the address counter. If the display position has shifted, it return to the original positions. When cursor or blinking is displayed on, bring the cursor to the left edge on first line of the display. The data in DDRAM does not change. Display Control RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 D CC LC REV Display control bit ON / OFF instruction D: Display ON / OFF Contro l When D = "High", entire display is turned ON When D = "Low", entire display is turned OFF, but display data is remained in DDRAM (default) CC: Character Cursor ON / OFF Control Bit When CC = "High", character cursor is turned ON. When CC = " Low", character cursor is disappeared in current display (default) . LC: Line Cursor ON / OFF Control Bit When LC = "High", line cursor is turned on according to the most significant 2-bits ( ADDR[6], ADDR[5]) of current DDRAM address (ADDR [6:0]) . When LC = " L ow", line cursor is disappeared in current display (default) REV: Black / White Reverse Display ON / OFF Control Bit When REV= "High", all the display area except icon area are black / white reversed . When REV= " Low", normal display status (default) Power Save Mode RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 - - - SLP Power Save mode is used to making KS0040 sleep mode. SLP: Sleep Mode ON / OFF Control Bit When SLP = "High", sleep mode is set (default). When SLP = "Low", sleep mode is reset. ( refer to "L OW P OWER C ONSUMPTION M ODE " and "I NITIALIZING & P OWER S AVE M ODE S ETUP ")
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD Contrast Increment / Decrement RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 - - - CID Contrast control register value increment / decrement instruction CID: Contrast Increment / Decrement Enable Bit When CID = “High”: c ontrast register value increased by 1 until 63 . When CID = “Low”: c ontrast register value decreased by 1 until 0 . Vertical Shift -u p / d own RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 - - CD UD Vertical dot-by-dot display shift - up / down instruction (refer to figure 14, 16 ) CD: Character / Dot Shift Select Bit When CD = "High" : d isplay shift - up / down by character is selected (It’s the same as 16-time dot shift) . When CD = "Low": d isplay shift - up / down by dot is selected . UD: Vertical Display Shift Direction Select When UD = "High" : d isplay shift - up is performed . When UD = "Low" : d isplay shift - down is performed . Double Height Character RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 - EN DH1 DH0 Double height character instruction (refer to figure 15 ) EN: Double Height Character Mode Enable Bit When EN = "High": d ouble height character mode is enabled . When EN = "Low": d ouble height character mode is disabled (default) . DH1, DH0: Double Height Character Line Select When [DH1, DH0] = [Low, Low]: 1, 2 - line becomes double height character = [Low, High]: 2, 3 - line becomes double height character = [High, Low]: 3, 4 - line becomes double height character = [High, High]: 1 to 4 - line becomes double height character
RAM Select / System Register Set RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 R3 R2 R1 R0 RAM select ion (DDRAM / CGRAM / ICONRAM) or system register set instruction. R3 / R2 / R1 / R0: RAM or s ystem register select ion bits Select bits Data length / value map R3 R2 R1 R0 Selected RAM or registers DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 DDRAM ICONRAM CGRAM page0 CGRAM page1 CGRAM page2 CGRAM page3 CGRAM page4 CGRAM page5 CGRAM page6 CGRAM page7 1-byte (half-size font) 2-byte (full-size font) 1-byte 2-byte 2-byte 2-byte 2-byte 2-byte 2-byte 2-byte 2-byte 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 Power control register Contrast control register Environment control register Function control register OSC VC VR DT1 VF DT0 FG INTR DIRC CM RR2 DIRS FL1 RR1 EXT RR0 ID N OTE : " - " - Don’t care For writing 2-byte data into RAM, data write instruction must be performed twice. OSC: oscillator circuit ON (OSC = "High"), OFF (OSC = "Low": default) control VC / VR / VF: voltage converter / regulator / follower circuit ON (VC / VR / VF = "High"), OFF (VC / VR / VF = "Low": default) control INTR: Use the internal voltage regulating resistors on (INTR = "High"), off (INTR = "Low": default) control bit RR2~RR0: internal voltage adjusting resistors set control register bits ([0,0,0]: default). ( refer to table 18 ) C5 to C0: electronic contrast control register ([0, 0, 0, 0, 0, 0]: default) (refer to figure 21 ) DT1, DT0: duty select register ([1, 1]: default) (refer to table 18 ) DIRC, DIRS: common data shift direction (DIRC), segment data shift direction (DIRS) flag register ([0, 0]: default) (refer to table 12 and table 13 ) EXT: DDRAM extended mode ON (EXT = "High"), OFF (EXT = "Low": default) control ID: RAM address increment (ID = "High": default), decrement (ID = "Low") mode set FG: CGRAM full graphic mode ON / OFF control register (FG = "Low": default). ( refer to figure 18 ) CM: center display mode ON / OFF control register (CM = "Low": default). ( refer to figure 17 ) FL1: first line fix mode, during vertical scroll instruction, ON / OFF control register (FL1 = "Low": default). ( refer to figure 16 ) B1, B0: character / line cursor attribute select register ([0, 0]: default) (refer to table 17 )
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD RAM Address Set RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 DDRAM / CGRAM / ICONRAM address set instruction . Each RAM is selected by RAM select instruction . Write Data RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 D7 D6 D5 D4 D3 D2 D1 D0
DDRAM / CGRAM / ICONRAM data or s ystem r egister value write instruction . Each RAM and s ystem r egister is selected by RAM select / system register set instruction. After write operation, the address is increased/decreased by 1 automatically, according to function control register set. When writing full-size character address in FCGROM to DDRAM, RAM data write instruction must be written twice , because the FCGROM address is 13-bits long. ( refer to figure 15 ) Read Data (8-bit B us M ode MPU Interface only) RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DDRAM / CGRAM / ICONRAM data or system register value read instruction . Each RAM and system register is selected by RAM select / system register set instruction. If you read RAM data after RAM address set instruction, you can get correct RAM data from the second. The first data would be incorrect, because there is no timing margin for transfer RAM data to output register. After write or read operation, the address is increased/decreased by 1 automatically, according to function control register set. When reading full size character address in FCGROM from DDRAM, RAM data read instruction must be executed twice , because the FCGROM address is 13-bits long. ( refer to figure 15 )
1 C6 C5 C4 C3 C2 C1 C0
Figure 15. DDRAM Data (FCGROM / HCGROM / CGRAM Address) Format Table 16. Display Attributes
Table 18. The R elationship between D uty and E nvironment S et
Figure 16. The Examples of Vertical Shift and First Line Fix Mode
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD (e) DH1, DH0 = [0, 0 ] and Center Mode ON (CM = 1), When 3-line Display Figure 17 . The Examples of Double Height Character Display
Figure 18 . The Examples of Full Graphic Mode Display (FG = 1)
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD INITIALIZING & POWER SAVE MODE SETUP HARDWARE RESET When RESET pin = "Active (rising or falling)", KS0040 can be initialized the following state. Return Home Address counter = 00H Control Display ON / OFF Instruction D = 0: display OFF CC, LC = [0, 0]: character / line cursor OFF REV = 0: reverse display OFF (normal display) Power Save Mode Instruction SLP = 1: s leep mode ON RAM Select Instruction R3 to R0 = [0, 0, 0, 0]: DDRAM is selected . System Register Set Instruction OSC = 0: oscillator OFF VC, VR, VF = [0, 0, 0]: voltage converter / regulator / follower OFF INTR = 0: internal voltage regulating resister OFF RR2 to RR0 = [0, 0, 0]: Internal voltage adjusting resistors set control register value are set to 000 . C5 to C0 = [0, 0, 0, 0, 0, 0]: E lectronic contrast control register value s are set to 00H . DT1, DT0 = [1, 1]: 4-line display mode DIRC = 0: normal direction of common outputs (COM1 to COM64, COMI1 (COMI2)) DIRS = 0: normal direction of segment outputs (SEGI1, SEGI2, SEG1 to SEG128, SEGI3, SEGI4) EXT = 0: N ormal DDRAM mode is selected . ID = 1: RAM address increment condition FG = 0: CGRAM full graphic mode OFF CM = 0: center display mode OFF FL1 = 0: first line fix mode OFF B1, B0 = [0, 0]: u nder line cursor attribute is selected. NOTE : If initialization is not done by RESET pin, unstable condition might result. S o, for initializing the RESET input pin must be active at first.
Reset S tart T ime tRESETB 50 ns Reset P ulse W idth tRW 1.0 µs Reset T ime tR 1.0 µs tRtRW V DD =2.4V tRESETB V DD RESET Internal Reset Time Figure 19 . Reset Timing NOTE : tRW indicates the minimum RESET duration for activat ing internal reset signal. tR indicates reset completion time of internal circuit from the edge of the internal reset signal.
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD INITIALIZING BY INSTRUCTION NOTE : Commands (3) and (4) initialize the RAM. The non-display area must satisfy the following conditions (for RAM clear). DDRAM: Write the A0H data. (Half character flag "1" and space character code "20H": "1" "0100000") CGRAM: Write the 00H data (blank data) ICONRAM: Write the 00H data (off data) As the RAM data is unstable during reset signal input (after power ON), blank data must be written. If not, unexpected display may result. Input of RAM (Data) Write Command Input of RAM Address Setup Command Display of Written Data End of Initialization Command Input (5) Display Control Commands D: ON Command Input (1) Power Save Set Command SLP = OFF (Sleep Mode OFF) (2) System Register Set Command a. Environment Register Value Set (DT1, DT0, DIRC, DIRS, EXT, ID) b. Function Control Register Value Set (FG, CM, FL1, B1, B0) c. Internal Voltage Adjusting Resistors Set Control Register set (RR2~RR0) d. Contrast Control Register Value Set (C5 to C0) e. Power Control Register Value Set (OSC → VC → VR (INTR) → VF: ON) (3) RAM Address Set Command (4) Data Writing (RAM Clear) (DDRAM = A0H, CG/ ICONRAM = 00H) Waiting for 10 µ sec or more Input of Reset Signal Power Regulation V DD -V SS Power ON Command Status Initializing by Hardware Reset Input Status Waiting for 20msec or more
SLEEP MODE SET OR RELEASE BY INSTRUCTION Sleep Mode Setting Sleep Mode Releasing Internal voltage regulating resistor control bit (INTR) and voltage adjusting resistors set control register bits (RR2 - RR0) are not changed in sleep mode. Enter the Sleep Mode Command Input (1) Display ON / OFF Control Command D = OFF (Display OFF) (2) Power Save Set Command SLP = ON (Power Save ON) *OSC, VC, VR, VF are automatically OFF . Command Status Initializing by Instruction Setup Input Status Normal Operation Status End of Initialization Return to Normal Operation Waiting for 20 ms or more Command Input (1) Power Save Set Command SLP = OFF (Sleep Mode OFF) (2) System Register Set Command (Power Control Register Set) * OSC → VC → VR → VF : ON (3) Display Control Command D = ON (Display ON ) End of Initialization
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD RECOMMENDATION OF POWER ON / OFF SEQUENCE Power ON Sequence (Power Control Register Set) Power OFF Sequence Oscillator ON [OSC, VC, VR, VF = 1, 0, 0, 0] V DD - V SS Power ON Voltage Converter ON [OSC, VC, VR, VF = 1, 1, 0, 0] Voltage Regulator ON [OSC, VC, VR, VF = 1, 1, 1, 0] Voltage Follower ON [OSC, VC, VR, VF = 1, 1, 1, 1] Waiting for ≥ 1ms Waiting for ≥ 1ms Waiting for ≥ 1ms Display OFF Voltage Regulator OFF [OSC, VC, VR, VF = 1, 1, 0, 1] Voltage Follower OFF [OSC, VC, VR, VF = 1, 1, 0, 0] Voltage Converter OFF [OSC, VC, VR, VF = 1, 0, 0, 0] Waiting for ≥ 50 ms Waiting for ≥ 1ms Waiting for ≥ 1ms Waiting for ≥ 1ms V DD -V SS Power OFF
remaining combination states are impractical, not recommended to be used. Table 19. Recommended P ower S upply C ombination NOTE : SEC recommendation is to use only the case listed above table.
Figure 22. Four T imes Boost ing
Figure 23. Voltage R egulator C ircuit
When Using Internal Resistors, Ra and Rb (INTR = "High") When INTR bit is set to " High ", resistor Ra is connected internally between VR pin and V SS , and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 20 . Internal Rb / Ra Ratio Depending on 3-bit Data (R R 2 R R 1 R R 0) 3-bit d ata settings (R R 2 R R1 R R0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 The following figure shows V0 voltage measured by adjusting internal regulator re s ist o r ratio ( Rb / Ra) and 6-bit electronic volume registers at Ta = 25 °C ( temperature coefficient = -0.05%/ °C ) . 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0 8 16 24 32 40 48 56 Electronic Volume Level [V] (1 1 1) (1 1 0) (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) Figure 24 . Electronic V olume L evel (Temperature Coefficient = -0.05% / °°C)
Table 21. The R elationship between E lectronic V olume C onstant, αα, and 6-bit Table 22. The C hange R atio of V REF and V0 by αα is as F ollowing T able
When Using External Resistors, Ra and Rb (INTR = "Low") When INTR bit is set to "Low", it is necessary to connect external regulator resistor Ra between VR and V SS , and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = (1, 1, 1, 1, 1, 1) 3. M aximum current flowing Ra, Rb = 1 µA From equation (1) Rb Ra From equation (2) 300 where α = 63 Vs = 2V or V DD From requirement 3. Ra + Rb From equations ( 2 ) , ( 3 ) and ( 4 ) A. When Vs = 2V (REF = "Low") Ra = 2 [M Ω ] Rb = 8 [M Ω ] B. When Vs = V DD = 3V (REF = "High") Ra = 3 [M Ω ] Rb = 7 [M Ω ]
Figure 25. LCD Bias Circuit Table 23. Duty Select Input & Internal Bias Circuit
Figure 26. When E xternal Power Supply is used
Figure 29. 4-Pin Serial Interface
Figure 30. Chip Bottom & Lower View (DIRS = 0, DIRC = 0)
Figure 31. Chip Bottom & Lower View (DIRS = 1, DIRC = 1)
Figure 32. Chip Top & Lower View (DIRS = 1, DIRC = 0)
Figure 33. Chip Top & Lower View (DIRS = 0, DIRC = 1)
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD FRAME FREQUENCY 1/17 Duty (DT1, DT0 = [0, 0]) 1-line Selection Period = 17 Clock Pulses One Frame = 17 x 17 x 40.8 µs = 11.8 ms (1 Clock=40.8 µs at fosc=24.5 kHz ) Frame Frequency = 1 / 11.8 ms = 85 Hz 171621 VS COM1
1 FRAME
Figure 34 . Frame Frequency (1/17 Duty) 1/33 Duty (DT1, DT0 = [0, 1]) VS 1-line Selection Period = 17 Clock Pulses One Frame = 17 x 33 x 21.0 µs = 11.8 ms (1 Clock=21.0 µs at fosc=47.6 kHz ) Frame Frequency = 1 / 11.8 ms = 85 Hz COM1 30 31 32 334321 30 31 32 334321 Figure 35 . Frame Frequency (1/33 Duty)
1/49 Duty (DT1, DT0 = [1, 0]) 494821 VS 1-line Selection Period = 17 Clock Pulses One Frame = 17 x 49 x 14.2 µs = 11.8 ms (1 Clock=14.2 µs at fosc=68.3 kHz ) Frame Frequency = 1 / 11.8 ms = 85 Hz COM1 Figure 36 . Frame Frequency (1/49 Duty) 1/65 Duty (DT1, DT0 = [1, 1]) VS 1-line Selection Period = 17 Clock Pulses One Frame = 17 x 65 x 10.7 µs = 11.8 ms (1 Clock=10.7 µs at fosc=93.7 kHz ) Frame Frequency = 1 / 11.8 ms = 85 Hz COM1 62 63 64 654321 62 63 64 654321 Figure 37 . Frame Frequency (1/65 Duty)
Table 24. Duty Select Input & Display Window Size
Table 25. Absolute Maximum Ratings
KS00 40 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
ELECTRICAL CHARACTERISTICS
Table 26. DC Characteristics
Table 26. DC Characteristics (Continued) NOTE : When power supply (VDD) range is 3.6V to 5.5V, the 4 times boosting is not allowed.
Figure 17. Write Bus Mode Timing (6800-series MPU Interface)
Figure 18. Write Bus Mode Timing (8080-series MPU Interface)
Figure 19. Read Bus Mode Timing (6800-series MPU Interface)
Figure 20. Read Bus Mode Timing (8080-series MPU Interface)
Figure 32. Clock Synchronized Serial Interface Mode Timing Diagram