KBE00F005A

KBE00F005A SAMSUNG | Alldatasheet

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KBE00F005A-D411 MCP MEMORY June 2005 1 Revision 1.0 MCP Specification 512Mb NAND*2 + 256Mb Mobile SDRAM*2 * Samsung Electronics reserves the right to change products or specification without notice. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

KBE00F005A-D411 MCP MEMORY Revision 1.0 Document Title Multi-Chip Package MEMORY 512M Bit(64Mx8) Nand Flash*2 / 256M Bit (2Mx32x4Banks) Mobile SDRAM*2

Revision History

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. Revision No. 0.0 1.0 Remark Preliminary Final History Initial issue. - 1Gb NAND Flash DDP B-Die _ Ver 0.1 - 512Mb Mobile SDRAM DDP F-Die _ Ver 1.0 <Common> - Changed operating temperature : page 3 - Changed flow chart : page 16 - Finalize Draft Date April 06, 2005 June 21, 2005 Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site. http://samsungelectronics.com/semiconductors/products/products_index.html

KBE00F005A-D411 MCP MEMORY Revision 1.0 GENERAL DESCRIPTION

FEATURES

<Common>

• Operating Temperature : -25°C ~ 85°C
• Package : 137ball FBGA Type - 10.5mmx13mm, 0.8mm pitch <NAND>
• Power Supply Voltage : 2.5~ 2.9V
• Organization - Memory Cell Array : (128M + 4096K)bit x 8 bit - Data Register : (512 + 16)bit x 8bit
• Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte
• Page Read Operation - Page Size : (512 + 16)Byte - Random Access : 15µs(Max.) - Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time - Program time : 200µs(Typ.) - Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection - Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back
• Unique ID for Copyright Protection <Mobile SDRAM>
• Power Supply Voltage : 1.7~1.95V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation.
• Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) -. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• 2/CS Support. Multi-Chip Package MEMORY 512M Bit(64Mx8) Nand Flash*2 / 256M Bit (2Mx32x4Banks) Mobile SDRAM*2 The KBE00F005A is a Multi Chip Package Memory which combines 1Gbit Nand Flash Memory(organized with two pieces of 512Mbit Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM.(organized with two pieces of 256Mbit Mobile SDRAM) 1Gbit NAND Flash memory is organized as 128M x8 bits and 512Mbit Mobile SDRAM is organized as 4M x32 bits x4 banks In 1Gbit NAND Flash,its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program oper- ation can be performed in typically 200µs on the 528-byte page and an erase operation can be performed in typically 2ms on a 16K- byte block. Data in the data register can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse rep- etition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the extended reliability of 100K program/erase cycles by providing E CC(Error Correcting Code) with real time mapping-out algorithm. This device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable appli- cations requiring non-volatility. In 512Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The KBE00F005A is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 137-ball FBGA Type. Address configuration Organization Bank Row Column Address 16M x 32 BA0, BA1 A0 - A12 A0 - A7

KBE00F005A-D411 MCP MEMORY Revision 1.0 PIN CONFIGURATION

137 FBGA: Top View (Ball Down) NAND

A4 WP ALE Vss R/B DQ31 DQ30 Vddq A5 DQ25 DQ27 DQ29 DQ28 Vssq A8 DQ18 NC DQ22 DQM3 DQ26 Vddq A11 DQ17 DQ19 DQ24 DQ23 RAS DQ15 DQ16 DQ9 Vddq CAS DQ20 DQ21 NC NC Vss CS DQ14 DQ11 DQ10 NC DQM0 Vssq BA1 DQ7 DQ8 DQ6 DQ4 Vddq A2 DQ0 DQ1 DQ2 DQ3 DQ5 Vddq Vss NC NC Vssq IO2 Vcc IO6 Vddq A B C D E F G H J K L M VssqDQM2 DNU NC DNU DNU NC Vssq Vss NC N P NC DQM1 DQ13 DQ12 9 1 0 Vss Vdd A12 NC Vdd Vss WEd Vdd Vssq Vddq Vssq Vssq Vdd Vddq Vssq Vssq Vddq Vddq Vss IO4 Vdd DNU DNU DNU DNUR IO3 IO5 IO7 NC NC NC NC NC RE A7 A9 CKE CLK BA0 A0A10 IO0 IO1 NC NC NC NC CS1

KBE00F005A-D411 MCP MEMORY Revision 1.0 NOTE : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for a ny specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.

ORDERING INFORMATION

MCP Memory(4chips) Device Type NAND + NAND + SDRAM+SDRAM NOR Flash Density, Voltage, Organization, Bank Size, Boot Block 00 = None Access Time 411 : NAND Flash 50ns NAND Flash 50ns Mobile SDRAM 9ns Mobile SDRAM 9ns SDRAM Interface, Density, Voltage, Organization, Option 5 = M-SDR, 256M+256M, 1.8V/1.8V, x32 UtRAM Density, Voltage, Organization 0 = None Package D = FBGA(Lead-Free) NAND Flash Density, Voltage, Organization F = 512M+512M, 2.7V/2.7V, x8 SRAM Density, Voltage, Organization 0 = None KB E 00 F 0 0 5 A - D 411 Version A = 2nd Generation PIN DESCRIPTION Pin Name Pin Function(Mobile SDRAM) CLK System Clock CKE Clock Enable CS,CS1 Chip Select RAS Row Address Strobe CAS Column Address Strobe WEd Write Enable A0 ~ A12 Address Input BA0 ~ BA1 Bank Address Input DQM0 ~ DQM3 Input/Output Data Mask DQ0 ~ DQ31 Data Input/Output Vdd Power Supply Vddq Data Out Power Vss Ground Vssq DQ Ground Pin Name Pin Function(NAND Flash) CE Chip Enable RE Read Enable WP Write Protection WEn Write Enable ALE Address Latch Enable CLE Command Latch Enable R/B Ready/Busy Output IO0 ~ IO7 Data Input/Output Vcc Power Supply Vss Ground Pin Name Pin Function NC No Connection DNU Do Not Use

KBE00F005A-D411 MCP MEMORY June 2005 6 Revision 1.0 FUNCTIONAL BLOCK DIAGRAM WP CLE WEn RE R/B CE IO0 to IO7 CS CAS RAS CKE WEd CLK A0~A12 DQM0~DQM3 BA0~BA1 ALE 1Gb NAND Flash Memory DQ0 to DQ31 512Mb Mobile SDRAM Vdd Vddq Vcc Vss Vss Vssq CS1

KBE00F005A-D411 MCP MEMORY June 2005 7 Revision 1.0 1Gb(128Mb x 8) NAND Flash DDP B-Die

KBE00F005A-D411 MCP MEMORY June 2005 8 Revision 1.0 PIN DESCRIPTION NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. Pin Name Pin Function I/O0 ~ I/O7 DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. CLE COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ALE ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CE CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE control during read operation, refer to ’Page read’ section of Device operation . RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WE WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WP WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. R/B READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. VccQ OUTPUT BUFFER POWER VccQ is the power supply for Output Buffer. VccQ is internally connected to Vcc, thus should be biased to Vcc. Vcc POWER VCC is the power supply for device. Vss GROUND N.C NO CONNECTION Lead is not internally connected. DNU DO NOT USE Leave it disconnected.

Figure 1. Functional Block Diagram Figure 2. Array Organization NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. 8 is set to "Low" or "High" by the 00h or 01h Command.

512 Bytes

16 Bytes

1 Block = 32 Pages

1 Page = 528 Bytes

1 Block = 528 B x 32 Pages

1 Device = 528B x 32Pages x 8,192 Blocks

command register. Table 1 defines the specific commands of this device. the conventional 512 byte structure. selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document. reading and data-input cycles are removed, system performance for solid-state disk application is significantly increased. Table 1. Command Sets NOTE : 1. The 00h command defines starting address of the 1st half of registers. The 01h command defines starting address of the 2nd half of registers. automatically moved to the 1st half register(00h) on the next cycle.

1. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.

Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation.

1. The 71h command should be used for read status of Multi Plane operation.
2. Multi plane operation and Copy-Back Program are not supported with 1.8V device.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

Figure 3. Memory Array Map

KBE00F005A-D411 MCP MEMORY June 2005 RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND , TA=-25 to 85°C) Parameter Symbol Value Unit Min Typ. Max Supply Voltage V CC 2.5 2.7 2.9 V Supply Voltage V CCQ 2.5 2.7 2.9 V Supply Voltage V SS 000 V ABSOLUTE MAXIMUM RATINGS NOTE : Maximum DC voltage on input/output pins is V CC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Symbol Rating Unit Voltage on any pin relative to VSS VIN/OUT -0.6 to + 4.6 VVCC -0.6 to + 4.6 VCCQ -0.6 to + 4.6 Temperature Under Bias T BIAS -40 to +125 °C Storage Temperature T STG -65 to +150 °C Short Circuit Current Ios 5 mA

KBE00F005A-D411 MCP MEMORY June 2005 DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less Parameter Symbol Test Conditions Value Unit Min Typ Max Operating Current Sequential Read I CC1 tRC=50ns, CE=VIL IOUT=0mA -1 0 2 0 mAProgram I CC2- - 1 0 2 0 Erase I CC3- - 1 0 2 0 Stand-by Current(TTL) ISB1C E =VIH, WP=0V/VCC --1 Stand-by Current(CMOS) ISB2C E =VCC-0.2, WP=0V/VCC -1 0 5 0 µAInput Leakage Current I LI VIN=0 to Vcc(max) - - ±10 Output Leakage Current I LO VOUT=0 to Vcc(max) - - ±10 Input High Voltage V IH* I/O pins VCCQ -0.4 - VCCQ +0.3 V Except I/O pins VCC -0.4 - VCC +0.3 Input Low Voltage, All inputs V IL* - -0.3 - 0.5 Output High Voltage Level V OH IOH-100µA VCCQ -0.4 -- Output Low Voltage Level V OL IOH=100µA- - 0 . 4 Output Low Current(R/B) IOL(R/B)V OL=0.1V 3 4 - mA Valid Block NOTE : 1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre- sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. Refer to the attached technical notes for an appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guar anteed to be a valid block, does not require Error Correction u p to 1K program/erase cycles. 3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space. Parameter Symbol Min Typ. Max Unit Valid Block Number N VB 8,052 - 8,192 Blocks

KBE00F005A-D411 MCP MEMORY June 2005 Program / Erase Characteristics Parameter Symbol Min Typ Max Unit Program Time tPROG(1) - 200 500 µs Dummy Busy Time for Multi Plane Program t DBSY 11 0 µs Number of Partial Program Cycles in the Same Page Main Array Nop - - 1 cycle Spare Array - - 2 cycles Block Erase Time t BERS -23 m s Capacitance(TA=25°C, VCC=2.7V , f=1.0MHz) NOTE : Capacitance is periodically sampled and not 100% tested. Item Symbol Test Condition Min Max Unit Input/Output Capacitance C I/O VIL=0V - 20 pF Input Capacitance C IN VIN=0V - 20 pF AC TEST CONDITION (TA=-25 to 85°C , Vcc=2.5V~2.9V unless otherwise noted) Parameter Value Input Pulse Levels 0V to VccQ Input Rise and Fall Times 5ns Input and Output Timing Levels VccQ/2 Output Load (VccQ:2.7V +/-10%) 1 TTL GATE and CL=30pF MODE SELECTION NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. CLE ALE CE WE RE WP Mode HL L H X Read Mode Command Input L H L H X Address Input(4clock) HL L H H Write Mode Command Input L H L H H Address Input(4clock) L L L H H Data Input L L L H X Data Output X X X X H X During Read(Busy) on the devices X X X X X H During Program(Busy) X X X X X H During Erase(Busy) X X(1) X X X L Write Protect XX H X X 0V/VCC(2) Stand-by NOTE : 1.Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C

KBE00F005A-D411 MCP MEMORY June 2005 AC Characteristics for Operation NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. TBD means "To Be Determinded". Parameter Symbol Min Max Unit Data Transfer from Cell to Register t R -1 5 µs ALE to RE Delay t AR 10 - ns CLE to RE Delay t CLR 10 - ns Ready to RE Low t RR 20 - ns RE Pulse Width t RP 25 - ns WE High to Busy t WB - 100 ns Read Cycle Time t RC 50 - ns RE Access Time t REA -3 0 n s CE Access Time t CEA -4 5 n s RE High to Output Hi-Z t RHZ -3 0 n s CE High to Output Hi-Z t CHZ -2 0 n s RE or CE High to Output hold t OH 15 - ns RE High Hold Time t REH 15 - ns Output Hi-Z to RE Low t IR 0- n s WE High to RE Low t WHR 60 - ns Device Resetting Time(Read/Program/Erase) t RST - 5/10/500(1) µs AC Timing Characteristics for Command / Address / Data Input NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. Parameter Symbol Min Max Unit CLE Set-up Time t CLS 0- n s CLE Hold Time t CLH 10 - ns CE Setup Time t CS 0. - n s CE Hold Time tCH 10 - ns WE Pulse Width t WP 25(1) -n s ALE Setup Time t ALS 0- n s ALE Hold Time tALH 10 - ns Data Setup Time t DS 20 - ns Data Hold Time tDH 10 - ns Write Cycle Time t WC 50 - ns WE High Hold Time tWH 15 - ns

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles. gested flow chart(Figure 4). Any intentional erasure of the initial invalid block information is prohibited. Figure 4. Flow chart to create initial invalid block table.

KBE00F005A-D411 MCP MEMORY June 2005 NAND Flash Technical Notes (Continued) Program Flow Chart Start I/O 6 = 1 ? I/O 0 = 0 ? No* Write 80h Write Address Write Data Write 10h Read Status Register Program Completed or R/B = 1 ? Program Error Yes No Yes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the b lock failure rate.The following possible failure modes should be consid ered to implement a highly reliable system. In the case of st atus read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current tar get data and copying the rest of the replac ed block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is re commended that the read failure due to single bit error should be reclaimed by ECC without any block replacement. The block failur e ratein the qualification report does not include those recla imed blocks. Failure Mode Detection and Countermeasure sequence Write Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement Read Single Bit Failure Verify ECC -> ECC Correction ECC : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection : If program operation results in an error, map out the block including the page in error and copy the * target data to another block.

KBE00F005A-D411 MCP MEMORY June 2005 Erase Flow Chart Start I/O 6 = 1 ? I/O 0 = 0 ? No* Write 60h Write Block Address Write D0h Read Status Register or R/B = 1 ? Erase Error Yes No : If erase operation results in an error, map out the failing block and replace it with another block. * Erase Completed Yes Read Flow Chart Start Verify ECC No Write 00h Write Address Read Data ECC Generation Reclaim the Error Page Read Completed Yes Block Replacement NAND Flash Technical Notes (Continued) When the error happens with page "a" of Block "A", try to write the data into another Block "B" from an exter- nal buffer. Then, prevent further system access to Block "A" (by creating a "invalid block" table or other appropriate scheme.) Buffer memory error occurs Block A Block B Page a

’B’ area, ’01h’ command must be inputted right before ’80h’ command is written. ’B’, ’C’ area can be programmed. It depends on how many data are inputted. ’A’ area after every program operation is executed. Only ’C’ area can be programmed. ’50h’ command can be omitted. ’00h’ command can be omitted. It depends on how many data are inputted. ’A’,’B’,’C’ area can be programmed. Table 2. Destination of the pointer

256 Byte

256 Byte 16 Byte

Figure 5. Block Diagram of Pointer Operation

KBE00F005A-D411 MCP MEMORY June 2005 Command Latch Cycle CE WE CLE ALE I/O0~7 Command Address Latch Cycle tCLS tCS tCLH tCH tWP tALS tALH tDS tDH CE WE CLE ALE I/O0~7 A0~A7 tCLS tCS tWC tWP tALS tDS tDH tALH tALS tWH A9~A16 tWC tWP tDS tDH tALH tALS tWH A17~A24 tWC tWP tDS tDH tALH tALS tWH tALH A25,,A26 tDS tDH tWP I/O DATA I/Ox Data In/Out I/O 0 ~ I/O 7 ~528byte

KBE00F005A-D411 MCP MEMORY June 2005 Input Data Latch Cycle CE CLE WE I/O0~7 DIN 0 DIN 1 DIN 511 ALE tALS tCLH tWC tCH tDS tDH tDS tDH tDS tDH tWP tWH tWP tWP Serial access Cycle after Read(CLE=L, WE=H, ALE=L) RE CE R/B Dout Dout Dout tRC tREA tRR tOH tREA tREH tREA tOH tRHZ* ≈≈≈≈ NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. I/Ox tCHZ* tRHZ*

KBE00F005A-D411 MCP MEMORY June 2005 tOH tOH Read1 Operation(Read One Page) CE CLE R/B I/O0~7 WE ALE RE Busy 00h or 01h A 0 ~ A7 A9 ~ A16 A17 ~ A24 Dout N Dout N+1 Dout N+2 Column Address Page(Row) Address tWB tAR2 tR tRC tRHZ tRR tCHZ Dout 527 tWC A25,A26 Status Read Cycle CE WE CLE RE I/OX 70h Status Output tCLR tCLH tCS tWP tCH tDS tDH tREA tIR tOH tOHtWHR tCEA tCLS tCHZ tRHZ

KBE00F005A-D411 MCP MEMORY June 2005 Read1 Operation(Intercepted by CE) CE CLE R/B I/O0~7 WE ALE RE Busy 00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A24 Dout N Dout N+1 Dout N+2 Page(Row) AddressAddress Column tWB tAR tCHZ tR tRR tRC Read2 Operation(Read One Page) CE CLE R/B I/O0~7 WE ALE RE 50h A0 ~ A7 A9 ~ A16 A17 ~ A24 Dout Dout 527 M Address 511+M tAR tR tWB tRR A0~A3 : Valid Address A4~A7 : Don′t care A25,A26 A25,A26 Selected Row Start address M 512 16

KBE00F005A-D411 MCP MEMORY June 2005 Page Program Operation CE CLE R/B I/O0~7 WE ALE RE 80h 70h I/O0 Din N Din 10h527A0 ~ A7 A17 ~ A24A9 ~ A16 Sequential Data Input Command Column Address Page(Row) Address 1 up to 528 Byte Data Serial Input Program Command Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program tPROGtWB tWC tWC tWC A25,A26 BLOCK ERASE OPERATION (ERASE ONE BLOCK) CE CLE R/B I/O0~7 WE ALE RE 60h A 17 ~ A24A9 ~ A16 Auto Block Erase Setup Command Erase Command Read Status Command I/O0=1 Error in Erase DOh 70h I/O 0 Busy tWB tBERS I/O0=0 Successful Erase Page(Row) Address tWC A25,A26

KBE00F005A-D411 MCP MEMORY June 2005 Multi-Plane Page Program Operation CE CLE R/B I/O0~7 WE ALE RE 80h Din N Din 11h527A0 ~ A7 A17 ~ A24A9 ~ A16 Sequential Data Input Command Column Address Page(Row) Address 1 up to 528 Byte Data Serial Input Program Max. three times repeatable tDBSYtWB tWC A25 Command Last Plane Input & Program tDBSY : typ. 1us max. 10us (Dummy) Din N Din 10h527A0 ~ A7 A17 ~ A24A9 ~ A16 tPROGtWB ≈ ≈ A25,A26 I/O 80h A0 ~ A7 & A9 ~ A26 I/O0~7 R/B

528 Byte Data

Address & Data Input 11h 80h Address & Data Input 11h 80h Address & Data Input 11h 80h Address & Data Input 10h Ex.) Four-Plane Page Program into Plane 0~3 or Plane 4~7 tDBSY tDBSY tDBSY tPROG Program Confirm Command (True) 80h 71h 71h Read Multi-Plane Status Command ,A26 A0 ~ A7 & A9 ~ A26 A0 ~ A7 & A9 ~ A26 A0 ~ A7 & A9 ~ A26 ≈ ≈ ≈

KBE00F005A-D411 MCP MEMORY June 2005 Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7 Block Erase Setup Command Erase Confirm Command Read Multi-Plane Status Command Max. 4 times repeatable 60h A9 ~ A26 I/O0~7 R/B Address 60h Address 60h Address 60h Address D0h 71h tBERS * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation CE CLE R/B I/O0~7 WE ALE RE 60h A 17 ~ A24A9 ~ A16 DOh 71h I/O 0 Busy tWB tBERS Page(Row) Address tWC A25,A26

KBE00F005A-D411 MCP MEMORY June 2005 Read ID Operation CE CLE I/O 0 ~ 7 WE ALE RE 90h Read ID Command Maker Code 00h ECh tREAD Address. 1cycle A5h C0h Multi Plane Code ID Defintition Table

90 ID : Access command = 90H

Must be don’t -cared Supports Multi Plane Operation (Must be don’t-cared for 1.8V device) 79h Device Code

KBE00F005A-D411 MCP MEMORY June 2005 Copy-Back Program Operation CE CLE R/B I/O0~7 WE ALE RE 00h 70h I/O08AhA0~A7 A17~A24A9~A16 Column Address Page(Row) Address Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program tPROGtWB tWC A0~A7 A17~A24A9~A16 Column Address Page(Row) Address Busy tWB tR Busy A25,A26 A25,A26 10h Copy-Back Data Input Command

KBE00F005A-D411 MCP MEMORY June 2005 Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg- ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read o pera- tion. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is change d. The 528 bytes of data within the selected page are trans- ferred to the data registers in less than 15µs(t R). The system controller can detect the completion of this data transfer(tR) by analyz- ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command. Addresses A 0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com- mand(00h/01h) is needed to move the pointer back to the main area. Figures 9 to 12 show typical sequence and timings for each read operation.

Figure 8. Read1 Operation

Figure 9. Read2 Operation

into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). Read Status command mode until another valid command is written to the command register. Figure 10. Program & Read Status Operation Figure 11. Block Erase Operation ensures that memory contents are not accidentally erased due to external noise conditions. the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 11 details the sequence.

enables a simultaneous programming of four pages. Partial activation of four planes is also permitted. when any of the pages fails. Multi-Plane page Program with "01h" pointer is not supported, thus prohibited. Figure 12. Four-Plane Page Program

selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure17. Figure 15. Multi-Plane Page Program & Read Status Operation address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each pla ne. Figure 16. Four Block Erase Operation Figure 13. Multi-Plane Program & Read Status Operation Figure 14. Addressing Multiple Planes

Figure 17. One Page Copy-Back program Operation ming into the copied pages is prohibited bef ore erase. A14, A15 and A26 must be the same between source and target page.

Back programming of four pages. Partial activation of four planes is also permitted. gramming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished. Figure 18. Four-Plane Copy-Back Program

Figure 19. Four-Plane Copy-Back Page Program (Continued)

KBE00F005A-D411 MCP MEMORY June 2005 READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to i t. Therefore, if the status regi ster is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. For Read Status of Multi Plane Program/Erase, the Read Multi- Plane Status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation. Table4. Read Staus Register Definition NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/ Erase operation, it sets "Fail" flag. 2. The pass/fail status applies only to the corresponding plane. I/O No. Status Definition by 70h Command Definition by 71h Command I/O 0 Total Pass/Fail Pass : "0" Fail : "1" Pass : "0"(1) Fail : "1" I/O 1 Plane 0 Pass/Fail Must be don’t -cared Pass : "0"(2) Fail : "1" I/O 2 Plane 1 Pass/Fail Must be don’t -cared Pass : "0"(2) Fail : "1" I/O 3 Plane 2 Pass/Fail Must be don’t -cared Pass : "0"(2) Fail : "1" I/O 4 Plane 3 Pass/Fail Must be don’t -cared Pass : "0"(2) Fail : "1" I/O 5 Reserved Must be don’t -cared Must be don’t-cared I/O 6 Device Operation Busy : "0" Read y : "1" Busy : "0" Ready : "1" I/O 7 Write Protect Protected : "0" Not Protect ed : "1" Protected : "0" Not Protected : "1"

Figure 20. Read ID Operation 1

Figure 21. RESET Operation after the Reset command is written. Refer to Figure 21 below.

determined by the following guidance. Figure 22. Rp vs tr ,tf & Rp vs ibusy where IL is the sum of the input currents of all devices tied to the R/B pin.

Figure 23. AC Waveforms for Power Transition

KBE00F005A-D411 MCP MEMORY June 2005 Mobile SDRAM DDP F-Die 512Mb(16Mb x 32)

KBE00F005A-D411 MCP MEMORY June 2005 FUNCTIONAL BLOCK DIAGRAM 8Mx32 8Mx32 DQ0~DQ31 A0~A12, BA0, BA1 CLK, /CAS, /RAS, /WE, DQM, CKE /CS1 /CS0

KBE00F005A-D411 MCP MEMORY June 2005 DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C) NOTES : 1. VIH (max) = 2.2V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ. Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 1.7 1.8 1.95 V VDDQ 1.7 1.8 1.95 V Input logic high voltage VIH 0.8 x VDDQ 1.8 VDDQ + 0.3 V 1 Input logic low voltage VIL -0.3 0 0.3 V 2 Output logic high voltage VOH VDDQ -0.2 - - V IOH = -0.1mA Output logic low voltage VOL - - 0.2 V IOL = 0.1mA Input leakage current ILI -2 - 2 uA 3 CAPACITANCE (VDD = 1.8V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV) Pin Symbol Min Max Unit Note Clock CCLK 2.5 6 pF CS CIN 1.5 3 pF RAS, CAS, WE, CKE CIN 2.5 6 pF DQM CIN 2.5 6 pF Address CADD 2.5 6 pF DQ0 ~ DQ31 COUT 5 10 pF ABSOLUTE MAXIMUM RATINGS NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 2.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 2.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1.0 W Short circuit current I OS 50 mA

KBE00F005A-D411 MCP MEMORY June 2005 DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C) NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ). 4. Measued with assumption that one of the 2 die should be in a state of Precharge standby in non power-down mode. Parameter Symbol Test Condition KBE00F005A-D411 111MHz@CL3 Unit Note Operating Current (One Bank Active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 50 mA 1 Precharge Standby Current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 0.6 mA ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 0.6 Precharge Standby Current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 20 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 2 Active Standby Current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 6 mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 2 Active Standby Current in non power-down mode (One Bank Active) ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 6 mA Operating Current (Burst Mode) ICC4 IO = 0 mA Page burst 4Banks Activated t CCD = 2CLKs 90 mA 1 Refresh Current ICC5 tARFC ≥ tARFC(min) 70 mA 2 Self Refresh Current ICC6 CKE ≤ 0.2V TCSR Range Max 40 Max 85 °C Full Array 300 800 uA1/2 of Full Array 240 600 1/4 of Full Array 200 500

KBE00F005A-D411 MCP MEMORY June 2005 OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) NOTES: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Parameter Symbol KBE00F005A-D411 111MHz@CL3 Unit Note Row active to row active delay tRRD(min) 18 ns 1 RAS to CAS delay tRCD(min) 27 ns 1 Row precharge time tRP(min) 27 ns 1 Row active time tRAS(min) 50 ns 1 tRAS(max) 100 us Row cycle time tRC(min) 77 ns 1 Last data in to row precharge tRDL(min) 15 ns 2 Last data in to Active delay tDAL(min) tRDL + tRP - Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Auto refresh cycle time tARFC(min) 80 ns Exit self refresh to active command tSRFX(min) 120 ns Col. address to col. address delay tCCD(min) 1 CLK 3 Number of valid output data CAS latency=3 2 ea 4Number of valid output data CAS latency=2 1 Number of valid output data CAS latency=1 0

KBE00F005A-D411 MCP MEMORY June 2005 AC CHARACTERISTICS(AC operating conditions unless otherwise noted) NOTES : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, Parameter Symbol KBE00F005A-D411 111MHz@CL3 Unit Note Min Max CLK cycle time CAS latency=3 tCC 9 1000 ns 1CAS latency=2 tCC 15 CAS latency=1 tCC 25 CLK to valid output delay CAS latency=3 tSAC 7 ns 1,2CAS latency=2 tSAC 10 CAS latency=1 tSAC 20 Output data hold time CAS latency=3 tOH 2.0 ns 2CAS latency=2 tOH 2.0 CAS latency=1 tOH 2.0 CLK high pulse width tCH 3.0 ns 3 CLK low pulse width tCL 3.0 ns 3 Input setup time tSS 2.0 ns 3 Input hold time tSH 1.5 ns 3 CLK to output in Low-Z tSLZ 1 ns 2 CLK to output in Hi-Z CAS latency=3 tSHZ nsCAS latency=2 10 CAS latency=1 20

KBE00F005A-D411 MCP MEMORY June 2005 SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) NOTES : 1. OP Code : Operand Code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only after setting partial self refresh mode of EMRS. 4. BA0 ~ BA1 : Bank select addresses. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A12,A11, A9 ~ A0 Note Register Mode Register Set H X L L L L X OP CODE 1, 2 Refresh Auto Refresh H H L L L H X X Self Refresh Entry L 3 Exit L H L H H H X X H X X X 3 Bank Active & Row Addr. H X L L H H X V Row Address Read & Column Address Auto Precharge Disable H X L H L H X V L Column Address (A0~A7) Auto Precharge Enable H 4, 5 Write & Column Address Auto Precharge Disable H X L H L L X V L Column Address (A0~A7) Auto Precharge Enable H 4, 5 Burst Stop H X L H H L X X 6 Precharge Bank Selection H X L L H L X V L X All Banks X H Clock Suspend or Active Power Down Entry H L H X X X X XL V V V Exit L H X X X X X Precharge Power Down Mode Entry H L H X X X X X L H H H Exit L H H X X X X L V V V DQM H X V X 7 No Operation Command H X H X X X X X L H H H

KBE00F005A-D411 MCP MEMORY June 2005 Register Programmed with Extended MRS Address BA1 BA0 A12 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function Mode Select RFU*1 DS RFU*1 PASR Normal MRS Mode Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 Mode Select 0 1 0 4 4 1 1 Reserved 0 1 1 3 BA1 BA0 Mode 0 1 1 8 8 Write Burst Length 1 0 0 Reserved 0 0 Setting for Nor- mal MRS 1 0 0 Reserved Reserved A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved

0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved

1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved

Register Programmed with Normal MRS Address BA0 ~ BA1 A12 ~ A10/AP A9*2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function "0" Setting for Normal MRS RFU*1 W.B.L Test Mode CAS Latency BT Burst Length A. MODE REGISTER FIELD TABLE TO PROGRAM MODES NOTES: 1.RFU(Reserved for future use) should stay "0" during MRS cycle. 2.If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. Mode Select Driver Strength PASR BA1 BA0 Mode A6 A5 Driver Strength A2 A1 A0 Size of Refreshed Area 0 0 Normal MRS 0 0 Full 0 0 0 Full Array 0 1 Reserved 0 1 1/2 0 0 1 1/2 of Full Array 1 0 EMRS for Mobile SDRAM 1 0 1/4 0 1 0 1/4 of Full Array 1 1 Reserved 1 1 1/8 0 1 1 Reserved Reserved Address 1 0 0 Reserved A12~A10/AP A9 A8 A7 A4 A3 1 0 1 Reserved 0 0 0 0 0 0 1 1 0 Reserved 1 1 1 Reserved EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength) Full Page Length x32 : 512Mb(512)

KBE00F005A-D411 MCP MEMORY June 2005 1. In order to save power consumption, Mobile SDRAM has PASR option. 2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array, 1/4 of Full Array BA1=0 - Full Array - 1/2 Array - 1/4 Array Partial Self Refresh Area BA0=0 BA1=0 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 BA1=1 BA0=0 Partial Array Self Refresh B. POWER UP SEQUENCE Note : 1. In order to save power consumption, Mobile-SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range ; Max. 40 °C, Max. 85 °C. 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. Temperature Range Self Refresh Current (Icc 6) Unit Full Array 1/2 of Full Array 1/4 of Full Array Max. 40 °C 300 240 200 uA Max. 85 °C 800 600 500 Internal Temperature Compensated Self Refresh (TCSR) 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS. EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used. The default state without EMRS command issued is the half driver strength and full array refreshed. The device is now ready for the operation selected by EMRS. For operating with DS or PASR , set DS or PASR mode in EMRS setting stage. In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.

KBE00F005A-D411 MCP MEMORY June 2005 C. BURST SEQUENCE 1. BURST LENGTH = 4 Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 2. BURST LENGTH = 8 Initial Address Sequential Interleave A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

KBE00F005A-D411 MCP MEMORY June 2005 D. DEVICE OPERATIONS BANK ADDRESSES (BA0 ~ BA1) This SDRAM is organized as two chips which has four indepen- dent banks of 2,097,152 words x 32 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations. ADDRESS INPUTS (A0 ~ A12) The 21 address bits are required to decode the 8,388,608 word locations are multiplexed into 13 address input pins (A0 ~ A12). The 13 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 8 bit column addresses (A0 ~ A7) are latched along with CAS , WE and BA0 ~ BA1 during read or write command. ADDRESSES of 512Mb CLOCK (CLK) The clock input is used as the reference for all SDRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V IL and V IH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and ICC specifications. CLOCK ENABLE (CKE) The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is fro- zen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is syn- chronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. NOP and DEVICE DESELECT When RAS , CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored.

KBE00F005A-D411 MCP MEMORY June 2005 D. DEVICE OPERATIONS (continued) DQM OPERATION The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read late ncy is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during bu rst interruptions of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. Please refer to DQM timing diagram also. MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ An and BA0 ~ BA1 in the same cycle as CS , RAS, CAS and WE going low is the data written in the mode reg- ister. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during opera- tion as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A0 ~ A2, burst type uses A3, CAS latency (read latency from column address) use A4 ~ A6, vendor specific options or test mode use A7 ~ A8, A10/AP ~ An and BA0 ~ BA1. The write burst length is programmed using A9. A7 ~ A8, A10/AP ~ An and BA0 ~ BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for vari- ous burst length, burst type and CAS latencies. EXTENDED MODE REGISTER SET (EMRS) The extended mode register stores the data for selecting driver strength, partial self refresh or temperature compensated self refresh. EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used. The default state without EMRS command issued is half driver strength, and all 4 banks refreshed. The extended mode register is written by asserting low on CS , RAS, CAS, WE and high on BA1 ,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A12 in the same cycle as CS RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. The mode register con- tents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 - A2 are used for partial self refresh , A5 - A6 are used for Driver strength, "Low" on BA1 and "High" on BA0 are used for EMRS. All the other address pins except A0-A2, A5-A6 and BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BANK ACTIVATE. The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is init iated. The read or write opera- tion can occur after a time delay of t RCD(min) from the time of bank activation. tRCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The mini- mum number of clock cycles required between bank activate and read or write command should be calculated by dividing t RCD(min) with cycle time of the clock and then rounding off the result to the next higher integer.

KBE00F005A-D411 MCP MEMORY June 2005 D. DEVICE OPERATIONS (continued) The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before another bank can be sensed reliably. t RRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to t RCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t RAS(min). Every SDRAM bank activate command must satisfy t RAS(min) specification before a prechar ge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by t RAS(max). The number of cycles for both tRAS(min) and t RAS(max) can be calculated similar to t RCD specification. BURST READ The burst read command is used to access burst of data on con- secutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least t RCD(min) before the burst read com- mand is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already pro- grammed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data out- put gapless. The burst read can be terminated by issuing another burst read or burst write in th e same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. BURST WRITE The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS , CAS and WE with valid col- umn address, a write burst is init iated. The data inputs are pro- vided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank t RDL after the last data input to be written into the active row. See DQM OPER- ATION also. ALL BANKS PRECHARGE All banks can be precharged at the same time by using Pre- charge all command. Asserting low on CS , RAS, and WE with high on A10/AP after all banks have satisfied t RAS(min) require- ment, performs precharge on all banks. At the end of t RP after performing precharge to all the banks, all banks are in idle state. PRECHARGE The precharge operation is performed on an active bank by asserting low on CS , RAS, WE and A10/AP with valid BA0 ~ BA1 of the bank to be precharged. The precharge command can be asserted anytime after t RAS(min) is satisfied from the bank active command in the desired bank. t RP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing t RP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t RAS(max). Therefore, each bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state.

KBE00F005A-D411 MCP MEMORY June 2005 D. DEVICE OPERATIONS (continued) AUTO PRECHARGE The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and "t RP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A10/AP. If burst read or burst write by asserting high on A10/AP, the bank is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to that partic- ular bank until the bank achieves idle state. AUTO REFRESH The storage cells of 64Mb, 128Mb and 256Mb SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The inter- nal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS , RAS and CAS with high on CKE and WE . The auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to com- plete the auto refresh operation is specified by t RC(min). The min- imum number of clock cycles required can be calculated by driving t RC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. All banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The 64Mb and 128Mb SDRAM’s auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms. The 256Mb and 512Mb SDRAM’s auto refresh cycle can be performed once in 7.8us or a burst of 8192 auto refresh cycles once in 64ms. SELF REFRESH The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are inter- nally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS , RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low mat- ters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tSRFX before the SDRAM reaches idle state to begin normal operation. In case that the system uses burst auto refresh during normal operation, it is recommended to use burst 8192 auto refresh cycles for 256Mb and 512Mb, and burst 4096 auto refresh cycles for 128Mb and 64Mb immediately before entering self refresh mode and after exiting in self refresh mode. On the other hand, if the syst em uses the distributed auto refresh, the system only has to keep the refresh duty cycle.

KBE00F005A-D411 MCP MEMORY June 2005 D Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z *NOTE : 1. CKE to CLK disable/enable = 1CLK. 2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L" 3. DQM masks both data-in and data-out. E. BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 2. DQM Operation 1) Clock Suspended During Write CLK CMD CKE Internal CLK DQ(CL2) DQ(CL3) WR D0 D1 D0 D1 D2 D3 Not Written Suspended Dout 2) Clock Suspended During Read (BL=4) CLK CMD CKE Internal CLK DQ(CL2) DQ(CL3) RD Masked by CKE Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Masked by CKE 1) Write Mask (BL=4) 2) Read Mask (BL=4) CLK CMD DQM DQ(CL2) DQ(CL3) CLK CMD DQM DQ(CL2) DQ(CL3) WR Masked by CKE Masked by CKE D0 D1 D3 D0 D1 D3 RD Q0 Q2 Q3 Q1 Q2 Q3 DQM to Data-in Mask = 0 DQM to Data-out Mask = 2 3) DQM with Clock Suspended (Full Page Read) *2 CLK CMD CKE DQM DQ(CL2) DQ(CL3) RD Q0 Q2 Q4 Q6 Q7 Q8 Q1 Q3 Q6 Q7Q5

KBE00F005A-D411 MCP MEMORY June 2005 tCCD *2 tCCD *2 tCDL *3 tCCD *2 tCDL *3 *NOTE: 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst. By "CAS Interrupt", to stop burst read/write by CAS access ; read and write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK) DQ(CL2) DQ(CL3) 3. CAS Interrupt (I) 1) Read interrupted by Read (BL=4) *1 2) Write interrupted by Write (BL=2) CLK CMD ADD RD RD AB 3) Write interrupted by Read (BL=2) QA0 QB0 QB1 QB1 QB3 QA0 QB0 QB1 QB1 QB3 CLK CMD ADD DQ WR WR AB DA0 DB0 DB1 CLK CMD ADD DQ(CL2) DQ(CL3) WR RD AB DA0 QB0 QB1 DA0 QB0 QB1

KBE00F005A-D411 MCP MEMORY June 2005 *NOTE: 1. To prevent bus contention, there should be at least one gap between data in and data out. Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 4. CAS Interrupt (II) : Read Interrupted by Write & DQM ii) CMD DQM (a) CL=2, BL=4 i) CMD DQ CLK DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ (b) CL=3, BL=4 CLK i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ v) CMD DQ DQM RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR Q0 D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3Q0

KBE00F005A-D411 MCP MEMORY June 2005 tRDL =2CLK tDAL =tRDL + tRP*4 *NOTE: 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank pre- charge of four banks operation. tRDL*1 *NOTE: 1. SAMSUNG can support tRDL=2CLK . 2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal 4. tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=tRDL+ tRP . Auto Precharge Starts *3 5. Write Interrupted by Precharge & DQM 6. Precharge 7. Auto Precharge 1) tRDL = 2CLK CMD DQ CLK DQM WR PRE D0 D1 D2 Masked by DQM 1) Normal Write CMD DQ CLK BL=4 & tRDL=2CLK D0 D1 D2 D3 WR PRE 2) Normal Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD PRE Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 1) Normal Write (BL=4) CLK CMD DQ WR Auto Precharge Starts@tRDL=2CLK *3 D0 D1 D2 D3 ACT 2) Normal Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

KBE00F005A-D411 MCP MEMORY June 2005 *NOTE: 1. SAMSUNG can support tRDL=2CLK. 2. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectively. 4. PRE : All banks precharge is necessary. MRS can be issued only at all banks precharge state. tRP 2CLK tRDL*1 tBDL *2 8. Burst Stop & Interrupted by Precharge 9. MRS 1) Normal Write D0 D1 D2 2) Write Burst Stop (BL=8) CMD DQ CLK DQM BL=4 & tRDL=2CLK WR PRE CLK CMD DQM DQ WR STOP D0 D1 D2 D3 3) Read Interrupted by Precharge (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD PRE Q0 Q1 Q0 Q1 4) Read Burst Stop (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD STOP Q0 Q1 Q0 Q1 1) Mode Register Set CLK CMD PRE MRS ACT

KBE00F005A-D411 MCP MEMORY June 2005 tSS tSS Auto Refresh Command PRE tRP(min) tARFC(min) Auto CKE = High Refresh CMD An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tARFC(min). CLK A Self Refresh command is defined by having CS , RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self refresh command, all of the external control signals including system clock(CLK) can be disabled except CKE. The clock is internally disabled during Self Refresh operation to reduce power. To exit the Self Refresh mode, supply stable clock input before returning CKE high, assert deselect or NOP command and then assert CKE high . In case that the system uses burst auto refresh during normal opreation, it is recommended to use burst 4096 auto refresh cycle immediately before entering self refresh mode and after exiti ng in self refresh mode. On the other hand, if the system uses t he distributed auto refresh, the syst em only has to keep the refresh duty cycle. Self Refresh Command CKE Stable Clock tSS NOPSelf Refresh CLK tSRFX(min) tSS ∼∼ ∼ ACT 10. Clock Suspend Exit & Power Down Exit 11. Auto Refresh & Self Refresh 1) Clock Suspend (=Active Power Down) Exit 2) Power Down (=Precharge Power Down) Exit CLK CKE Internal CLK CMD RD CLK CKE Internal CLK CMD NOP ACT

KBE00F005A-D411 MCP MEMORY June 2005 12. About Burst Type Control Basic MODE Sequential Counting At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=1, 2, 4, 8 and full page. Interleave Counting At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting. Random MODE Random column Access tCCD = 1 CLK Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM. 13. About Burst Length Control Basic MODE 1 At MRS A2,1,0 = "000". At auto precharge, tRAS should not be violated. 2 At MRS A2,1,0 = "001". At auto precharge, tRAS should not be violated. 4 At MRS A2,1,0 = "010". 8 At MRS A2,1,0 = "011". Full Page At MRS A2,1,0 = "111". Wrap around mode(infinite burst length) should be stopped by burst stop. RAS interrupt or CAS interrupt. Special MODE BRSW At MRS A9 = "1". Read burst =1, 2, 4, 8, full page write Burst =1. At auto precharge of write, t RAS should not be violated. Random MODE Burst Stop tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively Using burst stop command, any burst length control is possible. Interrupt MODE RAS Interrupt (Interrupted by Precharge) Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. t RDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. CAS Interrupt Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued.

KBE00F005A-D411 MCP MEMORY June 2005 FUNCTION TRUTH TABLE (TABLE 1) Current State CS RAS CAS WE BA Address Action Note IDLE H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL 2 L H L X BA CA, A10/AP ILLEGAL 2 L L H H BA RA Row (& Bank) Active ; Latch RA L L H L BA A10/AP NOP 4 L L L H X X Auto Refresh or Self Refresh 5 L L L L OP code OP code Mode Register Access 5 Row Active H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL 2 L H L H BA CA, A10/AP Begin Read ; latch CA ; determine AP L H L L BA CA, A10/AP Begin Read ; latch CA ; determine AP L L H H BA RA ILLEGAL 2 L L H L BA A10/AP Precharge L L L X X X ILLEGAL Read H X X X X X NOP (Continue Burst to End --> Row Active) L H H H X X NOP (Continue Burst to End --> Row Active) L H H L X X Term burst --> Row active L H L H BA CA, A10/AP Term burst, New Read, Determine AP L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP Term burst, Precharge timing for Reads L L L X X X ILLEGAL Write H X X X X X NOP (Continue Burst to End --> Row Active) L H H H X X NOP (Continue Burst to End --> Row Active) L H H L X X Term burst --> Row active L H L H BA CA, A10/AP Term burst, New read, Determine AP 3 L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP Term burst, precharge timing for Writes 3 L L L X X X ILLEGAL Read with Auto Precharge H X X X X X NOP (Continue Burst to End --> Precharge) L H H H X X NOP (Continue Burst to End --> Precharge) L H H L X X ILLEGAL L H L X BA CA, A10/AP ILLEGAL L L H X BA RA, RA10 ILLEGAL 2 L L L X X X ILLEGAL Write with Auto Precharge H X X X X X NOP (Continue Burst to End --> Precharge) L H H H X X NOP (Continue Burst to End --> Precharge) L H H L X X ILLEGAL L H L X BA CA, A10/AP ILLEGAL L L H X BA RA, RA10 ILLEGAL 2 L L L X X X ILLEGAL

KBE00F005A-D411 MCP MEMORY June 2005 *NOTE: 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle. 2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle. Abbreviations : RA = Row Address BA = Bank Address NOP = No Operation Command CA = Column Address AP = Auto Precharge FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS WE BA Address Action Note Precharging H X X X X X NOP --> Idle after tRP L H H H X X NOP --> Idle after tRP L H H L X X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP NOP --> Idle after tRP 4 Row Activating L L L X X X ILLEGAL H X X X X X NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L X X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP ILLEGAL 2 L L L X X X ILLEGAL Refreshing H X X X X X NOP --> Idle after tRC L H H X X X NOP --> Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL Mode Register Accessing H X X X X X NOP --> Idle after 2 clocks L H H H X X NOP --> Idle after 2 clocks L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL

KBE00F005A-D411 MCP MEMORY June 2005 FUNCTION TRUTH TABLE (TABLE 2) Current State CKE (n-1) CKE n CS RAS CAS WE Address Action Note Self Refresh H X X X X X X Exit Self Refresh --> Idle after tsRFX(ABI) L H H X X X X Exit Self Refresh --> Idle after tsRFX (ABI) 6 L H L H H H X Exit Self Refresh --> Idle after tsRFX (ABI) 6 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) All Banks Precharge Power Down H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI 7 L H L H H L X ILLEGAL 7 L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Low Power Mode) All Banks Idle H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down 8 H L L H H L X ILLEGAL 8 H L L H L X X ILLEGAL H L L L H H RA Row (& Bank) Active H L L L L H X Enter Self Refresh 8 H L L L L L OP Code Mode Register Access L L X X X X X NOP Any State other than Listed above H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend next cycle 9 L H X X X X X Exit Clock Suspend next cycle 9 L L X X X X X Maintain Clock Suspend *NOTE: 6. CKE low to high transition is asynchronous. 7. CKE low to high transition is asynchronous if restarts internal clock. A minimum setup time 1CLK + t SS must be satisfied before any command other than exit. 8. Power down and self refresh can be entered only from the all banks idle state. 9. Must be a legal command. Abbreviations : ABI = All Banks Idle, RA = Row Address

KBE00F005A-D411 MCP MEMORY June 2005 Power Up Sequence Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK Page Read Cycle at Different Bank @Burst Length=4 Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK Read & Write Cycle at Different Bank @Burst Length=4 Read & Write Cycle With Auto Precharge l @Burst Length=4 Read & Write Cycle With Auto Precharge ll @Burst Length=4 Clock Suspension & DQM Operation Cycle @CAS Letency=2, Burst Length=4 Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK Burst Read Single bit Write Cycle @Burst Length =2 Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4 Self Refresh Entry & Exit Cycle & Exit Cycle Mode Register Set Cycle and Auto Refresh Cycle Extended Mode Register Set Cycle

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 High level is necessary CKE CS RAS CAS ADDR BA0 BA1 DQ A10/AP WE Power Up Sequence for Mobile SDRAM DQM Precharge tRP 16 17 18 19 20 21 22 24 23 25 Key RAa Hi-Z Hi-Z tARFC tARFC (All Bank) Auto Refresh Auto Refresh Normal MRS Extended MRS Row Active (A-Bank) *NOTE: 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply V DD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS. EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used. The default state without EMRS command issued is the half driver strength and full array refreshed. The device is now ready for the operation selected by EMRS. For operating with DS or PASR , set DS or PASR mode in EMRS setting stage. In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set. : Don’t care Key CLOCK Hi RAa

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA0,BA1 A10/AP WE ADDR DQM : Don’t care CLOCK Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 HIGH Ra Ca BS BS Ra DQ Row Active Read Write Read Row Active Precharge tCC tCH tCL tRAS tRC tSH tSS *Note 1 tRCD tRP tSH tSS tSH tSStSH tSS *Note 2 *Note 2,3 *Note 2,3 *Note 2,3 *Note 4 *Note 2 *Note 3 *Note 3 *Note 3 *Note 4 tSS tSH tOHtSLZ tSAC tSHtSS tSHtSS *NOTE: 1. All input except CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0,BA1. Cb Cc Rb BS BS BS BS Qa Db Qc Rb

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP CL=3 ADDR WE : Don’t care CLOCK Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK HIGH Ra Ca Ra CL=2 Row Active Read Write Precharge tRC *Note 1 tSHZtSAC tOH *NOTE: 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ) after the clcok. 3. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) BA0 DQM DQ tRDL *Note 2 *Note 4 tSHZtSAC tOH tRDL*Note 4 (A-Bank) (A-Bank) (A-Bank) (A-Bank) Row Active (A-Bank) Precharge (A-Bank) tRCD Qa1 Db0Qa0 Qa2 Db1 Db2 Db3Qa3 Qa1 Db0Qa0 Qa2 Db1 Db2 Db3Qa3 Rb Rb Cb

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP CL=3 ADDR WE : Don’t care CLOCK Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK HIGH Ra Ca Ra CL=2 Row Active Read Write Precharge *NOTE: 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, t RDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. tDAL ,last data in to active delay, is 2CLK + tRP. BA0 DQM DQ tRDL *Note 3 (A-Bank) (A-Bank) (A-Bank) (A-Bank) *Note 2 Cb tDAL *Note 4 *Note 1 tCDL Read (A-Bank) Write (A-Bank) Row Active (A-Bank) Cc Cd Rb Rb Qa1 Dd0Qa0 Qb0 Dd1 Qb1 Qb2 Dc0 Dc1 Qa1 Dd0Qa0 Qb0 Dd1 Qb1 Dc0 Dc1 tRCD

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP CL=3 ADDR WE : Don’t care CLOCK Page Read Cycle at Different Bank @Burst Length=4 HIGH RAa CAa RAa CL=2 Row Active Read Precharge *NOTE: 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. BA0 DQM DQ (A-Bank) (A-Bank) (D-Bank) *Note 2 RCc Read (B-Bank) CBb RDd CCc CDd RBb RCc RDd QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 Row Active (B-Bank) Row Active (C-Bank) Row Active (D-Bank) Precharge (A-Bank) Read (C-Bank) Precharge (B-Bank) Read (D-Bank) Precharge (C-Bank) *Note 1 QAa0 QAa0 RBb

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP ADDR WE : Don’t care CLOCK Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK HIGH RAa Row Active Write Write Precharge *NOTE: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. BA0 DQM DQ *Note 1 (A-Bank) (A-Bank) (D-Bank) (All Banks) *Note 2 RAb CAa CBb RCc RDd CCc RAa RBb RCc RDd DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2 tCDL tRDL Row Active (B-Bank) Write (B-Bank) Row Active (C-Bank) Row Active (D-Bank) Write (C-Bank) DAa2DAa1DAa0 CDd

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP CL=3 ADDR WE : Don’t care CLOCK Read & Write Cycle at Different Bank @Burst Length=4 HIGH RAa RAa CL=2 Row Active Read Write Read *NOTE: 1. tCDL should be met to complete write. BA0 DQM DQ (A-Bank) (A-Bank) (D-Bank) (B-Bank) Precharge (A-Bank) CAa RDb RBc CBc RDb tCDL *Note 1 Row Active (D-Bank) Row Active (B-Bank) QAa1QAa0 QAa2 QAa3 QBc0 QBc1 QBc2 DDb0 DDb1 DDb2 DDb3 QAa1QAa0 QAa2 QAa3 QBc0 QBc1 CDb RBc DDb0 DDb1 DDb2 DDb3

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP CL=3 ADDR WE : Don’t care CLOCK Read & Write Cycle with Auto Precharge I @Burst Length=4 HIGH RAa RAa CL=2 Row Active Read with Precharge Row Active *NOTE: 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if Read(Write) command without auto precharge is issued at B-Bank before A-Bank auto precharge starts, A-Bank auto precharge will start at B-Bank read command input point . - any command can not be issued at A-Bank during t RP after A-Bank auto precharge starts. BA0 DQM DQ (A-Bank) Auto Pre (B-Bank) (A-Bank) Read without Auto Precharge(B-Bank) RBb RAc CAcCAa CBb RBb DAc0 DAc0 charge (A-Bank) Row Active (B-Bank) Auto Precharge Start Point (A-Bank) *Note1 Write with Auto Precharge (A-Bank) QAa1QAa0 QBb0 QBb1 DBb3 QBb2 QAa1QAa0 QBb0 QBb1 DBb3QBb2 DAc1 DAc1 RAc

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP CL=3 ADDR WE : Don’t care CLOCK Read & Write Cycle with Auto Precharge II @Burst Length=4 HIGH Ra CL=2 Row Active Read with *NOTE: 1. Any command to A-bank is not allowed in this period. t RP is determined from at auto precharge start point BA0 DQM DQ (A-Bank) Auto Precharge Auto Precharge Start Point Ca Rb (A-Bank) (A-Bank) Row Active (B-Bank) *Note1 Cb Read with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) Rb Qa1Qa0 Qa2 Qa3 Qb1 Qb0 Qb2 Qb3 Qa1Qa0 Qa2 Qa3 Qb1 Qb0 Qb2 Qb3 Ra

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP ADDR WE : Don’t care CLOCK Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 Ra Row Active Read Write *NOTE: 1. DQM is needed to prevent bus contention. BA0 DQM DQ *Note 1 DQM Ca Qb0 Qb1 Dc0 Dc2 Clock Suspension Write Cb Ra tSHZtSHZ Read Clock Suspension Write DQM Read DQM Qa1 Qa2 Qa3Qa0 Cc

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP CL=3 ADDR WE : Don’t care CLOCK Read Interrupted by Precharge Command & Read Burst Stop Cycle @Full Page Burst HIGH RAa CL=2 Row Active *NOTE: 1. At full page mode, burst is finished by burst stop or precharge. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at every burst length. BA0 DQM QAa3 (A-Bank) CAa CAb Burst Stop Precharge (A-Bank) DQ QAa4 1 1 QAa2 QAa3 QAa4 RAa Read (A-Bank) Read (A-Bank) QAa1QAa0 QAa2 QAa1QAa0 QAb1QAb0 QAb2 QAb3 QAb4 QAb5 QAb1QAb0 QAb2 QAb3 QAb4 QAb5

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP ADDR WE : Don’t care CLOCK Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, RAa Row Active Write *NOTE: 1. At full page mode, burst is finished by burst stop or precharge. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of t RDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. BA0 DQM DQ CAa CAb Burst Stop HIGH RAa DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 tBDL *Note 1 tRDL *Note 1,2 (A-Bank) (A-Bank) Write (A-Bank) Precharge (A-Bank) tRDL=2CLK DAa2DAa1DAa0

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS BA1 A10/AP CL=3 ADDR WE : Don’t care CLOCK Burst Read Single bit Write Cycle @Burst Length=2 HIGH RAa CL=2 Row Active *NOTE: 1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that t RAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. BA0 DQM (A-Bank) CAa RCc Precharge (C-Bank) DQ RAa Write (A-Bank) *Note 2 RBb CAb CBc CCd RBb RCc Row Active (B-Bank) Read with Auto Precharge (A-Bank) Row Active (C-Bank) Write with Auto Precharge (B-Bank) Read (C-Bank) DAa0 QAb0 QAb1 DBc0 QCd0 QCd1 DAa0 QAb0 QAb1 DBc0 QCd0 QCd1

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS A10/AP ADDR WE : Don’t care CLOCK Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 Precharge Row Active Precharge *NOTE: 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + t SS prior to Row active command. 3. Can not violate minimum refresh specification. (64ms) BA DQM DQ *Note 1 Power-down *Note 2 Ra Ca Qa0 Qa1 Qa2 Precharge Power-down Read Ra tSHZ *Note 2 Entry Exit Active Power-down Entry Active Power-down Exit tSS *Note 3 tSS tSS

KBE00F005A-D411 MCP MEMORY June 2005 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 CKE CS RAS CAS A10/AP ADDR WE : Don’t care CLOCK Self Refresh Entry & Exit Cycle Self Refresh Entry *NOTE: TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum t RAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tSRFX is required after CKE going high to complete self refresh exit. 7. 4K cycle(64Mb ,128Mb) or 8K cycle(256Mb, 512Mb) of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. BA0,BA1 DQM DQ *Note 1 *Note 4 tSS *Note 3 tSRFX*Note 2 *Note 6 Self Refresh Exit Auto Refresh Hi-Z Hi-Z

KBE00F005A-D411 MCP MEMORY June 2005 0123456 0 1 0 CKE CS RAS CAS BA1 ADDR WE : Don’t care CLOCK Mode Register Set Cycle Key MRS New Command *NOTE: MODE REGISTER SET CYCLE 1. CS , RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. BA0 DQM DQ Ra Auto Refresh Auto Refresh Cycle 123456789 HIGH HIGH New Command * All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. *Note 2 *Note 1 *Note 3 tARFC Hi-Z Hi-Z

KBE00F005A-D411 MCP MEMORY June 2005 0123456 CKE CS RAS CAS BA1 ADDR WE : Don’t care CLOCK Extended Mode Register Set Cycle Key EMRS New Command *NOTE: EXTENDED MODE REGISTER SET CYCLE 1. CS , RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. BA0 DQM DQ Ra HIGH *Note 2 *Note 1 *Note 3 Hi-Z

KBE00F005A-D411 MCP MEMORY June 2005 PACKAGE DIMENSION Units:millimeters

0.10 MAX

0.45±0.05 0.32±0.05 1.30±0.10 TOP VIEW 10.50±0.10 13.00±0.10 #A1 13.00±0.10 137-∅0.45±0.05 0.80

0.20 M A B ∅

(Datum A) 142765 38 #A1 INDEX MARK 10.50±0.10 13.00±0.10 0.80 910 0.80x9=7.20 0.80x14=11.20 A B C E G D F H J L K M N R (Datum B) 5.60 3.60 A B BOTTOM VIEW P 137-Ball Fine pitch Ball Grid Array Package (measured in millimeters)