KB2502

KB2502 SAMSUNG | Alldatasheet

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MAR. 2000 Ver 1.4 DATA SHEET KB2502 Preliminary

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary VIDEO AMP MERGED OSD PROCESSOR The KB2502 is a very high frequency video amplifier & wide range OSD processor 1 chip system with I 2 C Bus control used in monitors. It contains 3 matched R/G/B video amplifiers with OSD processor and provides flexible interfacing to I 2 C Bus controlled adjustment systems. FUNCTIONS

• R/G/B video amplifier
• OSD processor
• I2 C bus control
• Cut-off brightness control
• R/G/B sub contrast/cut-off control
• Half tone

FEATURES

• 3-channel R/G/B video amplifier, 175MHz @f-3dB
• I2 C bus control items - Contrast control: -38dB - Sub contrast control for each channel: -12dB - Brightness control - OSD contrast control: -38dB - Cut-off brightness control (AC coupling) - Cut-off control for each channel (AC coupling) - Switch registers for SBLK and video half tone and CLP/BLK polarity selection and INT/EXT CLP selection and generated CLP width control
• Built in ABL (automatic beam limitation)
• Built in video input clamp, BRT clamp
• Built in video half tone (3mode) function on OSD pictures
• Capable of 8.0Vp-p output swing
• Improvement of rise & fall time (2.2ns)
• Cut-off brightness control
• Built in blank gate with spot killer
• Clamp pulse generator
• OSD intensity
• BLK, CLP polarity selection
• Clamp gate with anti OSD sagging 32-DIP-600A

ORDERING INFORMATION

Device Package Operating Temperature KB2502 32-DIP-600A -20 °C ~ +75 °C OSD PART

• Built in 1K-byte SRAM
• 448 ROM fonts (each font consists of 12 × 18 dots.)
• Full screen memory architecture
• Wide range PLL available (15kHz ~ 90kHz, Reference 800 X 600)
• Programmable vertical height of character
• Programmable vertical and horizontal positioning
• Character color selection up to 16 different colors
• Programmable background color (up to 16 colors)
• Character blinking, bordering and shadowing
• Color blinking
• Character scrolling
• Fade-in and fade-out
• Box drawing
• Character sizing up to four times
• 72MHz pixel frequency from on-chip PLL (Reference 800 X 600)

Figure 1. Functional Block Diagram

19 GND2

Figure 2. Pin Configuration

Table 1. Pin Configuration

1 VFLB I Vertical flyback signal

2 VSSA - Ground (PLL part)

3 VCO_IN_P I This voltage is generated at the external loop filter and goes into the

4 VREF1 O Charge pump output

5 VREF O PLL regulator filter

6 VDDA - +5V supply voltage for PLL part

7 CONT_CAP - Contrast control for AMP part

9 GND3 - Ground for video AMP part(for AMP control)

10 CLP_IN - Video clamp pulse input

11 VCC3 - +12V supply voltage for video AMP part(for AMP control)

12 RIN I Video signal input (red)

13 VCC1 - +12V supply voltage for video AMP(for main video signal process)

14 GIN I Video signal input (green)

15 GND1 - Ground for video AMP part(for main video signal process)

16 BIN I Video signal input (blue)

17 BCLP - B output clamp cap

18 BOUT O Video signal output (blue)

19 GND2 - Ground for video AMP part(for video output drive)

20 GCLP - G output clamp cap

21 GOUT O Video signal output (green)

22 VCC2 - +12V supply voltage for video AMP part(for video output drive)

23 RCLP - R output clamp cap

24 ROUT O Video signal output (red)

25 BCT - B cut-off output

26 GCT - G cut-off output

27 RCT - R cut-off output

28 VSS - Ground for digital part

29 SCL I Serial clock (I 2 C)

30 SDA I/O Serial data (I 2 C)

31 VDD - +5V supply voltage for digital part

32 HFLB I Horizontal flyback signal

Table 2. Pin Description

7 Contrast cap

8 ABL_IN

10 CLP_IN Multi polarity input

Table 2. Pin Description (Continued)

29 SCL Serial clock input port of I 2 C bus

30 SDA Serial data input port of I 2 C bus

Table 3. Absolute Maximum Ratings

1 Maximum supply voltage

2 Operating temperature (see 2) Topr -20 - 75 °C

3 Storage temperature Tstg -65 150 °C

4 Operating supply voltage

5 Power dissipation P D - - W

Table 4. Thermal & ESD Parameter

1 Thermal resistance

2 Junction temperature Tj - 150 - °C

3 Human body model

4 Machine model

5 Charge device model CDM 800 - - V

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary

ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS (Tamb = 25 °C, V CC = 12V, V DD = V DDA = 5V, ABL input voltage = 5V, HFLB input signal = S3, load resistors = 470 Ω , except OSD part current 35 mA, unless otherwise stated) Table 5. DC Electrical Characteristics

Table 5. DC Electrical Characteristics (Continued)

Table 6. AC Electrical Characteristics

Table 7. OSD Electrical Chaacteristics

Table 8. Operation Timings Figure 3. I 2 C Bus Timing Diagram

Table 9. OSD Part DC Electrical Characteristics

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary NOTES: 1. Absolute maximum rating indicates the limit beyond which damage to the device may occur. 2. Operating ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the electrical characteristics. The guaranteed specifications appl y only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. 3. V CC supply pins 11, 13, and 22 must be externally wired together to prevent internal damage during V CC power on/off cycles. 4. The supply current specified is the quiescent current for V CC 1 /V CC 2 and V CC 3 with RL = ∞, The supply current for V CC2 (pin 22) also depends on the output load. 5. Output voltage is dependent on load resistor. Test circuit uses RL = 470 Ω 6. Measure gain difference between any two amplifiers Vin = 700mVpp. 7. When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit board without socket is recommended. Video amplifier 50MHz cross talk test also requires this printed circuit board. The reason for a double sided full ground plane PCB is that large measurement variations occur in single sided PCBs. 8. Adjust input frequency from 10MHz (AV max reference level) to the -3dB frequency (f -3dB). 9. Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at fin = 50MHz for cross talk 50MHz. 10. A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15kHz. This limit is guaranteed by design. if a lower line rate is used a longer clamp pulse may be required. 11. During the AC test the 4V DC level is the center voltage of the AC output signal. For example. If the output is 4Vpp the signal will swing between 2V DC and 6V DC. 12. These parameters are not tested on each product which is controlled by an internal qualification procedure. 14. Sub address 0F03, 0F05 ~ 0F07: FFH 0F04, 0F08 ~ 0F0C: 80H RGB input = S1, When the ABL input voltage is 0V, the R/G/B’s output voltage is VR/VG/VB and uses the formula ABLR = 20log (VR/V cffR ) 15. OSD TST mode = High, CLP operation off, RGB input = S5 (frequency sweep), RGB input clamp cap = 2.1V DC, RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V), S5’s frequency 1MHz → 130MHz sweep, -3dB point = 20log (V 130MHz /V 1MHz ) 03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H 0F: 80H 16. OSD TST mode = High, CLP operation off, RGB input clamp cap = 2.1V DC, RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V), 03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H 0F: 80H R input = S5 (50MHz) CT_50M = 20log (V outG /V outR ) or 20log (V outB /V outR ) 17. OSD TST mode = High, CLP operation off, RGB input clamp cap = 2.1V DC, RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V), 03, 05 ~ 07: FFH 04, 08 ~ 0C: 80H 0F: 80H R input = S5 (130MHz) CT_150M = 20log (V outG /V outR ) or 20log (V outB /V outR )

• S1, S2 signal’s low level must be synchronized with the S3 signal’s sync. term.
• The input signal level uses the IC pin as reference.

Table 10. Test Signal Format

Figure 4. Test Circuit

fonts, and the upper 7 bits give font characteristics to the selected font. character color intensity, horizontal & vertical character size, box, border, and shadow features in units of row. fade-in/out in units of frame. The V-AMP control registers are also located in the 16th row. Figure 9. Memory Map of Display Registers

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary REGISTER DESCRIPTION BINV BOX1 BOX0 B G R Blink/Fint C8 C7 C6 C5 C4 C3 C2 C1 C0 F E D C B A 9 8 7 6 5 4 3 2 1 0 Character Attribute Character Code (448 fonts) ¨ Character & Attribute Register: Row00 ~ 14, Column00 ~ 29 RB RG RR RINT CINT HZ2 HZ0 VZ1 VZ0 F E D C B A 9 8 7 6 5 4 3 2 1 0 ¨ Row Attribute Register: Row00 ~ 14, Column30 - BREN INTE CBil BOXE BORD SHA Raster Color Intensity Character Size - - Erase EN Scrl ScrT Bli1 Bli0 BliT F E D C B A 9 8 7 6 5 4 3 2 1 0 ¨ Frame Control Register 0: Row15, Column00 - Fde FdeT VPOL HPOL - - dot0 - FBLK CH5 CH4 CH3 CH2 CH1 CH0 F E D C B A 9 8 7 6 5 4 3 2 1 0 ¨ Frame Control Register 1: Row15, Column01 CP1 CP0 Fpll HF2 HF1 HF0 dot1 PLL Control Character Height Control HP0 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 F E D C B A 9 8 7 6 5 4 3 2 1 0 ¨ Frame Control Register 2: Row15, Column02 HP7 HP6 HP5 HP4 HP3 HP2 HP1 Horizontal Start Position Vertical Start Position - VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 F E D C B A 9 8 7 6 5 4 3 2 1 0 ¨ V-AMP Control Register: Row15, Column03 ~ 15 - - - - -- - - Contrast Control Column03 - BRT7 BRT6 BRT5 BRT4 BRT3 BRT2 BRT1 BRT0 F E D C B A 9 8 7 6 5 4 3 2 1 0 - - - - -- - - Brightness Control Column04 - RSB7 RSB6 RSB5 RSB4 RSB3 RSB2 RSB1 RSB0 F E D C B A 9 8 7 6 5 4 3 2 1 0 - - - - -- - - R SUB Contrast Control Column05 - GSB7 GSB6 GSB5 GSB4 GSB3 GSB2 GSB1 GSB0 F E D C B A 9 8 7 6 5 4 3 2 1 0 - - - - -- - - G SUB Contrast Control Column06

Figure 10. Register Description

Table 11. Register Description This is the address of 448 ROM fonts. blinking duty. When giving intensity in units of font, refer to the table below. attribute register's CINT bit. box drawings possible with font 'A' are shown below. Refer to row attribute register's 'BOXE' bit.

when changing font size. Refer to Character Size. Table 11. Register Description (Continued)

three bits have no meaning. Refer to 'BOXE' bit shown below. Character shadowing feature is carried out if you set this bit to '1'. Character bordering feature is carried out if you set this bit to '1'. attribute register's RB, RG, and RR don't do anything. If the BREN bit is '1' and the raster color is black, the raster is transparent. video's back raster. Refer to other color effect.

If this bit is '1', blink time is 0.5sec, and if not, 1sec. As the font blinks, there is a time when it is visible and invisible on screen. is the length of time the font is shown on screen. If this bit is '1', scroll time is 0.5sec, and if not, 1sec. register) because of video and OSD output timing. called erasing time, which can be calculated as follows.

according to your convenience. words, this bit is set to '1' if active high, and '0' if active low. words, this bit is set to '1' if active high, and '0' if active low. If this bit is '1', fade-in/fade-out time is 0.5sec. If not, it is 1sec.

KB2502 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS Preliminary Tabel 4. Register Description (Continued) Registers Bits Description Frame Control Registers - 1 (Row 15, Column 01) CH5 ~ CH0 (bit 5 ~ 0) Character height control While the purpose of VZ[1:0] (vertical character height) is to control the absolute size of the character, the purpose of CH[5:0] (Character Height) is to output OSD of a uniform size even if the resolution changes. If you adjust the value in the range of CH = 18 ~ CH = 63, each line's repeating number is decided (standard height CH = 18 is the reference value), by which the line is repeated. For more information on repeating number selection, refer to character height. FBLK (bit 6) Selection of the FBLK output pin's configuration Unlike pin description's FBLK, if this bit is '0', the FBLK pin output is high while the character and raster are being displayed and the character and raster are output as they are. If this bit is '1', the FBLK pin output becomes high only when character is being displayed, so only the character is output. Refer to 'Figure 11. Character/raster signal part. dot1, dot0 (bit 9, 8) Resolution control (dots/line) As shown above, the number of dots per horizontal line is decided by a combination of these two bits. HF2~HF0 (bit C ~ A) Horizontal frequency PLL's horizontal frequency is decided by the combination of these 3 bits. This is related to the selection of DOT[1:0], so you can't numerically express the frequency range with only the HF[2:0] selection. For more information, please refer to HF Bits Selection. FPLL (bit D) Full range PLL If this bit is '1', the OSD_PLL block's VCO operates at full range (4.8MHz - 96MHz). If it is ’0', it operates within the region decided by the HF bit [C:A] explained above. if you can’t optimize OSD screen decided by the HF bit in the high region, you may set the FPLL bit to ‘1’. Dot1 Dot0 No. of Dots 0 0 320 dots/line 0 1 480 dots/line 1 0 640 dots/line 1 1 800 dots/line

FBLK bit setting is explained at the figure below. current. Refer to PLL control. The output is decided by the combination of these two bits. Figure 11. Character/Raster Signal Part

KB2502 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS Preliminary Tabel 4. Register Description (Continued) Registers Bits Description Frame Control Registers - 2 (Row 15, Column 02) VP7 ~ VP0 Vertical start position control ( = VP[7:0] × 4) Signifies top margin height from the V-Sync reference edge. HP7 ~ HP0 Horizontal start position control ( = HP[7:0] × 6) Signifies delay of the horizontal display from the H-Sync reference edge to the character's 1st pixel location. V-AMP Control Registers - 0 (Row 15, Column 03) VC7 ~ VC0 (bit7 ~ 0) The contrast adjustment is made by contrdling simultaneously the gain of three internal variable gain amplifiers. The contrast adjustment allows to cover a typical range of 38dB. V-AMP Control Registers - 1 (Row 15, Column 04) BRT7 ~ BRT0 (bit7 ~ 0) The brightness adjustment controls to add the same black level (pedestal) to the 3-channel R/G/B signals after contrast amplifier. V-AMP Control Registers - 2 (Row 15, Column 05) RSB7 ~ RSB0 (bit7 ~ 0) R channel SUB contrast control. The SUB contrast adjustment is used to adjust the white balance, and the gain of each channel is controlled. The SUB contrast adjustment allows you to cover a typical tange of 12dB. V-AMP Control Registers - 3 (Row 15, Column 06) GSB7 ~ GSB0 (bit7 ~ 0) G channel SUB contrast control. The SUB contrast adjustment is used to adjust the white balance, and the gain of each channel is controlled. The SUB contrast adjustment allows you to cover a typical tange of 12dB. V-AMP Control Registers - 4 (Row 15, Column 07) BSB7 ~ BSB0 (bit7 ~ 0) B channel SUB contrast control. The SUB contrast adjustment is used to adjust the white balance, and the gain of each channel is controlled. The SUB contrast adjustment allows you to cover a typical tange of 12dB. V-AMP Control Registers - 5 (Row 15, Column 08) OSD7 ~ OSD0 (bit7 ~ 0) The OSD contrast adjustment is made by contrdling simultaneously the gain of three internal variable gain amplifiers. The OSD contrast adjustment allows to cover a typical range of 38dB. V-AMP Control Registers - 6 (Row 15, Column 09) RWB7 ~ RWB0 (bit7 ~ 0) R channel cut-off control. The cut-off adjustment is used to adjust the raster white balance. V-AMP Control Registers - 7 (Row 15, Column 10) GWB7 ~ GWB0 (bit7 ~ 0) G channel cut-off control. The cut-off adjustment is used to adjust the raster white balance.

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary V-AMP Control Registers - 8 (Row 15, Column 11) BWB7 ~ BWB0 (bit7 ~ 0) B channel cut-off control. The cut-off adjustment B used to adjust the raster white balance. V-AMP Control Registers - 9 (Row 15, Column 12) CUT7 ~ CUT0 (bit7 ~ 0) The cut-off brightness adjustment is made by simultaneously controlling the external cut-off current. V-AMP Control Registers - 10 (Row 15, Column 13) HT (bit 0) Video & OSD half tone enable. If you set this bit to ’1’, the half tone function is on. Then you can see the video signal & OSD raster. HS3 ~ HS1 (bit3 ~ 1) HS3 ~ HS1 bits select OSD raster color 1 to be half tone. To carry out half tone function, set the HT bit to ’1’. HS6 ~ HS4 (bit6 ~ 4) HS6 ~ HS4 bits select OSD raster color 2 to be half tone. To carry out half tone function, set the HT bit to ’1’. SB (bit 7) Soft blanking enable If you set this bit ’1’, the R/G/B outputs go to GND. Tabel 4. Register Description (Continued) Registers Bits Description HS3 HS2 HS1 OSD Raster Color 1 POR G R B 0 0 0 0 0 0 Black O 0 0 1 0 0 1 Blue 0 1 0 0 1 0 Red 0 1 1 0 1 1 Magenta 1 0 0 1 0 0 Green 1 0 1 1 0 1 Cyan 1 1 0 1 1 0 Yellow 1 1 1 1 1 1 White HS6 HS5 HS4 OSD Raster Color 2 POR G R B 0 0 0 0 0 0 Black O 0 0 1 0 0 1 Blue 0 1 0 0 1 0 Red 0 1 1 0 1 1 Magenta 1 0 0 1 0 0 Green 1 0 1 1 0 1 Cyan 1 1 0 1 1 0 Yellow 1 1 1 1 1 1 White

KB2502 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS Preliminary V-AMP Control Registers - 11 (Row 15, Column 14) CS2 ~ CS1 (bit1 ~ bit0) Cut-off offset current control BPW2 ~ BPW1 (bit4 ~ bit3) Generated clamp pulse width control To carry out this function, set the CLPS bit to " 0 " BLKP (bit 5) Polarity of horizontral fly back signal If this bit is ’0’, HFLB’s polarity is negative, and if ’1’, it is positive. CLPP (bit 6) Polarity of clamp pulse signal If this bit is ’0’, CLP’s polarity is positive, and if ’1’, it is negative. This bit has meaning only if the CLPS bit is set to ’1’. CLPS (bit 7) Clamp pulse generation enable If this bit is ’0’, clamp signal is made using the HFLB signal, so there is no need to supply the clamp signal. and if ’1’ you must supply external clamp signal. V-AMP Control Registers - 12 (Row 15, Column 15) HS9 ~ HS7 (bit2 ~ bit 0) HS9 ~ HS7 bits select OSD raster color 3 to be half tone. To carry out half tone function, set the HT bit to " 1 ". Tabel 4. Register Description (Continued) Registers Bits Description CS2 CS1 Cut-off Offset Current POR 0 0 0 O 0 1 50 µA 1 0 100 µA 1 1 150 µA BPW2 BPW1 Width POR 0 0 0.33 µs 0 1 0.66 µs 1 0 1.00 µs O 1 1 1.33 µs HS9 HS8 HS7 OSD Raster Color 3 POR G R B 0 0 0 0 0 0 Black O 0 0 1 0 0 1 Blue 0 1 0 0 1 0 Red 0 1 1 0 1 1 Magenta 1 0 0 1 0 0 Green 1 0 1 1 0 1 Cyan 1 1 0 1 1 0 Yellow 1 1 1 1 1 1 White

In normal status, you must set TST bit to ’0’. Table 12. Video AMP Part Address Map

KB2502 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS Preliminary Contrast Register (SUB ADRS: 03H) (Vin = 0.7Vpp, bright: 80H, subcont: FFH) Brightness Register (3-ch) (SUB ADRS: 04H) (cont: 80H, subcont: 80H) SUB Contrast Register (R/G/B-ch) (SUB ADRS: 05/06/07H) (Vin = 0.7Vpp, bright: 40H, cont: FFH) OSD Contrast Register (SUB ADRS: 08H) (VOSD = TTL, bright: 80H, subcont: 80H) Hex B7 B6 B5 B4 B3 B2 B1 B0 Contrast (Vpp) Gain (dB) int. Value (Hex) 00 0 0 0 0 0 0 0 0 0 - 80 1 0 0 0 0 0 0 0 2.85 - O FF 1 1 1 1 1 1 1 1 5.2 - Increment/bit 0.0223 Hex B7 B6 B5 B4 B3 B2 B1 B0 Brightness (Vpp) Int. Value (Hex) 00 0 0 0 0 0 0 0 0 0.2 80 1 0 0 0 0 0 0 0 1.5 O FF 1 1 1 1 1 1 1 1 2.7 Increment/bit 0.01055 Hex B7 B6 B5 B4 B3 B2 B1 B0 SUB Contrast (Vpp) Gain (dB) Int. Value (Hex) 00 0 0 0 0 0 0 0 0 - 80 1 0 0 0 0 0 0 0 - O FF 1 1 1 1 1 1 1 1 - Increment/bit Hex B7 B6 B5 B4 B3 B2 B1 B0 OSD Contrast (Vpp) Gain (dB) Int. Value (Hex) 00 0 0 0 0 0 0 0 0 0 - 80 1 0 0 0 0 0 0 0 3.2 - O FF 1 1 1 1 1 1 1 1 6.4 - Increment/bit 0.025

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary Cut-Off Brightness Register (3-ch) (SUB ADRS: 0CH) Cut-Off Register (R/G/B-ch) (SUB ADRS: 09/0A/0BH) (cont = 80H, subcont: 80H) Hex B7 B6 B5 B4 B3 B2 B1 B0 Cut-Off Brightness ( µA) Int. Value (Hex) 00 0 0 0 0 0 0 0 0 0 80 1 0 0 0 0 0 0 0 100 O FF 1 1 1 1 1 1 1 1 200 Increment/bit 0.781 Hex B7 B6 B5 B4 B3 B2 B1 B0 Cut-Off EXT ( µA) Int. Value (Hex) 00 0 0 0 0 0 0 0 0 0 80 1 0 0 0 0 0 0 0 300 O FF 1 1 1 1 1 1 1 1 600 Increment/bit 2.344

• Display RAM Structure Whereas ‘Figure 9. Memory Map of Display Registers’ showed a logical configuration, the Figure above shows a 1KByte SRAM (512 × 16 bit)'s practical and physical configuration. For facilitating internal calculations, addressing is done using exponents of 2, and the rows to the right of the 'Row Attribute Registers', excepting only IFF(255), are 'Virtual Registers' that are not used. If you set 'Frame Control Register 0's 'Erase' bit to '1', 480 areas are erased (excepting only the 16th line) in the Figure above, and the 'Erasing Time' is measured with 480 areas as the standard.

Figure 12. Display RAM Structure & Monitor Display Position

• ROM Fonts KB2502 provides 448 Rom fonts for displaying OSD Icons, which allows the use of multi-language OSD Icons. Font $000 is reserved for blank data.

Figure 13. Composition of the ROM Fonts

1 C $1 C0 $1 C1 $1 CE $1 CF

KB2502 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS Preliminary COLORING If you have an Intensity feature, the number of possible colors you can express becomes doubled. In other words, the number of colors you can represent with three colors blue, green, and red is 8 ( = 2 3 ), but with the intensity feature, it is 16 ( = 2 4 ).

• Character Color Character color is assinged for each font, and the 4 components for expressing a color are listed below.
• Raster Color According to the 'BOXE' bit setting, raster color can be assigned in units of font or row. There is a trade-off in either case. If 'BOXE' Bit is set to '1', the box drawing feature can be carried out in units of font, but the raster color can only be assigned in units of row. On the other hand, if 'BOXE' bit is set to '0', the box drawing feature can't be carried out, but you can assign raster color in units of font. Blue Character & attribute register's B bit[C] Green Character & attribute register's G bit[B] Red Character & attribute register's R bit[A] Intensity Character & attribute register's BLINK/FINT bit[9] Row attribute register's INTE bit[D] Row attribute register's CINT bit[4] If all 3 bits are set to '1', the character intensity feature is enabled. Blue Row attribute register's RB bit[8] if the row attribute register's 'BOXE' bit is '1', and character & attribute register's 'BINV' bit[F] if BOXE' bit is '0'. Green Row attribute register's RG bit[7] if row attribute register's 'BOXE' Bit is '1', and character & attribute register's 'BOX1' bit[E] if 'BOXE' bit is '0'. Red Row attribute register's RR bit[6] if row attribute register's 'BOXE' bit is '1', and character & attribute register's 'BOX0' bit[D] if 'BOXE' bit is '0'. Intensity Character & attribute register's BLINK/FINT bit[9] Row attribute register's INTE bit[D] Row attribute register's RINT bit[5] If all 3 bits are set to '1', the raster intensity feature is enabled. Notes for When Making KB2502 Fonts Address 000h is appointed as blank data. RAM's initial values are all 0, and all bits are written as 0 when you erase the RAM, so blank data means the initial value. In other words, blank data means 'do nothing'. You don't need to write any data for the space font, except for 000h. It just needs to be an undotted area.

• Character Height Whereas the purpose of VZ[1:0] (Vertical Character Height) is to adjust the character's absolute size, the purpose of CH[5:0] (Character Height) is to output a uniformly sized OSD even if the resolution changes. To express a Character Height of CH = 18 ~ CH = 63 after receiving CH[5:0]'s input from the frame control register-1, decide on each line's repeating number (Standard Height CH = 18) and repeat the lines. The following Figure shows two examples of a height-controlled character. height control is carried out by repeating some of the lines.

Figure 16. Character Height

Repeating line-number can be found by the following formula.

1. If CH[5:0] is greater than 32 and less than or equal to 46 (32 < CH[5:0] ≤ 46), all lines are repeated once or

twice. The lines that are repeated twice are chosen by the following formula.

1. If CH[5:0] is greater than 46 and less than or equal to 60 (46 < CH[5:0] ≤ 60), all lines are repeated two or three

times. The lines that are repeated three times are chosen by the following formula.

1. If CH[5:0] is greater than 60 and less than or equal to 64 (60 < CH[5:0] ≤ 64), all Lines are repeated three or four

times. The lines that are repeated four times are chosen by the following formula. Table 13. Repeating Line as Controlling by CH bits

• Positioning The frame control register-2's HP Bit [F:8] signifies delay of the horizontal display from the H-Sync reference edge to the character's 1st pixel location, and is controlled by multiplying HP [F:8]'s range value by 6. Also, VP bit[7:0] signifies the top margin height from the V-Sync reference edge, and is controlled by multiplying 4 to the VP [7:0]'s range value. Refer to the Figure shown below.

Figure 17. Frame Composition with the OSD Characters

• Box Drawing Set the row attribute register's boxe bit to '1' and enable the box feature. Then set the character & attribute register's BOX bit to select one of 4 modes. Or, use the character & attribute register's BINV bit to inverse the white and black areas of the box mode selected by the BOX bit. The principle behind the boxing feature is shown below. Out of the 12 horizontal dots and 18 vertical lines that make 1 character, make the first and 12th horizontal dots to HDOT0/HDOT11, and the first and 18th vertical lines to DOTLINE-0H/DOTLINE-17H in order to carry out box drawing for 1 dot outside the character.

Figure 18. Box Drawing

• Fade-In/Fade-Out Fade-in/fade-out is displaying from the center to the outside in units of font when OSD display is on/off. Each font's display is turned on/of without regard to size, in units of (12 × 18) dot. Also, to control the fade in/out time, the V_PULSE's 1/4, 1/8 clocks are used for counting. In other words, as control data, it takes 0.5sec if the frame control register - 0's 'FdeT' bit is 1, and 1sec if 0. If it is difficult to visualize the fade-in / fade-out feature with the explanation and diagrams in this document, write the control data to the OSD IC and verify the IC's operations. Like the scrolling feature, fade in/out can only be verified when OSD is enabled/disabled.

Figure 21. Fade-In/Fade-Out

• Introduction PLL (Phase Lock Loop) is feedback controlled circuit that maintains a constant phase difference between a reference signal and an oscillator output signal. Generally, PLL is composed as follow Figure. - PFD (Phase Frequency Detector) PFD compares the phase of the VCO output frequency, with the phase of a reference signal frequency output pulse is generated in proportion to that phase difference. - LF (Loop Filter) LF smooths the output pulse of the phase detector and the resulting DC component is the VCO input. - VCO (Voltage Controlled Oscillator) VCO is controlled by loop filter output. The output of the VCO is fed back to the phase frequency detector input for comparison which in turn controls the VCO oscillating frequency to minimize the phase difference. - FD (Frequency Divider) FD divides too much different frequency that is oscillated from the VCO to compare it with reference signal frequency.

Figure 22. Block Diagram of General PLL

• PLL of the KB2502 PLL is composed of the phase detector, charge pump, VCO, and N-divider as 4 sub-blocks. The following is the description of the input/output signals. - HFLB (Input) Horizontal flyback signal is refrence signal of the PLL built in KB2502. The HFLB signal's frequency range is 15 ~ 90kHz, so the PLL block must be a wide range PLL that can cover HFLB's entire frequency range. - VCO (Input) Error signal that passes through an external loop filter is input into VCO. Operation voltage range is 1-4V. You can raise immunity towards external noise by lowering VCO sensitivity. You can do this by making it have the maximum operation voltage range possible in the 5V power voltage.

Figure 23. Block Diagram of the PLL Built in KB2502

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary - DOT0, 1 (Input) Mode control signal that controls the number of dots per line in the frame control register. There are 4 modes: 320, 480, 640, and 800 dots/line. According to your choice of mode, the OSD_PLL block's N-Divider is controlled by one of ÷ 320, ÷ 480, ÷ 640, or ÷ 800 Divider. - HF0, 1, 2 (Input) The horizontal Sync frequency information is received from the micro controller through the frame control registers-1's bit C-A. - CP0, 1 (Input) Charge Pump's output sourcing (or sinking) current control pin. This control data is received through frame control registers-1's bits E-D. - VCO_OUT (Output) VCO output that becomes a system clock. It is the OSD R, G, B output signal's dot frequency, and the standard signal for OSD's various timings. Also, it is input into the N-Divider and makes a PLL loop - CP_OUT (Output) Charge Pump circuit's output. input into external loop filter. It becomes one of 3 states according to the standard signal input into the phase detector (HFLB) and the divider output (Div_Out). - HFLB Div_Out is lead: Current sink - HFLB Lag: Current source - HFLB In-Phase: High impedence fclk < 0.4V > 4.2V Rise Time : < 4nS Fall Time : < 4nS

• PLL External Circuit You may follow the recommendations for PCB art work and input/output signal characteristic improvement in recommendation. The external circuit that has the most influence on KB2502 PLL block operation is pin 3 (VCO_IN) and pin 4 (CP_OUT)'s surrounding circuit. Refer to OSD PLL block. Because the PLL circuit is basically a feedback circuit, there are many components that influence the characteristics. C1, R1, R2, and R3 do not have a localized effect. As you can see, they are connected to the PLL control bits and influence the characteristics through their complicated relationships. The main functions of the time canstant and their reference values are as follows.

Figure 24. PLL External Circuit Table 14. Main Function of Time Constant in PLL External Circuit

• PLL Control Bit After configuring an external circuit using the recommended values, carry out programming using the recommended values for frequency range and control bits given in the Table below. (Ref: 800 × 600, C1: 562, R1: 5.6K, R2: 27K, R3: 30M)
• Locking Range As you can see the figure below, it is 2.35V that measured voltage at pin-3 to optimize OSD quality. The proper voltage range is 1.5 ~ 3.25V.

Table 15. Recommend Values of PLL Control Bit Figure 25. Locking Range

• HF Bits Selection HF bits is not selecting from out of 8 (2 3 ) steps uniformly, but selecting the step shown in figure below. In example, at 800 mode, there are 5 steps that the frequency range is controlled by HF bits. After fixing time constants of the external circuit and PLL control bits except HF bits, if HF bits are stepped up, the voltage measured at pin-3 drops. On the contrary, if HF bits are stepped down, the voltage rises. The voltage measured at pin-3 don't change by changing CP bits.
• External Register at pin-4 The external register at pin-4 is the factor that changes greatly at PLL tunning. The initial value of this external register value is decided as follows. At first, the external register is replaced variable-register (about 50K Ω range). and then, set the lowest PLL control bits at the lowest frequency allowed by set. and then, change variable-register to be 2.35V that optimum voltage is locking. and then, measure register value at this time. also, set the highest PLL control bits at the highest frequency allowed by set. and then, change variable-register to be 2.35V that optimum voltage is locking. and then, measure register value at this time. You may decide the average of these two registers' value to initial value.

Table 16. HF Bits Selection

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary The table below shows that other factors change as changing external register's value. Fixing Factor Variable Factor Change Voltage Current Lock Range Time constants of the external circuit and PLL control bits except Rext ↑ ↑ ↓ ↓ (shift) ↓ ↓ ↑ ↑ (shift)

KB2502 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS Preliminary RECOMMENDATION 5V Power Routing KB2502's OSD part power is composed of analog VDD and digital VDD. To eliminate clock noise influence in the digital block, you need to separate the analog VDDA and digital VDD. (BD102 use: Refer to Application Circuit ) 12V Power Routing Because KB2502 is a wideband AMP of above 150MHz, 12V power significantly affects the video characteristics. The effects from the inductance and capacitance are different for each board, and , therefore, some tuning is required to obtain the optimum performance. The output power, VCC2, must be separated from VCC1 and VCC3 using a coil, which is parallel-connected to the damping resistor.The appropriate coil value is between 20uH - 200uH. Parallel-connected a variable resistor to the coil and control its resistance to obtain the optimum video waveform. (Moreover, BD103 can tune using a coil and variable resistor to obtain the optimum video waveform. L103, R124, BD103: Refer to application circuit) VCC1, VCC3 12V Power Use a 104 capacitor and large capacitor greater than 470uH for the power filter capacitor. 12V Output Stage Power VCC2 Do not use the power filter capacitor. 5V Digital Power VDD Don't use a coil or magnetic core to the VDD input. Make the power filter capacitor, an electric capacitor of greater than 50uF, single and connect it to VSS, the digital GND. Output Stage GND2 Care must be taken during routing because it ,as an AMP output stage GND, is an important factor of video oscillation. R/G/B clamp cap and R/G/B load resistor must be placed as close as possible to the GND2 pin. GND2 must be arranged so that it has the minimum GND loop, which at one point must be connected to the main GND. Digital GND VSS When this is to be connected directly to the GND2, it can cause the OSD clock noise, so the loop connection should be routed as far away as possible. If the OSD clock noise affects the screen, separate VSS GND from all GND and connect it to the main board using a bead. Again, the bead connection point should be placed as far away as possible to the GND2. Analog Block The PLL built in to KB2502 is sensitive to noise due to the wide range PLL characteristics. Therefore, you need to isolate the analog block in the following manner. First make a separate land for the analog block (pin2 - pin6)'s ground, and connect it to the main ground through a 1M Ω resistor. The analog GND of both sides of a double faced PCB must be separated from the main ground. (Separate pin 2's 5V analog GND, which is the GND for OSD PLL, from the main and digital GNDs and connect it to the main GND using about 1M Ω resistor. GND for pins 2 - 6 is the No. 2 VSSA GND.)

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary I2 C Control Line (SCL, SDA Line) I2 C communication noise (noise generated in the OSD display pattern when data is transmitted in the I 2 C line) may be generated because of an I 2 C control line that passes near the analog block. The I 2 C control lines near KB2502 must be separated from the analog block as much as possible. Furthermore, the I 2 C bus interference can be prevented by inserting a series resistor in the line. Horizontal Flyback Signal Display jittering can be generated if the horizontal signal (HFLB) input to KB2502 is not a clean signal. We recommend a short path and shielded cable for obtaining a clean signal. Generally, the input horizontal signal (HFLB) is generated by using a high voltage horizontal flyback signal. The effect from the high voltage flyback signal can be reduced by separating the R115 and R117 GND, which determines the flyback signal slice level, from the transistor GND, which generates the actual KB2502 input horizontal signal. Furthermore, the flyback signal sharpness must be maintained by minimizing the values of R115, R116 and R117 resistors, which set the horizontal signal slice level. values. (R115, R116, R117: Refer to application circuit ) HFLB Input Signal Generator You can correct the circuit by reducing the resistors that sets the slice level of the horizontal signal in the HFLB- generating circuit.

Figure 26. Application Board Circuit

100 CR08

100 CG08

56 CB07

56 CR07

Figure 27. Typical Application Circuit

Figure 28. ROM Fonts

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary

KB2502 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS Preliminary

VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS KB2502 Preliminary