K5P2880YCM SAMSUNG | Alldatasheet

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Revision 0.0 June. 2001- 1 - Document Title Multi-Chip Package MEMORY 128M Bit (16Mx8) Nand Flash Memory / 8M Bit (1Mx8/512Kx16) Full CMOS SRAM

Revision History

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you ha ve any questions, please contact the SAMSUNG branch office near you. Revision No. 0.0 Remark Advanced Information History Initial issue. Draft Date Jun. 11th 2001 Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site. http://samsungelectronics.com/semiconductors/products/products_index.html

Revision 0.0 June. 2001- 2 - Multi-Chip Package MEMORY 128M Bit (16Mx8) Nand Flash Memory / 8M Bit (1Mx8/512Kx16) Full CMOS SRAM The K5P2880YCM featuring single 3.0V power supply is a Multi ChipPackage Memory which combines 128Mbit Nand Flash and 8Mbit full CMOS SRAM. The 128Mbit Flash memory is organized as 16M x8 bit and the 8Mbit SRAM is organized as 1M x8 or 512K x16 bit. In 128Mb NAND Flash a 528-byte page program can be typically achieved within 300us and an 16K-byte block erase can be typically achieved within 2ms. In serial read operation, a byte can be read by 50ns. The I/O pins serve as the ports for address and data input/output as well as command inputs. Even the write-intensive systems can take advantage of the FLASH ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correct- ing Code) with real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ECC. The 8Mbit SRAM sup- ports the low data retention voltage for battery backup operation with low current. The K5P2880YCM is suitable for use in data memory of mobil communication system to reduce not only mount area but also power consumption. This device is available in 69-ball TBGA Type.

FEATURES

  • Power Supply voltage : 2.7V to 3.3 V
  • Organization - Flash : (16M + 512K)bit x 8bit - SRAM : 1M x 8 / 512K x 16 bit
  • Access Time - Flash : Random access : 10us(Max.), Serial read : 50ns(Min.) - SRAM : 85 ns
  • Power Consumption (typical value) - Flash Read Current : 10 mA(@20MHz) Program/Erase Current : 10 mA Standby Current : 10 µA - SRAM Operating Current : 20 mA Standby Current : 0.5 µA
  • Flash Automatic Program and Erase Page Program : (512 + 16)Byte Block Erase : (16K + 512)Byte
  • Flash Fast Write Cycle Time Program time : 300us(Typ.) Block Erase Time : 2ms(Typ.)
  • Flash Endurance : 100,000 Program/Erase Cycles Minimum
  • Flash Data Retention : 10 years
  • SRAM Data Retention : 1.5 V (min.)
  • Operating Temperature : -25 °C ~ 85 °C
  • Package : 69 - ball TBGA Type - 8 x 13mm, 0.8 mm pitch GENERAL DESCRIPTION SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. BALL CONFIGURATION Ball Name Description A 0 to A 18 Address Input Balls (SRAM) D/Q 0 to D/Q 7 Data Input/Output Balls (Common) D/Q 8 to D/Q 15 Data Input/Output Balls (SRAM) Vccs Power Supply (SRAM) Vcc F Power Supply (Flash Memory) VccQ F Output Buffer Power (Flash Memory) This input may be tied directly to V CCF . Vss Ground (Common) UB Upper Byte Enable (SRAM) LB Lower Byte Enable (SRAM) WP Write Protection (Flash Memory) CLE Command Latch Enable(Flash Memory) ALE Address Latch Enable(Flash Memory) BYTE S Byte Control (SRAM) SA Address Inputs (SRAM) CE F Chip Enable (Flash Memory) CS 1 S Chip Enable (SRAM Low Active) CS2 S Chip Enable (SRAM High Active) WE Write Enable (Common) OE /RE Output Enable (Common) R/ B Ready/Busy (Flash memory) N.C No Connection A 7 U B A 8 A 3 A 6 C E f L B C S 2 s N .C A 2 A 5 A 1 8 A L E N .C A 9 A 4 D Q 6 W P O E /R E D Q 9 D Q 3 D Q 4 D Q 1 3 1 2 3 4 5 6 A B C D E F C L E W E V S S A 1 0 D Q 1A 0 A 1 A 1 7 A 1 1 A 1 2 A 1 5 A 1 3 N .C A 1 4 S A A 1 6 R /B 7 8 V c c f D Q 8 D Q 2 D Q 1 1 D Q 5 H D Q 1 4 C S 1 s D Q 0 D Q 1 0 V c c Q F V c c S D Q 1 2 G D Q 7 V s s B Y T E S D Q 1 5 N .C N .C N .CN .CN .C N .C N .C N .C N .C N .C N .CN .C In d e x 9 1 0 K J BALL DESCRIPTION 69 Ball TBGA , 0.8mm Pitch Top View (Ball Down)

Figure 1. FUNCTIONAL BLOCK DIAGRAM NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register.

  • A 8 is set to "Low" or "High" by the 00h or 01h Command.

512 Bytes

16 Bytes

1 Block =32 Pages

1 Page = 528 Bytes

1 Block = 528 Bytes x 32 Pages

1 Device = 528 Bytes x 32Pages x 1024 Blocks

Figure 2. Flash ARRAY ORGANIZATION

128 M bit

8 M bit

Table 1. COMMAND SETS NOTE : 1. The 00h command defines starting address of the 1st half of registers. The 01h command defines starting address of the 2nd half of registers. automatically moved to the 1st half register(00h) on the next cycle. except Page Program command and Block Erase command which require two cycles: one cycle for setup and another for execution. by writing specific commands into command register. Table 1 defines the specific commands of the NAND Flash.

Table 2. FLASH MEMORY OPERATIONS TABLE NOTE : 1. X can be V IL or V IH.

  1. WP should be biased to CMOS high or CMOS low for standby.

Table 3. SRAM OPERATIONS TABLE

  1. Address input for byte operation.

command mode until another valid command is written to the command register. Figure 5. Program & Read Status Operation

528 Byte Data

Figure 4. Read2 Operation

Figure 9. AC Waveforms for Power Transition operation and the value may be calculated by the following equation.

intentional erasure of the original invalid block information is prohibited. Figure 10. Flow chart to create invalid block table

Figure 11. Flash Program flow chart target data to another block. failure rate does not include those reclaimed blocks. ECC : Error Correcting Code --> Hamming Code etc.

shows the block diagram of its operations. Table 6. Destination of the pointer Table 7. Pointer Status after each operation

  • 01h command is valid just one time when it is used as a pointer for program/erase.
  • Erase operation does not affect the pointer status. Previous pointer status is maintained.

256 Byte

256 Byte 16 Byte

Figure 15. Block Diagram of Pointer Operation

Revision 0.0 June. 2001- 16 - RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, T A =-25 to 85 °C) Parameter Symbol Min Typ. Max Unit Supply Voltage V CCf, V CCs 2.7 3.0 3.3 V Supply Voltage V CCQ 2.7 3.0 3.3 V Supply Voltage V SS 0 0 0 V ABSOLUTE MAXIMUM RATINGS NOTE : Maximum DC voltage on input/output pins is V CCQ +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended peri ods may affect reliability. Parameter Symbol Rating Unit Voltage on any pin relative to V SS V IN -0.5 to (Vccf,Vccs)+ 0.3 V V CCf, V CCs -0.2 to 3.6V V VccQ -0.2 to 3.6V Temperature Under Bias T BIAS -25 to + 125 Storage Temperature T STG -65 to + 150 °C DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI V CCf, V CCS= V CCf Max. ,V CCS Max. V CCQf= V CCQf Max.,V IN= V CCQf or GND - ±10 µA Output Leakage Current ILO V CCf, V CCS= V CCf Max. ,V CCS Max. V CCQf= V CCQf Max.,V IN= V CCQf or GND - ±10 µA Input Low Voltage Level, All inputs V IL -0.4 0.4 V Input High Voltage Level V IH VccQf-0.4 VccQf+0.4 Output Low Voltage Level V OL Vccf/=Vccf Min, Vccs=Vccs Min I OL = 0.1mA - 0.4 Output High Voltage Level V OH Vccf=Vccf Min, Vccs=Vccs Min. I OH = -0.1mA VccQ-0.3 -

Revision 0.0 June. 2001- 17 - DC AND OPERATING CHARACTERISTICS (Continued) Parameter Symbol Test Conditions Typ Max Unit Flash Active Sequential Read Currnt ICC 1f tRC=50ns, CEf =V IL , I OUT =0mA V CCf= V CCf Max,V CCQf= V CCQf Max 10 20 mA Active Program Current ICC 2f V CCf= V CCf Max,V CCQf= V CCQf Max 10 20 mA Active Erase Current ICC 3f V CCf= V CCf Max,V CCQf= V CCQf Max 10 20 mA Stand_by Current ISB 2f CEf =VccQf, WP =0V/V CCQf 10 50 µA SRAM Operating Current ICC 1s Cycle time=1 µs, 100% duty, CS 1s ≤0.2V, CS2s ≥Vcc S -0.2V, All outputs open V IN ≤0.2V or V IN ≥V CCS -0.2V 5 mA ICC 2s Cycle time=Min, 100% duty, CS 1s=V IL , CS2s=V IH All outputs open, V IN =V IL or V IH 30 mA Stand_by Current(CMOS) ISB 2s CS 1s ≥Vcc S -0.2V, CS2s ≥Vcc S -0.2V ( CS 1s controlled) or CS2s ≤0.2V (CS2s controlled), BYTE S =V SS or V CCS Other input =0~Vcc S 15 µA CAPACITANCE (T A = 25 °C, V CC = 3.0V, f = 1.0MHz) Note : Capacitance is periodically sampled and not 100% tested. Item Symbol Test Condition Min Max Unit Input/Output Capacitance C I/O V IL =0V - 20 pF Input Capacitance C IN V IN =0V - 18 pF VALID BLOCK OF FLASH MEMORY NOTE : 1. The Flash memory may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits . Do not try to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block. Parameter Symbol Min Typ. Max Unit Valid Block Number N VB 1014 1020 1024 Blocks

Revision 0.0 June. 2001- 18 - AC TEST CONDITION Note : AC test inputs are driven at VccQ for a logic "1" and 0.0V for a logic "0". Input timing begins, and output timing ends, at V ccQ / 2. Input rise and fall times (10% - 90%)<5ns. Worst case speed condition are when VccQf = VccQf Min. Parameter Value Input Pulse Levels 0V to VccQf Input Rise and Fall Times 5ns Input and Output Timing Levels VccQf/2 Output Load 1TTL gate and C L = 50pF VccQf VccQf Input Pulse and Test Point Input & Output Test Point 2 VccQf Device Under Test C L 25K 25K Out VccQ

Revision 0.0 June. 2001- 19 - Flash AC Timing Characteristics for Command / Address / Data Input Parameter Symbol Min Max Unit CLE Set-up Time tCLS 0 - ns CLE Hold Time tCLH 10 - ns CE Setup Time tCS 0 - ns CE Hold Time tCH 10 - ns WE Pulse Width tWP 25 - ns ALE Setup Time t ALS 0 - ns ALE Hold Time tALH 10 - ns Data Setup Time tDS 20 - ns Data Hold Time tDH 10 - ns Write Cycle Time tWC 50 - ns WE High Hold Time tWH 15 - ns Flash Program/Erase Characteristics Parameter Symbol Min Typ Max Unit Program Time tPROG - 300 600 µs Number of Partial Program Cycles in the Same Page Main Array Nop - - 2 cycles Spare Array - - 3 cycles Block Erase Time tBERS - 2 4 ms Flash AC Characteristics for Operation NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us Parameter Symbol Min Max Unit Data Transfer from Cell to Register tR - 10 µs ALE to RE Delay( ID read ) t AR1 20 - ns ALE to RE Delay(Read cycle) t AR2 50 - ns CE Access Time tCEA - 45 ns Ready to RE Low tRR 20 - ns RE Pulse Width t RP 30 - ns WE High to Busy tWB - 100 ns Read Cycle Time tRC 50 - ns RE Access Time tREA - 35 ns RE High to Output Hi-Z tRHZ 15 30 ns CE High to Output Hi-Z tCHZ - 20 ns RE High Hold Time t REH 15 - ns Output Hi-Z to RE Low t IR 0 - ns WE High to RE Low tWHR 60 - ns Device Resetting Time (Read/Program/Erase) tRST - 5/10/500 (1) µs

Revision 0.0 June. 2001- 20 - * Command Latch Cycle CE WE CLE ALE I/O 0 ~ 7 Command tCLS tCS tCLH tCH tWP tALS tALH tDS tDH * Address Latch Cycle CE WE CLE ALE I/O 0 ~ 7 A 0 ~A 7 tCLS tCS tWC tWP tALS tDS tDH tALH tALS tWH A 9 ~A 16 tWC tWP tDS tDH tALH tALS tWH A 17 ~A 23 tWP tDS tDH tALH

Revision 0.0 June. 2001- 21 - * Input Data Latch Cycle CE CLE WE I/O 0 ~ 7 DIN 0 DIN 1 DIN 511 ALE tALS tCLH tWC tCH tDS tDH tDS tDH tDS tDH tWP tWH tWP tWP * S equential Out Cycle after Read (CLE=L, WE =H, ALE=L) RE CE R/ B I/O 0 ~ 7 Dout Dout Dout tRC tREA tRR tRHZ* tREA tREH tREA tCHZ* tRHZ* ≈≈≈≈ NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested.

Revision 0.0 June. 2001- 22 - * Status Read Cycle CE WE CLE RE I/O 0 ~ 7 70h Status Output tCLS tCLH tCS tWP tCH tDS tDH tREA tIR tRHZ tCHZ tWHR tCEA tCLS READ1 OPERATION (READ ONE PAGE) CE CLE R/ B I/O 0 ~ 7 WE ALE RE Busy 00h or 01h A 0 ~ A 7 A 9 ~ A 16 A 17 ~ A 23 Dout N Dout N+1 Dout N+2 Dout N+3 Column Address Page(Row) Address tWB tAR2 tR tRC tRHZ tCHZ Dout 527 tWC tRR ≈≈≈

Revision 0.0 June. 2001- 23 - READ2 OPERATION (READ ONE PAGE) CE CLE R/ B I/O 0 ~ 7 WE ALE RE 50h A 0 ~ A 7 A 9 ~ A 16 A 17 ~ A 23 Dout Dout 527 M Address A 0 ~ A 3 :Valid Address A 4 ~ A 7 :Dont care 511+M Dout 511+M+1 tAR2 tR tWB tRR Selected Row Start address M 512 16 PAGE PROGRAM OPERATION CE CLE R/ B I/O 0 ~ 7 WE ALE RE 80h 70h I/O 0 Din N Din Din 10h527N+1A 0 ~ A 7 A 17 ~ A 23A 9 ~ A 16 Sequential Data Input Command Column Address Page(Row) Address 1 up to 528 Byte Data Sequential Input Program Command Read Status Command I/O 0 =0 Successful Program I/O 0 =1 Error in Program tPROGtWB tWC tWC tWC

Revision 0.0 June. 2001- 24 - MANUFACTURE & DEVICE ID READ OPERATION CE CLE I/O 0 ~ 7 WE ALE RE 90h Read ID Command Maker Code Device Code 00h ECh 73h tREA Address 1st Cycle BLOCK ERASE OPERATION (ERASE ONE BLOCK) CE CLE R/ B I/O 0 ~ 7 WE ALE RE 60h A 17 ~ A 23A 9 ~ A 16 Auto Block Erase Erase Command Read Status Command I/O 0 =1 Error in Erase DOh 70h I/O 0 Busy tWB tBERS I/O 0 =0 Successful Erase Page(Row) Address tWC Setup Command

Revision 0.0 June. 2001- 25 - SRAM DATA RETENTION CHARACTERISTICS 2. Typical values are not 100% tested Item Symbol Test Condition Min Typ Max Unit Vccs for data retention V DR CS 1s ≥Vccs-0.2V 1) 1.5 - 3.3 V Data retention current IDR Vccs=3.0V, CS 1s ≥Vccs-0.2V 1) 25 °C - 2.0 2) 5 µA 85 °C - 25 Data retention set-up time tSDR See data retention waveform 0 - - ns Recovery time tRDR tRC - - SRAM AC CHARACTERISTICS Parameter List Symbol 85ns Units Min Max Read Read cycle time tRC 85 - ns Address access time t AA - 85 ns Chip select to output tCO1 , t CO2 - 85 ns Output enable to valid output tOE - 45 ns UB , LB Access Time t BA - 85 ns Chip select to low-Z output tLZ1 , t LZ2 10 - ns UB , LB enable to low-Z output tBLZ 10 - ns Output enable to low-Z output tOLZ 5 - ns Chip disable to high-Z output tHZ1 , t HZ2 0 25 ns UB , LB disable to high-Z output tBHZ 0 25 ns Output disable to high-Z output tOHZ 0 25 ns Output hold from address change t OH 15 - ns Write Write cycle time t WC 85 - ns Chip select to end of write t CW 70 - ns Address set-up time t AS 0 - ns Address valid to end of write tAW 70 - ns UB , LB Valid to End of Write tBW 70 - ns Write pulse width tWP 60 - ns Write recovery time t WR 0 - ns Write to output high-Z tWHZ 0 25 ns Data to write time overlap t DW 35 - ns Data hold from write time tDH 0 - ns End write to output low-Z tOW 5 - ns

Revision 0.0 June. 2001- 26 - SRAM TIMMING DIAGRAMS Address Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled , CS 1 S = OE =V IL , CS 2 S = WE =V IH , UB or/and LB =V IL ) TIMING WAVEFORM OF READ CYCLE(2) ( WE =V IH , if CIOs is low, ignore UB /LB timing) Data ValidHigh-Z tRC CS 1 S Address UB , LB OE Data out tAA t RC tOH t OHtAA tCO1 t BA tOE tOLZ tBLZ t LZ tOHZ tBHZ tHZ NOTES (READ CYCLE) 1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection. CS2 S tCO2

Revision 0.0 June. 2001- 27 - SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF WRITE CYCLE(1) ( WE Controlled, if CIOs is low, ignore UB /LB timing) Address CS 1 S Data Undefined UB , LB WE Data in Data out TIMING WAVEFORM OF WRITE CYCLE(2) ( CS 1 S Controlled, if CIOs is low, ignore UB /LB timing) Address Data Valid UB , LB WE Data in Data out High-Z High-Z tWC t CW(2) t WR(4) t AW tBW tWP(1) tAS(3) tDHt DW tWHZ tOW t WC tCW(2) tAW tBW tWP(1) tDHt DW tWR(4) High-Z High-ZData Valid tAS(3) CS 2 S CS 1 S CS 2 S t CW(2)

Revision 0.0 June. 2001- 28 - Address Data Valid UB , LB WE Data in Data out High-Z High-Z TIMING WAVEFORM OF WRITE CYCLE(3) ( UB , LB Controlled, CIOs must be high.) NOTES (WRITE CYCLE) 1. A wri te occurs during the overlap(t WP ) of low CS 1 S and low WE . A write begins when CS 1 S goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran- sition when CS 1 S goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS 1 S going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS 1 S or WE going high. tWC tCW(2) tBW tWP(1) t DHtDW tWR(4) tAW SRAM DATA RETENTION WAVE FORM CS 1 S controlled V CCS 2.4V 2.2V V DR CS 1 S GND Data Retention Mode CS 1 S ≥V CCS - 0.2V tSDR tRDR tAS(3) CS 1 S CS 2 S CS 2 S controlled V CCS 2.4V 0.4V V DR CS 2 S GND Data Retention Mode t SDR tRDR CS 2 S ≤0.2V tCW(2)

Revision 0.0 June. 2001- 29 - PACKAGE DIMENSION 69-Ball Tape Ball Grid Array Package (measured in millimeters) Top View #A1 8.00 ± 0.10 1 3 .0 0 ± 0 .1 0 Bottom View 14 27 6 5 38 A B C E G D F H 0.80 0.80 x9=7.20 A 0 .8 0 x 9 = 7 . 2 0 1 3 .0 0 ± 0 .1 0 3.60 69- ∅ 0.45 ± 0.05 A1 INDEX MARK 910 J K 3 .6 0 0 .8 0 B 8.00 ± 0.10

0.20 M A B ∅

(Datum A) (Datum B) Side View 13.00 ± 0.10 0.45 ± 0.05 0.08MAX 0 .3 5 ± 0 .0 5 1 .1 0 ± 0 .1 0