K5L5628JBM

K5L5628JTM SAMSUNG | Alldatasheet

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Technical content

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Document Title Multi-Chip Package MEMORY 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

Revision History

Revision No. 0.0 1.0 Remark Preliminary Final History Initial Draft (256M NOR Flash A-die_rev0.3) (128M UtRAM M-die_rev0.1) Finalize - Deleted Synchronous Burst Read and Asynchronous Write Mode Draft Date August 12, 2004 November 10, 2004 The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site. http://samsungelectronics.com/semiconductors/products/products_index.html

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Multi-Chip Package MEMORY 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

FEATURES

<Common>

• Operating Temperature : -30°C ~ 85°C
• Package : 115Ball FBGA Type - 8.0mm x 12.0mm 0.8mm ball pitch 1.4mm (Max.) Thickness <NOR Flash>
• Single Voltage, 1.7V to 1.95V for Read and Write operations
• Organization - 16,772,216 x 16 bit ( Word Mode Only)
• Read While Program/Erase Operation
• Multiple Bank Architecture - 16 Banks (16Mb Partition)
• OTP Block : Extra 256Byte block
• Read Access Time (@ C L=30pF) - Asynchronous Random Access Time : 90ns (54MHz) / 80ns (66MHz) - Synchronous Random Access Time : 88.5ns (54MHz) / 70ns (66MHz) - Burst Access Time : 14.5ns (54MHz) / 11ns (66MHz)
• Burst Length : - Continuous Linear Burst - Linear Burst : 8-word & 16-word with No-wrap & Wrap
• Block Architecture - Eight 4Kword blocks and five hundreds eleven 32Kword blocks - Bank 0 contains eight 4 Kword blocks and thirty-one 32Kword blocks - Bank 1 ~ Bank 15 contain four hundred eighty 32Kword blocks
• Reduce program time using the V PP
• Support Single & Quad word accelerate program
• Power Consumption (Typical value, CL=30pF) - Burst Access Current : 30mA - Program/Erase Current : 15mA - Read While Program/Erase Current : 40mA - Standby Mode/Auto Sleep Mode : 25uA
• Block Protection/Unprotection - Using the software command sequence - Last two boot blocks are protected by WP =VIL - All blocks are protected by VPP=VIL
• Handshaking Feature - Provides host system with minimum latency by monitoring RDY
• Erase Suspend/Resume
• Program Suspend/Resume
• Unlock Bypass Program/Erase
• Hardware Reset (RESET
• Data Polling and Toggle Bits - Provides a software method of detecting the status of program or erase completion
• Endurance 100K Program/Erase Cycles Minimum
• Data Retention : 10 years
• Support Common Flash Memory Interface
• Low Vcc Write Inhibit <UtRAM>
• Process Technology: CMOS
• Organization: 8M x16 bit
• Power Supply Voltage: VCC 2.5~2.7V, VCCQ 1.7~2.0V
• Three State Outputs
• Supports MRS (Mode Register Set)
• MRS control - MRS Pin Control
• Supports Power Saving modes - Partial Array Refresh mode Internal TCSR
• Supports Driver Strength Optimization for system environment power saving.
• Supports Asynchronous 4-Page Read and Asynchronous Write Operation
• Supports Synchronous Burst Read and Synchronous Burst Write Operation
• Synchronous Burst(Read/Write) Operation - Supports 4 word / 8 word / 16 word and Full Page(256 word) burst - Supports Linear Burst type & Interleave Burst type - Latency support : Latency 3 @ 52.9MHz(tCD 12ns) - Supports Burst Read Suspend in No Clock toggling - Supports Burst Write Data Masking by /UB & /LB pin control - Supports WAIT pin function for indicating data availability.
• Max. Burst Clock Frequency : 52.9MHz SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary The K5L5628JT(B)M is a Multi Chip Package Memory which comb ines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory and 128Mbit Synchronous Burst UtRAM. 256Mbit Synchronous Burst Multi Bank NOR Flash Memory is organized as 16M x1 6 bits and 128Mbit Synchronous Burst UtRAM is organized as 8M x16 bits. In 256Mbit Synchronous Burst Multi Bank NOR Flash Memory, the memory architecture of the device is designed to divide its memory arrays into 519 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capa- bility. The NOR Flash consists of sixteen banks. This device is capable of reading data from one bank while programming or eras ing in the other bank. Regarding read access time, the device provides an 14.5ns burst access time and an 88.5ns initial access time at 54MHz. At 66MHz, the device provides an 11ns burst access time and 70ns initial access time. The dev ice performs a program operation in units of 16 bits (Word) and an erase operation in units of a block. Single or multiple blocks can be erased. The block erase operation is c om- pleted within typically 0.7 sec. The device requires 15mA as program/erase current. In 128Mbit Synchronous Burst U tRAM, the device is fabricated by SAMSUNG ′s advanced CMOS technology using one transistor memory cell. The device supports the traditional SRAM like asynchronous bus operation(asynchronous page read and asynchronous write), and the fully synchronous bus operation(synchronous burst read and synchronous burst write). These two bus operation modes are defined through the mode register setting. The device al so supports the special features for the standby power saving . Those are the Partial Array Refresh(PAR) mode and internal Temperature Compensated Self Refresh(TCSR) mode. The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. The K5L5628JT(B)M is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 115-ball FBGA Type. GENERAL DESCRIPTION

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary PIN CONFIGURATION 115-FBGA: Top View (Ball Down) 123456 A B C D E F G H CLKuADVuVccuNCCLKfNCADVf A11A8WEVppLBWPDNU A12A19MRSA6A3 A13A9A20A5A2 A14A10NCA4A1DNU A23DQ6NCVssA0DNU DQ15DQ13DQ4OECEf DQ7DQ12VccquVccfDQ10DQ0CSu J K DQ14DQ5NCDQ11DQ2DQ8NC UB RESET A18 RDYf/ A17 NC DQ1 Vccu DQ9 DQ3 91 0 NC NC A15 A21 A22 A16 NC Vss NC DNU DNU DNU L M NCNCNCVccfVssNCNCDNU NC DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU DNUDNU DNU DNU DNUDNU DNU DNU DNUDNU DNUDNU DNU DNU DNU DNU N P WAITu

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary PIN DESCRIPTION Ball Name Description Ball Name Description A0 to A22 Address Input Balls (Common) RDYf/WAIT u Ready Output (Flash Memory)/Wait(U tRAM) A23 Address Input Balls (Flash Memory) ADV f Address Input Valid (Flash Memory) DQ0 to DQ15 Data Input/Output Balls (Common) ADV u Address Input Valid (U tRAM) CEf Chip Enable (Flash Memory) MRS Mode Register Set (UtRAM) CSu Chip Select (U tRAM) LB Lower Byte Enable (UtRAM) OE Output Enable (Common) UB Upper Byte Enable (UtRAM) RESET Hardware Reset (Flash Memory) Vccf Power Supply (Flash Memory) VPP Accelerates Programming (Flash Memory) Vccu Power Supply (U tRAM) WE Write Enable (Common) Vccqu Data Out Power (U tRAM) WP Write Protection (Flash Memory) Vss Ground (Common) CLKf Clock (Flash Memory) NC No Connection CLKu Clock (U tRAM) DNU Do Not Use

ORDERING INFORMATION

Demuxed NOR Flash + Demuxed UtRAM Samsung MCP Memory 2Chip MCP K 5 L 56 28 J T(B) M - D H 18 NOR Flash Density 56 : 256Mbit, x16 Flash Access Time 14.5ns(CF 54MHz) Block Architecture T = Top Boot Block B = Bottom Boot Block Version 1st Generation UtRAM Access Time 18.9ns Operating Voltage J : 1.8V/1.8V(NOR), 2.6V/1.8V(UtRAM) Package D : FBGA(Lead Free) UtRAM Density, (Organization) 28 : 128Mbit, x16, Burst

Figure 1. FUNCTIONAL BLOCK DIAGRAM

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash A-die

Table 2. DEVICE BANK DIVISIONS

16 Mbit Eight 4Kwords,

Table 1. PRODUCT LINE-UP

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 0 BA518 4 Kwords FFF000h-FFFFFFh BA517 4 Kwords FFE000h-FFEFFFh BA516 4 Kwords FFD000h-FFDFFFh BA515 4 Kwords FFC000h-FFCFFFh BA514 4 Kwords FFB000h-FFBFFFh BA513 4 Kwords FFA000h-FFAFFFh BA512 4 Kwords FF9000h-FF9FFFh BA511 4 Kwords FF8000h-FF8FFFh BA510 32 Kwords FF0000h-FF7FFFh BA509 32 Kwords FE8000h-FEFFFFh BA508 32 Kwords FE0000h-FE7FFFh BA507 32 Kwords FD8000h-FDFFFFh BA506 32 Kwords FD0000h-FD7FFFh BA505 32 Kwords FC8000h-FCFFFFh BA504 32 Kwords FC0000h-FC7FFFh BA503 32 Kwords FB8000h-FBFFFFh BA502 32 Kwords FB0000h-FB7FFFh BA501 32 Kwords FA8000h-FAFFFFh BA500 32 Kwords FA0000h-FA7FFFh BA499 32 Kwords F98000h-F9FFFFh BA498 32 Kwords F90000h-F97FFFh BA497 32 Kwords F88000h-F8FFFFh BA496 32 Kwords F80000h-F87FFFh BA495 32 Kwords F78000h-F7FFFFh BA494 32 Kwords F70000h-F77FFFh BA493 32 Kwords F68000h-F6FFFFh BA492 32 Kwords F60000h-F67FFFh BA491 32 Kwords F58000h-F5FFFFh BA490 32 Kwords F50000h-F57FFFh BA489 32 Kwords F48000h-F4FFFFh BA488 32 Kwords F40000h-F47FFFh BA487 32 Kwords F38000h-F3FFFFh BA486 32 Kwords F30000h-F37FFFh BA485 32 Kwords F28000h-F2FFFFh BA484 32 Kwords F20000h-F27FFFh BA483 32 Kwords F18000h-F1FFFFh BA482 32 Kwords F10000h-F17FFFh BA481 32 Kwords F08000h-F0FFFFh BA480 32 kwords F00000h-F07FFFh Bank 1 BA479 32 Kwords EF8000h-EFFFFFh BA478 32 Kwords EF0000h-EF7FFFh BA477 32 Kwords EE8000h-EEFFFFh BA476 32 Kwords EE0000h-EE7FFFh BA475 32 Kwords ED8000h-EDFFFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 1 BA474 32 Kwords ED0000h-ED7FFFh BA473 32 Kwords EC8000h-ECFFFFh BA472 32 Kwords EC0000h-EC7FFFh BA471 32 Kwords EB8000h-EBFFFFh BA470 32 Kwords EB0000h-EB7FFFh BA469 32 Kwords EA8000h-EAFFFFh BA468 32 Kwords EA0000h-EA7FFFh BA467 32 Kwords E98000h-E9FFFFh BA466 32 Kwords E90000h-E97FFFh BA465 32 Kwords E88000h-E8FFFFh BA464 32 Kwords E80000h-E87FFFh BA463 32 Kwords E78000h-E7FFFFh BA462 32 Kwords E70000h-E77FFFh BA461 32 Kwords E68000h-E6FFFFh BA460 32 Kwords E60000h-E67FFFh BA459 32 Kwords E58000h-E5FFFFh BA458 32 Kwords E50000h-E57FFFh BA457 32 Kwords E48000h-E4FFFFh BA456 32 Kwords E40000h-E47FFFh BA455 32 Kwords E38000h-E3FFFFh BA454 32 Kwords E30000h-E37FFFh BA453 32 Kwords E28000h-E2FFFFh BA452 32 Kwords E20000h-E27FFFh BA451 32 Kwords E18000h-E1FFFFh BA450 32 Kwords E10000h-E17FFFh BA449 32 Kwords E08000h-E0FFFFh BA448 32 Kwords E00000h-E07FFFh Bank 2 BA447 32 Kwords DF8000h-DFFFFFh BA446 32 Kwords DF0000h-DF7FFFh BA445 32 Kwords DE8000h-DEFFFFh BA444 32 Kwords DE0000h-DE7FFFh BA443 32 Kwords DD8000h-DDFFFFh BA442 32 Kwords DD0000h-DD7FFFh BA441 32 Kwords DC8000h-DCFFFFh BA440 32 Kwords DC0000h-DC7FFFh BA439 32 Kwords DB8000h-DBFFFFh BA438 32 Kwords DB0000h-DB7FFFh BA437 32 Kwords DA8000h-DAFFFFh BA436 32 Kwords DA0000h-DA7FFFh BA435 32 Kwords D98000h-D9FFFFh BA434 32 Kwords D90000h-D97FFFh BA433 32 Kwords D88000h-D8FFFFh BA432 32 Kwords D80000h-D87FFFh BA431 32 Kwords D78000h-D7FFFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 2 BA430 32 Kwords D70000h-D77FFFh BA429 32 Kwords D68000h-D6FFFFh BA428 32 Kwords D60000h-D67FFFh BA427 32 Kwords D58000h-D5FFFFh BA426 32 Kwords D50000h-D57FFFh BA425 32 Kwords D48000h-D4FFFFh BA424 32 Kwords D40000h-D47FFFh BA423 32 Kwords D38000h-D3FFFFh BA422 32 Kwords D30000h-D37FFFh BA421 32 Kwords D28000h-D2FFFFh BA420 32 Kwords D20000h-D27FFFh BA419 32 Kwords D18000h-D1FFFFh BA418 32 Kwords D10000h-D17FFFh BA417 32 Kwords D08000h-D0FFFFh BA416 32 Kwords D00000h-D07FFFh Bank 3 BA415 32 Kwords CF8000h-CFFFFFh BA414 32 Kwords CF0000h-CF7FFFh BA413 32 Kwords CE8000h-CEFFFFh BA412 32 Kwords CE0000h-CE7FFFh BA411 32 Kwords CD8000h-CDFFFFh BA410 32 Kwords CD0000h-CD7FFFh BA409 32 Kwords CC8000h-CCFFFFh BA408 32 Kwords CC0000h-CC7FFFh BA407 32 Kwords CB8000h-CBFFFFh BA406 32 Kwords CB0000h-CB7FFFh BA405 32 Kwords CA8000h-CAFFFFh BA404 32 Kwords CA0000h-CA7FFFh BA403 32 Kwords C98000h-C9FFFFh BA402 32 Kwords C90000h-C97FFFh BA401 32 Kwords C88000h-C8FFFFh BA400 32 Kwords C80000h-C87FFFh BA399 32 Kwords C78000h-C7FFFFh BA398 32 Kwords C70000h-C77FFFh BA397 32 Kwords C68000h-C6FFFFh BA396 32 Kwords C60000h-C67FFFh BA395 32 Kwords C58000h-C5FFFFh BA394 32 Kwords C50000h-C57FFFh BA393 32 Kwords C48000h-C4FFFFh BA392 32 Kwords C40000h-C47FFFh BA391 32 Kwords C38000h-C3FFFFh BA390 32 Kwords C30000h-C37FFFh BA389 32 Kwords C28000h-C2FFFFh BA388 32 Kwords C20000h-C27FFFh BA387 32 Kwords C18000h-C1FFFFh BA386 32 Kwords C10000h-C17FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 3 BA385 32 Kwords C08000h-C0FFFFh BA384 32 Kwords C00000h-C07FFFh Bank 4 BA383 32 Kwords BF8000h-BFFFFFh BA382 32 Kwords BF0000h-BF7FFFh BA381 32 Kwords BE8000h-BEFFFFh BA380 32 Kwords BE0000h-BE7FFFh BA379 32 Kwords BD8000h-BDFFFFh BA378 32 Kwords BD0000h-BD7FFFh BA377 32 Kwords BC8000h-BCFFFFh BA376 32 Kwords BC0000h-BC7FFFh BA375 32 Kwords BB8000h-BBFFFFh BA374 32 Kwords BB0000h-BB7FFFh BA373 32 Kwords BA8000h-BAFFFFh BA372 32 Kwords BA0000h-BA7FFFh BA371 32 Kwords B98000h-B9FFFFh BA370 32 Kwords B90000h-B97FFFh BA369 32 Kwords B88000h-B8FFFFh BA368 32 Kwords B80000h-B87FFFh BA367 32 Kwords B78000h-B7FFFFh BA366 32 Kwords B70000h-B77FFFh BA365 32 Kwords B68000h-B6FFFFh BA364 32 Kwords B60000h-B67FFFh BA363 32 Kwords B58000h-B5FFFFh BA362 32 Kwords B50000h-B57FFFh BA361 32 Kwords B48000h-B4FFFFh BA360 32 Kwords B40000h-B47FFFh BA359 32 Kwords B38000h-B3FFFFh BA358 32 Kwords B30000h-B37FFFh BA357 32 Kwords B28000h-B2FFFFh BA356 32 Kwords B20000h-B27FFFh BA355 32 Kwords B18000h-B1FFFFh BA354 32 Kwords B10000h-B17FFFh BA353 32 Kwords B08000h-B0FFFFh BA352 32 Kwords B00000h-B07FFFh Bank 5 BA351 32 Kwords AF8000h-AFFFFFh BA350 32 Kwords AF0000h-AF7FFFh BA349 32 Kwords AE8000h-AEFFFFh BA348 32 Kwords AE0000h-AE7FFFh BA347 32 Kwords AD8000h-ADFFFFh BA346 32 Kwords AD0000h-AD7FFFh BA345 32 Kwords AC8000h-ACFFFFh BA344 32 Kwords AC0000h-AC7FFFh BA343 32 Kwords AB8000h-ABFFFFh BA342 32 Kwords AB0000h-AB7FFFh BA341 32 Kwords AA8000h-AAFFFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 5 BA340 32 Kwords AA0000h-AA7FFFh BA339 32 Kwords A98000h-A9FFFFh BA338 32 Kwords A90000h-A97FFFh BA337 32 Kwords A88000h-A8FFFFh BA336 32 Kwords A80000h-A87FFFh BA335 32 Kwords A78000h-A7FFFFh BA334 32 Kwords A70000h-A77FFFh BA333 32 Kwords A68000h-A6FFFFh BA332 32 Kwords A60000h-A67FFFh BA331 32 Kwords A58000h-A5FFFFh BA330 32 Kwords A50000h-A57FFFh BA329 32 Kwords A48000h-A4FFFFh BA328 32 Kwords A40000h-A47FFFh BA327 32 Kwords A38000h-A3FFFFh BA326 32 Kwords A30000h-A37FFFh BA325 32 Kwords A28000h-A2FFFFh BA324 32 Kwords A20000h-A27FFFh BA323 32 Kwords A18000h-A1FFFFh BA322 32 Kwords A10000h-A17FFFh BA321 32 Kwords A08000h-A0FFFFh BA320 32 Kwords A00000h-A07FFFh Bank 6 BA319 32 Kwords 9F8000h-9FFFFFh BA318 32 Kwords 9F0000h-9F7FFFh BA317 32 Kwords 9E8000h-9EFFFFh BA316 32 Kwords 9E0000h-9E7FFFh BA315 32 Kwords 9D8000h-9DFFFFh BA314 32 Kwords 9D0000h-9D7FFFh BA313 32 Kwords 9C8000h-9CFFFFh BA312 32 Kwords 9C0000h-9C7FFFh BA311 32 Kwords 9B8000h-9BFFFFh BA310 32 Kwords 9B0000h-9B7FFFh BA309 32 Kwords 9A8000h-9AFFFFh BA308 32 Kwords 9A0000h-9A7FFFh BA307 32 Kwords 998000h-99FFFFh BA306 32 Kwords 990000h-997FFFh BA305 32 Kwords 988000h-98FFFFh BA304 32 Kwords 980000h-987FFFh BA303 32 Kwords 978000h-97FFFFh BA302 32 Kwords 970000h-977FFFh BA301 32 Kwords 968000h-96FFFFh BA300 32 Kwords 960000h-967FFFh BA299 32 Kwords 958000h-95FFFFh BA298 32 Kwords 950000h-957FFFh BA297 32 Kwords 948000h-94FFFFh BA296 32 Kwords 940000h-947FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 6 BA295 32 Kwords 938000h-93FFFFh BA294 32 Kwords 930000h-937FFFh BA293 32 Kwords 928000h-92FFFFh BA292 32 Kwords 920000h-927FFFh BA291 32 Kwords 918000h-91FFFFh BA290 32 Kwords 910000h-917FFFh BA289 32 Kwords 908000h-90FFFFh BA288 32 Kwords 900000h-907FFFh Bank 7 BA287 32 Kwords 8F8000h-8FFFFFh BA286 32 Kwords 8F0000h-8F7FFFh BA285 32 Kwords 8E8000h-8EFFFFh BA284 32 Kwords 8E0000h-8E7FFFh BA283 32 Kwords 8D8000h-8DFFFFh BA282 32 Kwords 8D0000h-8D7FFFh BA281 32 Kwords 8C8000h-8CFFFFh BA280 32 Kwords 8C0000h-8C7FFFh BA279 32 Kwords 8B8000h-8BFFFFh BA278 32 Kwords 8B0000h-8B7FFFh BA277 32 Kwords 8A8000h-8AFFFFh BA276 32 Kwords 8A0000h-8A7FFFh BA275 32 Kwords 898000h-89FFFFh BA274 32 Kwords 890000h-897FFFh BA273 32 Kwords 888000h-88FFFFh BA272 32 Kwords 880000h-887FFFh BA271 32 Kwords 878000h-87FFFFh BA270 32 Kwords 870000h-877FFFh BA269 32 Kwords 868000h-86FFFFh BA268 32 Kwords 860000h-867FFFh BA267 32 Kwords 858000h-85FFFFh BA266 32 Kwords 850000h-857FFFh BA265 32 Kwords 848000h-84FFFFh BA264 32 Kwords 840000h-847FFFh BA263 32 Kwords 838000h-83FFFFh BA262 32 Kwords 830000h-837FFFh BA261 32 Kwords 828000h-82FFFFh BA260 32 Kwords 820000h-827FFFh BA259 32 Kwords 818000h-81FFFFh BA258 32 Kwords 810000h-817FFFh BA257 32 Kwords 808000h-80FFFFh BA256 32 Kwords 800000h-807FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 8 BA255 32 Kwords 7F8000h-7FFFFFh BA254 32 Kwords 7F0000h-7F7FFFh BA253 32 Kwords 7E8000h-7EFFFFh BA252 32 Kwords 7E0000h-7E7FFFh BA251 32 Kwords 7D8000h-7DFFFFh BA250 32 Kwords 7D0000h-7D7FFFh BA249 32 Kwords 7C8000h-7CFFFFh BA248 32 Kwords 7C0000h-7C7FFFh BA247 32 Kwords 7B8000h-7BFFFFh BA246 32 Kwords 7B0000h-7B7FFFh BA245 32 Kwords 7A8000h-7AFFFFh BA244 32 Kwords 7A0000h-7A7FFFh BA243 32 Kwords 798000h-79FFFFh BA242 32 Kwords 790000h-797FFFh BA241 32 Kwords 788000h-78FFFFh BA240 32 Kwords 780000h-787FFFh BA239 32 Kwords 778000h-77FFFFh BA238 32 Kwords 770000h-777FFFh BA237 32 Kwords 768000h-76FFFFh BA236 32 Kwords 760000h-767FFFh BA235 32 Kwords 758000h-75FFFFh BA234 32 Kwords 750000h-757FFFh BA233 32 Kwords 748000h-74FFFFh BA232 32 Kwords 740000h-747FFFh BA231 32 Kwords 738000h-73FFFFh BA230 32 Kwords 730000h-737FFFh BA229 32 Kwords 728000h-72FFFFh BA228 32 Kwords 720000h-727FFFh BA227 32 Kwords 718000h-71FFFFh BA226 32 Kwords 710000h-717FFFh BA225 32 Kwords 708000h-70FFFFh BA224 32 kwords 700000h-707FFFh Bank 9 BA223 32 Kwords 6F8000h-6FFFFFh BA222 32 Kwords 6F0000h-6F7FFFh BA221 32 Kwords 6E8000h-6EFFFFh BA220 32 Kwords 6E0000h-6E7FFFh BA219 32 Kwords 6D8000h-6DFFFFh BA218 32 Kwords 6D0000h-6D7FFFh BA217 32 Kwords 6C8000h-6CFFFFh BA216 32 Kwords 6C0000h-6C7FFFh BA215 32 Kwords 6B8000h-6BFFFFh BA214 32 Kwords 6B0000h-6B7FFFh BA213 32 Kwords 6A8000h-6AFFFFh BA212 32 Kwords 6A0000h-6A7FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 9 BA211 32 Kwords 698000h-69FFFFh BA210 32 Kwords 690000h-697FFFh BA209 32 Kwords 688000h-68FFFFh BA208 32 Kwords 680000h-687FFFh BA207 32 Kwords 678000h-67FFFFh BA206 32 Kwords 670000h-677FFFh BA205 32 Kwords 668000h-66FFFFh BA204 32 Kwords 660000h-667FFFh BA203 32 Kwords 658000h-65FFFFh BA202 32 Kwords 650000h-657FFFh BA201 32 Kwords 648000h-64FFFFh BA200 32 Kwords 640000h-647FFFh BA199 32 Kwords 638000h-63FFFFh BA198 32 Kwords 630000h-637FFFh BA197 32 Kwords 628000h-62FFFFh BA196 32 Kwords 620000h-627FFFh BA195 32 Kwords 618000h-61FFFFh BA194 32 Kwords 610000h-617FFFh BA193 32 Kwords 608000h-60FFFFh BA192 32 Kwords 600000h-607FFFh Bank 10 BA191 32 Kwords 5F8000h-5FFFFFh BA190 32 Kwords 5F0000h-5F7FFFh BA189 32 Kwords 5E8000h-5EFFFFh BA188 32 Kwords 5E0000h-5E7FFFh BA187 32 Kwords 5D8000h-5DFFFFh BA186 32 Kwords 5D0000h-5D7FFFh BA185 32 Kwords 5C8000h-5CFFFFh BA184 32 Kwords 5C0000h-5C7FFFh BA183 32 Kwords 5B8000h-5BFFFFh BA182 32 Kwords 5B0000h-5B7FFFh BA181 32 Kwords 5A8000h-5AFFFFh BA180 32 Kwords 5A0000h-5A7FFFh BA179 32 Kwords 598000h-59FFFFh BA178 32 Kwords 590000h-597FFFh BA177 32 Kwords 588000h-58FFFFh BA176 32 Kwords 580000h-587FFFh BA175 32 Kwords 578000h-57FFFFh BA174 32 Kwords 570000h-577FFFh BA173 32 Kwords 568000h-56FFFFh BA172 32 Kwords 560000h-567FFFh BA171 32 Kwords 558000h-55FFFFh BA170 32 Kwords 550000h-557FFFh BA169 32 Kwords 548000h-54FFFFh BA168 32 Kwords 540000h-547FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 10 BA167 32 Kwords 538000h-53FFFFh BA166 32 Kwords 530000h-537FFFh BA165 32 Kwords 528000h-52FFFFh BA164 32 Kwords 520000h-527FFFh BA163 32 Kwords 518000h-51FFFFh BA162 32 Kwords 510000h-517FFFh BA161 32 Kwords 508000h-50FFFFh BA160 32 Kwords 500000h-507FFFh Bank 11 BA159 32 Kwords 4F8000h-4FFFFFh BA158 32 Kwords 4F0000h-4F7FFFh BA157 32 Kwords 4E8000h-4EFFFFh BA156 32 Kwords 4E0000h-4E7FFFh BA155 32 Kwords 4D8000h-4DFFFFh BA154 32 Kwords 4D0000h-4D7FFFh BA153 32 Kwords 4C8000h-4CFFFFh BA152 32 Kwords 4C0000h-4C7FFFh BA151 32 Kwords 4B8000h-4BFFFFh BA150 32 Kwords 4B0000h-4B7FFFh BA149 32 Kwords 4A8000h-4AFFFFh BA148 32 Kwords 4A0000h-4A7FFFh BA147 32 Kwords 498000h-49FFFFh BA146 32 Kwords 490000h-497FFFh BA145 32 Kwords 488000h-48FFFFh BA144 32 Kwords 480000h-487FFFh BA143 32 Kwords 478000h-47FFFFh BA142 32 Kwords 470000h-477FFFh BA141 32 Kwords 468000h-46FFFFh BA140 32 Kwords 460000h-467FFFh BA139 32 Kwords 458000h-45FFFFh BA138 32 Kwords 450000h-457FFFh BA137 32 Kwords 448000h-44FFFFh BA136 32 Kwords 440000h-447FFFh BA135 32 Kwords 438000h-43FFFFh BA134 32 Kwords 430000h-437FFFh BA133 32 Kwords 428000h-42FFFFh BA132 32 Kwords 420000h-427FFFh BA131 32 Kwords 418000h-41FFFFh BA130 32 Kwords 410000h-417FFFh BA129 32 Kwords 408000h-40FFFFh BA128 32 Kwords 400000h-407FFFh Bank 12 BA127 32 Kwords 3F8000h-3FFFFFh BA126 32 Kwords 3F0000h-3F7FFFh BA125 32 Kwords 3E8000h-3EFFFFh BA124 32 Kwords 3E0000h-3E7FFFh BA123 32 Kwords 3D8000h-3DFFFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 12 BA122 32 Kwords 3D0000h-3D7FFFh BA121 32 Kwords 3C8000h-3CFFFFh BA120 32 Kwords 3C0000h-3C7FFFh BA119 32 Kwords 3B8000h-3BFFFFh BA118 32 Kwords 3B0000h-3B7FFFh BA117 32 Kwords 3A8000h-3AFFFFh BA116 32 Kwords 3A0000h-3A7FFFh BA115 32 Kwords 398000h-39FFFFh BA114 32 Kwords 390000h-397FFFh BA113 32 Kwords 388000h-38FFFFh BA112 32 Kwords 380000h-387FFFh BA111 32 Kwords 378000h-37FFFFh BA110 32 Kwords 370000h-377FFFh BA109 32 Kwords 368000h-36FFFFh BA108 32 Kwords 360000h-367FFFh BA107 32 Kwords 358000h-35FFFFh BA106 32 Kwords 350000h-357FFFh BA105 32 Kwords 348000h-34FFFFh BA104 32 Kwords 340000h-347FFFh BA103 32 Kwords 338000h-33FFFFh BA102 32 Kwords 330000h-337FFFh BA101 32 Kwords 328000h-32FFFFh BA100 32 Kwords 320000h-327FFFh BA99 32 Kwords 318000h-31FFFFh BA98 32 Kwords 310000h-317FFFh BA97 32 Kwords 308000h-30FFFFh BA96 32 Kwords 300000h-307FFFh Bank 13 BA95 32 Kwords 2F8000h-2FFFFFh BA94 32 Kwords 2F0000h-2F7FFFh BA93 32 Kwords 2E8000h-2EFFFFh BA92 32 Kwords 2E0000h-2E7FFFh BA91 32 Kwords 2D8000h-2DFFFFh BA90 32 Kwords 2D0000h-2D7FFFh BA89 32 Kwords 2C8000h-2CFFFFh BA88 32 Kwords 2C0000h-2C7FFFh BA87 32 Kwords 2B8000h-2BFFFFh BA86 32 Kwords 2B0000h-2B7FFFh BA85 32 Kwords 2A8000h-2AFFFFh BA84 32 Kwords 2A0000h-2A7FFFh BA83 32 Kwords 298000h-29FFFFh BA82 32 Kwords 290000h-297FFFh BA81 32 Kwords 288000h-28FFFFh BA80 32 Kwords 280000h-287FFFh BA79 32 Kwords 278000h-27FFFFh BA78 32 Kwords 270000h-277FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 13 BA77 32 Kwords 268000h-26FFFFh BA76 32 Kwords 260000h-267FFFh BA75 32 Kwords 258000h-25FFFFh BA74 32 Kwords 250000h-257FFFh BA73 32 Kwords 248000h-24FFFFh BA72 32 Kwords 240000h-247FFFh BA71 32 Kwords 238000h-23FFFFh BA70 32 Kwords 230000h-237FFFh BA69 32 Kwords 228000h-22FFFFh BA68 32 Kwords 220000h-227FFFh BA67 32 Kwords 218000h-21FFFFh BA66 32 Kwords 210000h-217FFFh BA65 32 Kwords 208000h-20FFFFh BA64 32 Kwords 200000h-207FFFh Bank 14 BA63 32 Kwords 1F8000h-1FFFFFh BA62 32 Kwords 1F0000h-1F7FFFh BA61 32 Kwords 1E8000h-1EFFFFh BA60 32 Kwords 1E0000h-1E7FFFh BA59 32 Kwords 1D8000h-1DFFFFh BA58 32 Kwords 1D0000h-1D7FFFh BA57 32 Kwords 1C8000h-1CFFFFh BA56 32 Kwords 1C0000h-1C7FFFh BA55 32 Kwords 1B8000h-1BFFFFh BA54 32 Kwords 1B0000h-1B7FFFh BA53 32 Kwords 1A8000h-1AFFFFh BA52 32 Kwords 1A0000h-1A7FFFh BA51 32 Kwords 198000h-19FFFFh BA50 32 Kwords 190000h-197FFFh BA49 32 Kwords 188000h-18FFFFh BA48 32 Kwords 180000h-187FFFh BA47 32 Kwords 178000h-17FFFFh BA46 32 Kwords 170000h-177FFFh BA45 32 Kwords 168000h-16FFFFh BA44 32 Kwords 160000h-167FFFh BA43 32 Kwords 158000h-15FFFFh BA42 32 Kwords 150000h-157FFFh BA41 32 Kwords 148000h-14FFFFh BA40 32 Kwords 140000h-147FFFh BA39 32 Kwords 138000h-13FFFFh BA38 32 Kwords 130000h-137FFFh BA37 32 Kwords 128000h-12FFFFh BA36 32 Kwords 120000h-127FFFh BA35 32 Kwords 118000h-11FFFFh BA34 32 Kwords 110000h-117FFFh BA33 32 Kwords 108000h-10FFFFh BA32 32 Kwords 100000h-107FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Top Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 15 BA31 32 Kwords 0F8000h-0FFFFFh BA30 32 Kwords 0F0000h-0F7FFFh BA29 32 Kwords 0E8000h-0EFFFFh BA28 32 Kwords 0E0000h-0E7FFFh BA27 32 Kwords 0D8000h-0DFFFFh BA26 32 Kwords 0D0000h-0D7FFFh BA25 32 Kwords 0C8000h-0CFFFFh BA24 32 Kwords 0C0000h-0C7FFFh BA23 32 Kwords 0B8000h-0BFFFFh BA22 32 Kwords 0B0000h-0B7FFFh BA21 32 Kwords 0A8000h-0AFFFFh BA20 32 Kwords 0A0000h-0A7FFFh BA19 32 Kwords 098000h-09FFFFh BA18 32 Kwords 090000h-097FFFh BA17 32 Kwords 088000h-08FFFFh BA16 32 Kwords 080000h-087FFFh BA15 32 Kwords 078000h-07FFFFh BA14 32 Kwords 070000h-077FFFh BA13 32 Kwords 068000h-06FFFFh BA12 32 Kwords 060000h-067FFFh BA11 32 Kwords 058000h-05FFFFh BA10 32 Kwords 050000h-057FFFh BA9 32 Kwords 048000h-04FFFFh BA8 32 Kwords 040000h-047FFFh BA7 32 Kwords 038000h-03FFFFh BA6 32 Kwords 030000h-037FFFh BA5 32 Kwords 028000h-02FFFFh BA4 32 Kwords 020000h-027FFFh BA3 32 Kwords 018000h-01FFFFh BA2 32 Kwords 010000h-017FFFh BA1 32 Kwords 008000h-00FFFFh BA0 32 Kwords 000000h-007FFFh OTP Block Address A23 ~ A8 Block Size (x16) Address Range FFFFh 128words FFFF80h-FFFFFFh Table 3-1-1. Top Boot Block OTP Addresses Table After entering OTP block, any issued addresses should be in the range of OTP block address

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 15 BA518 32 Kwords FF8000h-FFFFFFh BA517 32 Kwords FF0000h-FF7FFFh BA516 32 Kwords FE8000h-FEFFFFh BA515 32 Kwords FE0000h-FE7FFFh BA514 32 Kwords FD8000h-FDFFFFh BA513 32 Kwords FD0000h-FD7FFFh BA512 32 Kwords FC8000h-FCFFFFh BA511 32 Kwords FC0000h-FC7FFFh BA510 32 Kwords FB8000h-FBFFFFh BA509 32 Kwords FB0000h-FB7FFFh BA508 32 Kwords FA8000h-FAFFFFh BA507 32 Kwords FA0000h-FA7FFFh BA506 32 Kwords F98000h-F9FFFFh BA505 32 Kwords F90000h-F97FFFh BA504 32 Kwords F88000h-F8FFFFh BA503 32 Kwords F80000h-F87FFFh BA502 32 Kwords F78000h-F7FFFFh BA501 32 Kwords F70000h-F77FFFh BA500 32 Kwords F68000h-F6FFFFh BA499 32 Kwords F60000h-F67FFFh BA498 32 Kwords F58000h-F5FFFFh BA497 32 Kwords F50000h-F57FFFh BA496 32 Kwords F48000h-F4FFFFh BA495 32 Kwords F40000h-F47FFFh BA494 32 Kwords F38000h-F3FFFFh BA493 32 Kwords F30000h-F37FFFh BA492 32 Kwords F28000h-F2FFFFh BA491 32 Kwords F20000h-F27FFFh BA490 32 Kwords F18000h-F1FFFFh BA489 32 Kwords F10000h-F17FFFh BA488 32 Kwords F08000h-F0FFFFh BA487 32 kwords F00000h-F07FFFh Bank 14 BA486 32 Kwords EF8000h-EFFFFFh BA485 32 Kwords EF0000h-EF7FFFh BA484 32 Kwords EE8000h-EEFFFFh BA483 32 Kwords EE0000h-EE7FFFh BA482 32 Kwords ED8000h-EDFFFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 14 BA481 32 Kwords ED0000h-ED7FFFh BA480 32 Kwords EC8000h-ECFFFFh BA479 32 Kwords EC0000h-EC7FFFh BA478 32 Kwords EB8000h-EBFFFFh BA477 32 Kwords EB0000h-EB7FFFh BA476 32 Kwords EA8000h-EAFFFFh BA475 32 Kwords EA0000h-EA7FFFh BA474 32 Kwords E98000h-E9FFFFh BA473 32 Kwords E90000h-E97FFFh BA472 32 Kwords E88000h-E8FFFFh BA471 32 Kwords E80000h-E87FFFh BA470 32 Kwords E78000h-E7FFFFh BA469 32 Kwords E70000h-E77FFFh BA468 32 Kwords E68000h-E6FFFFh BA467 32 Kwords E60000h-E67FFFh BA466 32 Kwords E58000h-E5FFFFh BA465 32 Kwords E50000h-E57FFFh BA464 32 Kwords E48000h-E4FFFFh BA463 32 Kwords E40000h-E47FFFh BA462 32 Kwords E38000h-E3FFFFh BA461 32 Kwords E30000h-E37FFFh BA460 32 Kwords E28000h-E2FFFFh BA459 32 Kwords E20000h-E27FFFh BA458 32 Kwords E18000h-E1FFFFh BA457 32 Kwords E10000h-E17FFFh BA456 32 Kwords E08000h-E0FFFFh BA455 32 Kwords E00000h-E07FFFh Bank 13 BA454 32 Kwords DF8000h-DFFFFFh BA453 32 Kwords DF0000h-DF7FFFh BA452 32 Kwords DE8000h-DEFFFFh BA451 32 Kwords DE0000h-DE7FFFh BA450 32 Kwords DD8000h-DDFFFFh BA449 32 Kwords DD0000h-DD7FFFh BA448 32 Kwords DC8000h-DCFFFFh BA447 32 Kwords DC0000h-DC7FFFh BA446 32 Kwords DB8000h-DBFFFFh BA445 32 Kwords DB0000h-DB7FFFh BA444 32 Kwords DA8000h-DAFFFFh BA443 32 Kwords DA0000h-DA7FFFh BA442 32 Kwords D98000h-D9FFFFh BA441 32 Kwords D90000h-D97FFFh BA440 32 Kwords D88000h-D8FFFFh BA439 32 Kwords D80000h-D87FFFh BA438 32 Kwords D78000h-D7FFFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 13 BA437 32 Kwords D70000h-D77FFFh BA436 32 Kwords D68000h-D6FFFFh BA435 32 Kwords D60000h-D67FFFh BA434 32 Kwords D58000h-D5FFFFh BA433 32 Kwords D50000h-D57FFFh BA432 32 Kwords D48000h-D4FFFFh BA431 32 Kwords D40000h-D47FFFh BA430 32 Kwords D38000h-D3FFFFh BA429 32 Kwords D30000h-D37FFFh BA428 32 Kwords D28000h-D2FFFFh BA427 32 Kwords D20000h-D27FFFh BA426 32 Kwords D18000h-D1FFFFh BA425 32 Kwords D10000h-D17FFFh BA424 32 Kwords D08000h-D0FFFFh BA423 32 Kwords D00000h-D07FFFh Bank 12 BA422 32 Kwords CF8000h-CFFFFFh BA421 32 Kwords CF0000h-CF7FFFh BA420 32 Kwords CE8000h-CEFFFFh BA419 32 Kwords CE0000h-CE7FFFh BA418 32 Kwords CD8000h-CDFFFFh BA417 32 Kwords CD0000h-CD7FFFh BA416 32 Kwords CC8000h-CCFFFFh BA415 32 Kwords CC0000h-CC7FFFh BA414 32 Kwords CB8000h-CBFFFFh BA413 32 Kwords CB0000h-CB7FFFh BA412 32 Kwords CA8000h-CAFFFFh BA411 32 Kwords CA0000h-CA7FFFh BA410 32 Kwords C98000h-C9FFFFh BA409 32 Kwords C90000h-C97FFFh BA408 32 Kwords C88000h-C8FFFFh BA407 32 Kwords C80000h-C87FFFh BA406 32 Kwords C78000h-C7FFFFh BA405 32 Kwords C70000h-C77FFFh BA404 32 Kwords C68000h-C6FFFFh BA403 32 Kwords C60000h-C67FFFh BA402 32 Kwords C58000h-C5FFFFh BA401 32 Kwords C50000h-C57FFFh BA400 32 Kwords C48000h-C4FFFFh BA399 32 Kwords C40000h-C47FFFh BA398 32 Kwords C38000h-C3FFFFh BA397 32 Kwords C30000h-C37FFFh BA396 32 Kwords C28000h-C2FFFFh BA395 32 Kwords C20000h-C27FFFh BA394 32 Kwords C18000h-C1FFFFh BA393 32 Kwords C10000h-C17FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 12 BA392 32 Kwords C08000h-C0FFFFh BA391 32 Kwords C00000h-C07FFFh Bank 11 BA390 32 Kwords BF8000h-BFFFFFh BA389 32 Kwords BF0000h-BF7FFFh BA388 32 Kwords BE8000h-BEFFFFh BA387 32 Kwords BE0000h-BE7FFFh BA386 32 Kwords BD8000h-BDFFFFh BA385 32 Kwords BD0000h-BD7FFFh BA384 32 Kwords BC8000h-BCFFFFh BA383 32 Kwords BC0000h-BC7FFFh BA382 32 Kwords BB8000h-BBFFFFh BA381 32 Kwords BB0000h-BB7FFFh BA380 32 Kwords BA8000h-BAFFFFh BA379 32 Kwords BA0000h-BA7FFFh BA378 32 Kwords B98000h-B9FFFFh BA377 32 Kwords B90000h-B97FFFh BA376 32 Kwords B88000h-B8FFFFh BA375 32 Kwords B80000h-B87FFFh BA374 32 Kwords B78000h-B7FFFFh BA373 32 Kwords B70000h-B77FFFh BA372 32 Kwords B68000h-B6FFFFh BA371 32 Kwords B60000h-B67FFFh BA370 32 Kwords B58000h-B5FFFFh BA369 32 Kwords B50000h-B57FFFh BA368 32 Kwords B48000h-B4FFFFh BA367 32 Kwords B40000h-B47FFFh BA366 32 Kwords B38000h-B3FFFFh BA365 32 Kwords B30000h-B37FFFh BA364 32 Kwords B28000h-B2FFFFh BA363 32 Kwords B20000h-B27FFFh BA362 32 Kwords B18000h-B1FFFFh BA361 32 Kwords B10000h-B17FFFh BA360 32 Kwords B08000h-B0FFFFh BA359 32 Kwords B00000h-B07FFFh Bank 10 BA358 32 Kwords AF8000h-AFFFFFh BA357 32 Kwords AF0000h-AF7FFFh BA356 32 Kwords AE8000h-AEFFFFh BA355 32 Kwords AE0000h-AE7FFFh BA354 32 Kwords AD8000h-ADFFFFh BA353 32 Kwords AD0000h-AD7FFFh BA352 32 Kwords AC8000h-ACFFFFh BA351 32 Kwords AC0000h-AC7FFFh BA350 32 Kwords AB8000h-ABFFFFh BA349 32 Kwords AB0000h-AB7FFFh BA348 32 Kwords AA8000h-AAFFFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 10 BA347 32 Kwords AA0000h-AA7FFFh BA346 32 Kwords A98000h-A9FFFFh BA345 32 Kwords A90000h-A97FFFh BA344 32 Kwords A88000h-A8FFFFh BA343 32 Kwords A80000h-A87FFFh BA342 32 Kwords A78000h-A7FFFFh BA341 32 Kwords A70000h-A77FFFh BA340 32 Kwords A68000h-A6FFFFh BA339 32 Kwords A60000h-A67FFFh BA338 32 Kwords A58000h-A5FFFFh BA337 32 Kwords A50000h-A57FFFh BA336 32 Kwords A48000h-A4FFFFh BA335 32 Kwords A40000h-A47FFFh BA334 32 Kwords A38000h-A3FFFFh BA333 32 Kwords A30000h-A37FFFh BA332 32 Kwords A28000h-A2FFFFh BA331 32 Kwords A20000h-A27FFFh BA330 32 Kwords A18000h-A1FFFFh BA329 32 Kwords A10000h-A17FFFh BA328 32 Kwords A08000h-A0FFFFh BA327 32 Kwords A00000h-A07FFFh Bank 9 BA326 32 Kwords 9F8000h-9FFFFFh BA325 32 Kwords 9F0000h-9F7FFFh BA324 32 Kwords 9E8000h-9EFFFFh BA323 32 Kwords 9E0000h-9E7FFFh BA322 32 Kwords 9D8000h-9DFFFFh BA321 32 Kwords 9D0000h-9D7FFFh BA320 32 Kwords 9C8000h-9CFFFFh BA319 32 Kwords 9C0000h-9C7FFFh BA318 32 Kwords 9B8000h-9BFFFFh BA317 32 Kwords 9B0000h-9B7FFFh BA316 32 Kwords 9A8000h-9AFFFFh BA315 32 Kwords 9A0000h-9A7FFFh BA314 32 Kwords 998000h-99FFFFh BA313 32 Kwords 990000h-997FFFh BA312 32 Kwords 988000h-98FFFFh BA311 32 Kwords 980000h-987FFFh BA310 32 Kwords 978000h-97FFFFh BA309 32 Kwords 970000h-977FFFh BA308 32 Kwords 968000h-96FFFFh BA307 32 Kwords 960000h-967FFFh BA306 32 Kwords 958000h-95FFFFh BA305 32 Kwords 950000h-957FFFh BA304 32 Kwords 948000h-94FFFFh BA303 32 Kwords 940000h-947FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 9 BA302 32 Kwords 938000h-93FFFFh BA301 32 Kwords 930000h-937FFFh BA300 32 Kwords 928000h-92FFFFh BA299 32 Kwords 920000h-927FFFh BA298 32 Kwords 918000h-91FFFFh BA297 32 Kwords 910000h-917FFFh BA296 32 Kwords 908000h-90FFFFh BA295 32 Kwords 900000h-907FFFh Bank 8 BA294 32 Kwords 8F8000h-8FFFFFh BA293 32 Kwords 8F0000h-8F7FFFh BA292 32 Kwords 8E8000h-8EFFFFh BA291 32 Kwords 8E0000h-8E7FFFh BA290 32 Kwords 8D8000h-8DFFFFh BA289 32 Kwords 8D0000h-8D7FFFh BA288 32 Kwords 8C8000h-8CFFFFh BA287 32 Kwords 8C0000h-8C7FFFh BA286 32 Kwords 8B8000h-8BFFFFh BA285 32 Kwords 8B0000h-8B7FFFh BA284 32 Kwords 8A8000h-8AFFFFh BA283 32 Kwords 8A0000h-8A7FFFh BA282 32 Kwords 898000h-89FFFFh BA281 32 Kwords 890000h-897FFFh BA280 32 Kwords 888000h-88FFFFh BA279 32 Kwords 880000h-887FFFh BA278 32 Kwords 878000h-87FFFFh BA277 32 Kwords 870000h-877FFFh BA276 32 Kwords 868000h-86FFFFh BA275 32 Kwords 860000h-867FFFh BA274 32 Kwords 858000h-85FFFFh BA273 32 Kwords 850000h-857FFFh BA272 32 Kwords 848000h-84FFFFh BA271 32 Kwords 840000h-847FFFh BA270 32 Kwords 838000h-83FFFFh BA269 32 Kwords 830000h-837FFFh BA268 32 Kwords 828000h-82FFFFh BA267 32 Kwords 820000h-827FFFh BA266 32 Kwords 818000h-81FFFFh BA265 32 Kwords 810000h-817FFFh BA264 32 Kwords 808000h-80FFFFh BA263 32 Kwords 800000h-807FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 7 BA262 32 Kwords 7F8000h-7FFFFFh BA261 32 Kwords 7F0000h-7F7FFFh BA260 32 Kwords 7E8000h-7EFFFFh BA259 32 Kwords 7E0000h-7E7FFFh BA258 32 Kwords 7D8000h-7DFFFFh BA257 32 Kwords 7D0000h-7D7FFFh BA256 32 Kwords 7C8000h-7CFFFFh BA255 32 Kwords 7C0000h-7C7FFFh BA254 32 Kwords 7B8000h-7BFFFFh BA253 32 Kwords 7B0000h-7B7FFFh BA252 32 Kwords 7A8000h-7AFFFFh BA251 32 Kwords 7A0000h-7A7FFFh BA250 32 Kwords 798000h-79FFFFh BA249 32 Kwords 790000h-797FFFh BA248 32 Kwords 788000h-78FFFFh BA247 32 Kwords 780000h-787FFFh BA246 32 Kwords 778000h-77FFFFh BA245 32 Kwords 770000h-777FFFh BA244 32 Kwords 768000h-76FFFFh BA243 32 Kwords 760000h-767FFFh BA242 32 Kwords 758000h-75FFFFh BA241 32 Kwords 750000h-757FFFh BA240 32 Kwords 748000h-74FFFFh BA239 32 Kwords 740000h-747FFFh BA238 32 Kwords 738000h-73FFFFh BA237 32 Kwords 730000h-737FFFh BA236 32 Kwords 728000h-72FFFFh BA235 32 Kwords 720000h-727FFFh BA234 32 Kwords 718000h-71FFFFh BA233 32 Kwords 710000h-717FFFh BA232 32 Kwords 708000h-70FFFFh BA231 32 kwords 700000h-707FFFh Bank 6 BA230 32 Kwords 6F8000h-6FFFFFh BA229 32 Kwords 6F0000h-6F7FFFh BA228 32 Kwords 6E8000h-6EFFFFh BA227 32 Kwords 6E0000h-6E7FFFh BA226 32 Kwords 6D8000h-6DFFFFh BA225 32 Kwords 6D0000h-6D7FFFh BA224 32 Kwords 6C8000h-6CFFFFh BA223 32 Kwords 6C0000h-6C7FFFh BA222 32 Kwords 6B8000h-6BFFFFh BA221 32 Kwords 6B0000h-6B7FFFh BA220 32 Kwords 6A8000h-6AFFFFh BA219 32 Kwords 6A0000h-6A7FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 6 BA218 32 Kwords 698000h-69FFFFh BA217 32 Kwords 690000h-697FFFh BA216 32 Kwords 688000h-68FFFFh BA215 32 Kwords 680000h-687FFFh BA214 32 Kwords 678000h-67FFFFh BA213 32 Kwords 670000h-677FFFh BA212 32 Kwords 668000h-66FFFFh BA211 32 Kwords 660000h-667FFFh BA210 32 Kwords 658000h-65FFFFh BA209 32 Kwords 650000h-657FFFh BA208 32 Kwords 648000h-64FFFFh BA207 32 Kwords 640000h-647FFFh BA206 32 Kwords 638000h-63FFFFh BA205 32 Kwords 630000h-637FFFh BA204 32 Kwords 628000h-62FFFFh BA203 32 Kwords 620000h-627FFFh BA202 32 Kwords 618000h-61FFFFh BA201 32 Kwords 610000h-617FFFh BA200 32 Kwords 608000h-60FFFFh BA199 32 Kwords 600000h-607FFFh Bank 5 BA198 32 Kwords 5F8000h-5FFFFFh BA197 32 Kwords 5F0000h-5F7FFFh BA196 32 Kwords 5E8000h-5EFFFFh BA195 32 Kwords 5E0000h-5E7FFFh BA194 32 Kwords 5D8000h-5DFFFFh BA193 32 Kwords 5D0000h-5D7FFFh BA192 32 Kwords 5C8000h-5CFFFFh BA191 32 Kwords 5C0000h-5C7FFFh BA190 32 Kwords 5B8000h-5BFFFFh BA189 32 Kwords 5B0000h-5B7FFFh BA188 32 Kwords 5A8000h-5AFFFFh BA187 32 Kwords 5A0000h-5A7FFFh BA186 32 Kwords 598000h-59FFFFh BA185 32 Kwords 590000h-597FFFh BA184 32 Kwords 588000h-58FFFFh BA183 32 Kwords 580000h-587FFFh BA182 32 Kwords 578000h-57FFFFh BA181 32 Kwords 570000h-577FFFh BA180 32 Kwords 568000h-56FFFFh BA179 32 Kwords 560000h-567FFFh BA178 32 Kwords 558000h-55FFFFh BA177 32 Kwords 550000h-557FFFh BA176 32 Kwords 548000h-54FFFFh BA175 32 Kwords 540000h-547FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 5 BA174 32 Kwords 538000h-53FFFFh BA173 32 Kwords 530000h-537FFFh BA172 32 Kwords 528000h-52FFFFh BA171 32 Kwords 520000h-527FFFh BA170 32 Kwords 518000h-51FFFFh BA169 32 Kwords 510000h-517FFFh BA168 32 Kwords 508000h-50FFFFh BA167 32 Kwords 500000h-507FFFh Bank 4 BA166 32 Kwords 4F8000h-4FFFFFh BA165 32 Kwords 4F0000h-4F7FFFh BA164 32 Kwords 4E8000h-4EFFFFh BA163 32 Kwords 4E0000h-4E7FFFh BA162 32 Kwords 4D8000h-4DFFFFh BA161 32 Kwords 4D0000h-4D7FFFh BA160 32 Kwords 4C8000h-4CFFFFh BA159 32 Kwords 4C0000h-4C7FFFh BA158 32 Kwords 4B8000h-4BFFFFh BA157 32 Kwords 4B0000h-4B7FFFh BA156 32 Kwords 4A8000h-4AFFFFh BA155 32 Kwords 4A0000h-4A7FFFh BA154 32 Kwords 498000h-49FFFFh BA153 32 Kwords 490000h-497FFFh BA152 32 Kwords 488000h-48FFFFh BA151 32 Kwords 480000h-487FFFh BA150 32 Kwords 478000h-47FFFFh BA149 32 Kwords 470000h-477FFFh BA148 32 Kwords 468000h-46FFFFh BA147 32 Kwords 460000h-467FFFh BA146 32 Kwords 458000h-45FFFFh BA145 32 Kwords 450000h-457FFFh BA144 32 Kwords 448000h-44FFFFh BA143 32 Kwords 440000h-447FFFh BA142 32 Kwords 438000h-43FFFFh BA141 32 Kwords 430000h-437FFFh BA140 32 Kwords 428000h-42FFFFh BA139 32 Kwords 420000h-427FFFh BA138 32 Kwords 418000h-41FFFFh BA137 32 Kwords 410000h-417FFFh BA136 32 Kwords 408000h-40FFFFh BA135 32 Kwords 400000h-407FFFh Bank 3 BA134 32 Kwords 3F8000h-3FFFFFh BA133 32 Kwords 3F0000h-3F7FFFh BA132 32 Kwords 3E8000h-3EFFFFh BA131 32 Kwords 3E0000h-3E7FFFh BA130 32 Kwords 3D8000h-3DFFFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 3 BA129 32 Kwords 3D0000h-3D7FFFh BA128 32 Kwords 3C8000h-3CFFFFh BA127 32 Kwords 3C0000h-3C7FFFh BA126 32 Kwords 3B8000h-3BFFFFh BA125 32 Kwords 3B0000h-3B7FFFh BA124 32 Kwords 3A8000h-3AFFFFh BA123 32 Kwords 3A0000h-3A7FFFh BA122 32 Kwords 398000h-39FFFFh BA121 32 Kwords 390000h-397FFFh BA120 32 Kwords 388000h-38FFFFh BA119 32 Kwords 380000h-387FFFh BA118 32 Kwords 378000h-37FFFFh BA117 32 Kwords 370000h-377FFFh BA116 32 Kwords 368000h-36FFFFh BA115 32 Kwords 360000h-367FFFh BA114 32 Kwords 358000h-35FFFFh BA113 32 Kwords 350000h-357FFFh BA112 32 Kwords 348000h-34FFFFh BA111 32 Kwords 340000h-347FFFh BA110 32 Kwords 338000h-33FFFFh BA109 32 Kwords 330000h-337FFFh BA108 32 Kwords 328000h-32FFFFh BA107 32 Kwords 320000h-327FFFh BA106 32 Kwords 318000h-31FFFFh BA105 32 Kwords 310000h-317FFFh BA104 32 Kwords 308000h-30FFFFh BA103 32 Kwords 300000h-307FFFh Bank 2 BA102 32 Kwords 2F8000h-2FFFFFh BA101 32 Kwords 2F0000h-2F7FFFh BA100 32 Kwords 2E8000h-2EFFFFh BA99 32 Kwords 2E0000h-2E7FFFh BA98 32 Kwords 2D8000h-2DFFFFh BA97 32 Kwords 2D0000h-2D7FFFh BA96 32 Kwords 2C8000h-2CFFFFh BA95 32 Kwords 2C0000h-2C7FFFh BA94 32 Kwords 2B8000h-2BFFFFh BA93 32 Kwords 2B0000h-2B7FFFh BA92 32 Kwords 2A8000h-2AFFFFh BA91 32 Kwords 2A0000h-2A7FFFh BA90 32 Kwords 298000h-29FFFFh BA89 32 Kwords 290000h-297FFFh BA88 32 Kwords 288000h-28FFFFh BA87 32 Kwords 280000h-287FFFh BA86 32 Kwords 278000h-27FFFFh BA85 32 Kwords 270000h-277FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 2 BA84 32 Kwords 268000h-26FFFFh BA83 32 Kwords 260000h-267FFFh BA82 32 Kwords 258000h-25FFFFh BA81 32 Kwords 250000h-257FFFh BA80 32 Kwords 248000h-24FFFFh BA79 32 Kwords 240000h-247FFFh BA78 32 Kwords 238000h-23FFFFh BA77 32 Kwords 230000h-237FFFh BA76 32 Kwords 228000h-22FFFFh BA75 32 Kwords 220000h-227FFFh BA74 32 Kwords 218000h-21FFFFh BA73 32 Kwords 210000h-217FFFh BA72 32 Kwords 208000h-20FFFFh BA71 32 Kwords 200000h-207FFFh Bank 1 BA70 32 Kwords 1F8000h-1FFFFFh BA69 32 Kwords 1F0000h-1F7FFFh BA68 32 Kwords 1E8000h-1EFFFFh BA67 32 Kwords 1E0000h-1E7FFFh BA66 32 Kwords 1D8000h-1DFFFFh BA65 32 Kwords 1D0000h-1D7FFFh BA64 32 Kwords 1C8000h-1CFFFFh BA63 32 Kwords 1C0000h-1C7FFFh BA62 32 Kwords 1B8000h-1BFFFFh BA61 32 Kwords 1B0000h-1B7FFFh BA60 32 Kwords 1A8000h-1AFFFFh BA59 32 Kwords 1A0000h-1A7FFFh BA58 32 Kwords 198000h-19FFFFh BA57 32 Kwords 190000h-197FFFh BA56 32 Kwords 188000h-18FFFFh BA55 32 Kwords 180000h-187FFFh BA54 32 Kwords 178000h-17FFFFh BA53 32 Kwords 170000h-177FFFh BA52 32 Kwords 168000h-16FFFFh BA51 32 Kwords 160000h-167FFFh BA50 32 Kwords 158000h-15FFFFh BA49 32 Kwords 150000h-157FFFh BA48 32 Kwords 148000h-14FFFFh BA47 32 Kwords 140000h-147FFFh BA46 32 Kwords 138000h-13FFFFh BA45 32 Kwords 130000h-137FFFh BA44 32 Kwords 128000h-12FFFFh BA43 32 Kwords 120000h-127FFFh BA42 32 Kwords 118000h-11FFFFh BA41 32 Kwords 110000h-117FFFh BA40 32 Kwords 108000h-10FFFFh BA39 32 Kwords 100000h-107FFFh

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Table 3-1. Bottom Boot Block Address Table Bank Block Block Size (x16) Address Range Bank 0 BA38 32 Kwords 0F8000h-0FFFFFh BA37 32 Kwords 0F0000h-0F7FFFh BA36 32 Kwords 0E8000h-0EFFFFh BA35 32 Kwords 0E0000h-0E7FFFh BA34 32 Kwords 0D8000h-0DFFFFh BA33 32 Kwords 0D0000h-0D7FFFh BA32 32 Kwords 0C8000h-0CFFFFh BA31 32 Kwords 0C0000h-0C7FFFh BA30 32 Kwords 0B8000h-0BFFFFh BA29 32 Kwords 0B0000h-0B7FFFh BA28 32 Kwords 0A8000h-0AFFFFh BA27 32 Kwords 0A0000h-0A7FFFh BA26 32 Kwords 098000h-09FFFFh BA25 32 Kwords 090000h-097FFFh BA24 32 Kwords 088000h-08FFFFh BA23 32 Kwords 080000h-087FFFh BA22 32 Kwords 078000h-07FFFFh BA21 32 Kwords 070000h-077FFFh BA20 32 Kwords 068000h-06FFFFh BA19 32 Kwords 060000h-067FFFh BA18 32 Kwords 058000h-05FFFFh BA17 32 Kwords 050000h-057FFFh BA16 32 Kwords 048000h-04FFFFh BA15 32 Kwords 040000h-047FFFh BA14 32 Kwords 038000h-03FFFFh BA13 32 Kwords 030000h-037FFFh BA12 32 Kwords 028000h-02FFFFh BA11 32 Kwords 020000h-027FFFh BA10 32 Kwords 018000h-01FFFFh BA9 32 Kwords 010000h-017FFFh BA8 32 Kwords 008000h-00FFFFh BA7 4 Kwords 007000h-007FFFh BA6 4 Kwords 006000h-006FFFh BA5 4 Kwords 005000h-005FFFh BA4 4 Kwords 004000h-004FFFh BA3 4 Kwords 003000h-003FFFh BA2 4 Kwords 002000h-002FFFh BA1 4 Kwords 001000h-001FFFh BA0 4 Kwords 000000h-000FFFh OTP Block Address A23 ~ A8 Block Size (x16) Address Range 0000h 128words 000000h-00007Fh Table 3-1-2. Bottom Boot Block OTP Block Addresses After entering OTP block, any issued addresses should be in the range of OTP block address

Table 4. Device Bus Operations Note : L=VIL (Low), H=VIH (High), X=Don’t Care. tions, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes.

Table 5. Command Sequences defined valid register command sequences are stated in Table 5.

1. RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A23 ~ A12)
2. The 4th cycle data of autoselect mode and RD are output data. The others are input data.
3. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD and Device ID.
4. Unless otherwise noted, address bits A23–A11 are don’t cares.
5. The reset command is required to return to read mode.

If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode. If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode. bank was in erase suspend mode.

1. The 3rd and 4th cycle bank address of autoselect mode must be same.
2. 00H for an unprotected block and 01H for a protected block.
3. 0H for handshaking, 1H for non-handshaking
4. The unlock bypass command sequence is required prior to this command sequence.
5. Quadruple word accelerated program is invoked only at Vpp=V

ID ,Vpp setup is required prior to this command sequence. PA1, PA2, PA3, PA4 have the same A23~A2 address.

1. The system may read and program in non-erasing blocks when in the erase suspend mode.

The system may enter the autoselect mode when in the erase suspend mode. The erase suspend command is valid only during a block erase operation, and requires the bank address.

1. The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address.
2. This mode is used only to enable Data Read by suspending the Program operation.
3. Set block address(BA) as either A6 = V

IH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH and A0 = VIL for protected.

1. Command is valid when the device is in Read mode or Autoselect mode.
2. See "Set Burst Mode Congiguration Register" for details.

Table 5. Command Sequences (Continued)

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary DEVICE OPERATION To write a command or command sequence (which includes programming data to the device and erasing blocks of memory), the sys- tem must drive CLK, WE and CE to VIL and OE to VIH when providing address or data. The device provide the unlock bypass mode to save its program time for program oper ation. Unlike the standard program command sequence which is comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the entire device can be erased. Table 3 indicates the address space that each block occupies. The device’s address space is divided into six- teen banks: Bank 0 contains the boot/parameter blocks, and the ot her banks(from Bank 1 to 15) c onsist of uniform blocks. A “bank address” is the address bits required to uniquely select a bank. Si milarly, a “block address” is the address bits required to u niquely select a block. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Character- istics section contains timing specification tables and timing diagrams for write operations. Read Mode The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in asynchronous mode. After completing an Internal Program/Erase R outine, each bank is ready to read array data. The reset com- mand is required to return a bank to the read(or erase-suspend-r ead)mode if DQ5 goes high during an active program/erase opera- tion, or if the bank is in the autoselect mode. The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. That means device enters burst read mode from asynchronous read mode to burst read mode using CLK and AVD signal. When the burst read is finished(or terminated), the device return to asynchronous read mode automatically. Asynchronous Read Mode For the asynchronous read mode a valid address s hould be asserted on A0-A23, while driving AVD and CE to V IL. WE should remain at V IH . The data will appear on DQ0-DQ15. Since the memory ar ray is divided into sixteen banks, each bank remains enabled for read access until the command register contents are altered. Address access time (t AA) is equal to the delay from valid addresses to va lid output data. The chip enable access time(t CE) is the delay from the falling edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. To prevent the memory content from spurious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset. Synchronous (Burst) Read Mode The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, t he sys- tem should determine how many clock cycle s are desired for the initial word(t IACC) of each burst access and what mode of burst operation is desired using "Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further details. The status data also can be re ad during burst read mode by using AVD signal with a bank address. To initiate the synchro- nous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase operation. Continuous Linear Burst Read The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. Note that the device is enabled for asynchronous mode when it first powers up. The initial word is output t IAA after the rising edge of the first CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has internal address boundary that occurs every 16 words. When the device is cross- ing the first word boundary, additional cl ock cycles are needed before data appears for the next address. The number of addtion al clock cycle can varies from zero to three cycles, and the exact number of additional clock cycle depends on the starting addres s of burst read.(Refer to Figure 13) The RDY output indicates this condition to the system by pulsing low. The device will continue to out- put sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until th e system asserts CE high, RESET low or AVD low in conjunction with a new address.(See Table 4.) The reset command does not ter- minate the burst read operation. If the host system crosses the bank boundary while reading in burst mode, and the accessed bank is not programming or erasing, a additional clock cycles are needed as previously mentioned. If the host system crosses the bank boundary while the accessed bank is programming or erasing, that is busy bank, the synchronous read will be terminated.

written to the device, and then wrap back to the first address in the selected address group. cycles as continuous linear mode is needed. driven active for burst read mode. Upon power up, the number of total initial access cycles defaults to seven. the initial word of valid burst data. Using the autoselect command sequence the handshaking feature may be verified in the device. mode. The burst mode configuration register must be set before the device enter burst mode. ware reset with the default setting. Table 6. Burst Address Groups(Wrap mode only) Table 7. Burst Mode Configuration Register Table

mode. Note that hardware reset will set the wait state to the default setting, that is 7 initial cycles. 16 word linear burst modes with no-wrap. and device type by reading a binary code. In addition, this mode allows the host system to verify the block protection or unprotection. terminate the autoselect operation, write Reset command(F0H) into the command register. Table 9. Autoselct Mode Description completed. ICC5 in the DC Characteristics table represents the standby current specification. The device features Automatic Sleep Mode to minimize the dev ice power consumption during both asynchronous and burst mode. are changed, the device provides new data without wait time. Automatic sleep mode current is equal to standby mode current. Table 8. Burst Address Sequences

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Output Disable Mode When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state. Block Protection & Unprotection To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles are written: addresses are don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while specifying with addresses A6, A1 a nd A0 whether that block should be protected (A6 = V IL, A1 = V IH, A0 = V IL) or unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset command). The device offers three types of data protection at the block level:

• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.
• When WP is at VIL, the two outermost blocks are protected.
• When VPP is at VIL, all blocks are protected. Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL. Hardware Reset The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least a period of tRP, the device immediately te rminates any operation in progress, tris tates all outputs, and ignores all read/write com- mands for the duration of the RESET pulse. The device also resets the internal state machine to asynchronous read mode. To ensure data integrity, the interrupted operation should be reinitiated once the device is ready to accept another command sequence. As previously noted, when RESET is held at VSS ± 0.2V, the device enters standby mode. The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program or Erase Routine, the device will be automatically reset to the asyn- chronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the device require s a time of tREADY (during Internal Routines) before the device is ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC Char- acteristics tables for RESET parameters and to Figure 6 for the timing diagram. Software Reset The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The addresses are in Don’t Care state. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in a program command seq uence before programming begins. If the device begins erasure or programming, the reset command is ignored until the operation is completed. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset com- mand is valid between the sequence cycles in an autoselect co mmand sequence. In an autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset com- mand returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend mode, writing the reset command returns that bank to the pr ogram-suspend-read mode. If DQ5 goes high during a program or an erase operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase Suspend) Program The device can be programmed in units of a word. Programming is wr iting 0's into the memory array by executing the Internal Pr o- gram Routine. In order to perform the Internal Program Rout ine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and veri - fies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not require d to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location. Accelerated Program Operation The device provides Single/Quadruple word ac celerated program operations through the Vpp input. Using this mode, faster manu- facturing throughput at the factory is possible. When V ID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. By removing VID returns the device to normal operation mode. Note that Read while Accelerated Programm and Program suspend mode are not guaranteed

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Single word accelerated program operation The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one- cycle (PA - PD) is for program address and data ). Quadruple word accelerated program operation As well as Single word accelerated program, the system would use five-cycle program sequence (One-cycle (XXX - A5H) is for qua- druple word program command, and four cycles are for program address and data).

• Only four words programming is possible
• Each program address must have the same A23~A2 address
• The device automatically generates adequate program pulses and ignores other command after program command Unlock Bypass The device provides the unlock bypass mode to save its operati on time. This mode is possible for program, block erase and chip erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command sequence or the assertion of V ID on V PP pin. Unlike the standard program/erase command sequence that c ontains four/six bus cycles, the unlock bypass program/er ase command sequence needs only two bus cy cles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypa ss mode, the unlock bypass pro- gram/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass m ode. Also, The unlock bypass erase command sequence is com- prised of two bus cycles; writing the unloc k bypass block erase command(80H-30H) or wr iting the unlock bypass chip erase com- mand(80H-10H). This command sequences are the only valid ones fo r erasing the device in the unl ock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode. To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the unlock bypass mode. Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit the unlock bypass mode, just remove the asserted V ID from the V PP pin.(Note that user never float the V pp, that is, Vpp is always connected with VIH, VIL or VID.). Chip Erase To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatic ally pre-programs and verifies t he entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode. Block Erase To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) i s written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. Multiple blocks can be erased sequentially by wr iting the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block addr ess and the Block Erase comman d (30H) can be written to perform the Multi-Block Erase. For th e Multi-Block Erase, only sixt h cycle(block address and 30H) is needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required betwe en the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Era se command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following th e exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command during Block Erase operation. The device provides accelerated erase o perations through the Vpp input. When V ID is asserted on the Vpp input, the device auto- matically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for erase. By removing VID returns the device to normal operation mode.

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Erase Suspend / Resume The Erase Suspend command interrupts the Block Erase to read or program data in a block t hat is not being erased. Also, it is p os- sible to protect or unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50 us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20 us(recovery time) to suspend the erase operation. Therefore system must wait for 20us(recov- ery time) to read the data from the bank which include the block being erased. Otherwise, system can read the data immediately from a bank which don’t include the block being erased without recovery time(max. 20us) after Erase Suspend command. And, after the maximum 20us recovery time, the device is availble for progra mming data in a block that is not being erased. But, when the Eras e Suspend command is written during the block erase time window (50 us) , the device imm ediately terminates the block erase time window and suspends the erase operation. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Sus- pend or Erase Resume command is executed, the addresses are in Don't Care state. Program Suspend / Resume The device provides the Program Suspend/R esume mode. This mode is used to enable Data Read by suspending the Program operation. The device accepts a Program Suspend command in Program mode(including Program operations performed during Erase Suspend) but other commands are ignored. After input of the Program Suspend command, 2us is needed to enter the Pro- gram Suspend Read mode. Therefore system must wait for 2us(r ecovery time) to read the data from the bank which include the block being programmed. Othwewise, syst em can read the data immediately from a bank which don't include block being pro- grammed without ecovery time(max. 2us) after Program Su spend command. Like an Erase Su spend mode, the device can be returned to Program mode by using a Program Resume command. Read While Write Operation The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write o pera- tion. An erase operation may also be suspended to read from or pr ogram to another location within the same bank(except the bloc k being erased). The Read While Write operation is prohibited during the chip erase operation. Figure 12 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-write current specifications. OTP Block Region The OTP Block feature provides a 256-byte Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The OTP Block is customer lockable and sh ipped with itself unlocked, allowing customers to untilize the th at block in any manner they choose. The custom er-lockable OTP Block has the Protection Ve rify Bit (DQ0) set to a "0" for Unlocked state or a "1" for Locked state. The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table8). After the system has written the "Enter OTP Bl ock" Command sequence, it may read the OTP Block by using the addresses (FFFF80h~FFFFFFh) normally and may check the Protection Ve rify Bit (DQ0) by using the "Autoselect Block Protection Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block" Command suquence, a hardware reset or until pow er is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is enabled. Customer Lockable In a Customer lockable device, The OTP Block is one-time programm able and can be locked only once. Note that the Accelerated programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP Block" Command sequence, and then the "Block Protection" Command sqeunce (Table 8) with an OTP Block address. Hardware reset terminates Locking operatio n, and then makes exiting from OTP Block. The Locking opera- tion has to be above 100us. The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the OTP Block space can be modified in any way. Low VCC Write Inhibit To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc < VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode.Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above VLKO.

Mode without erasing the data in the block. Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle. ical zero while OE is a logical one. device is reset to the read mode. operation. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. Table 10. Hardware Sequence Flags

1. DQ2 will toggle when the device performs successive read operations from the erase/program suspended block.
2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.

Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6. the device then returns to the Read Mode without erasing the data in the block. If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure. accepted, the software may check the status of DQ3 following each block erase command. the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. state, data is not valid at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state. Figure 1. Data Polling Algorithms Figure 2. Toggle Bit Algorithms

Table 11. Common Flash Memory Interface Code know which command sets to use to enable flash writes, block erases, and control the flash component.

Table 11. Common Flash Memory Interface Code (Continued)

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary ABSOLUTE MAXIMUM RATINGS Notes : Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+1.5V for periods <20ns. Maximum DC input voltage is +9.5V on VPP which, during transitions, may overshoot to +11.0V for periods <20ns. 3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Symbol Rating Unit Voltage on any pin relative to VSS Vcc Vcc -0.5 to +2.5 VVPP VIN -0.5 to +9.5 All Other Pins -0.5 to +2.5 Temperature Under Bias T bias -30 to +125 °C Storage Temperature T stg -65 to +150 °C Short Circuit Output Current I OS 5m A Operating Temperature T A -30 to + 85 °C DC CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input Leakage Current I LI VIN=VSS to VCC, VCC=VCCmax - 1.0 - + 1.0 µA VPP Leakage Current I LIP VCC=VCCmax , VPP=9.5V - - 35 µA Output Leakage Current I LO VOUT=VSS to VCC, VCC=VCCmax, OE=VIH - 1.0 - + 1.0 µA Active Burst Read Current I CCB1 CE=VIL, OE=VIH -3 0 4 5 m A Active Asynchronous Read Current ICC1 CE=VIL, OE=VIH 10MHz - 30 45 mA 1MHz - 3 5 mA Active Write Current (Note 2) I CC2 CE=VIL, OE=VIH, WE=VIL, VPP=VIH -1 5 3 0 m A Read While Write Current I CC3 CE=VIL, OE=VIH -4 0 7 0 m A Accelerated Program Current I CC4 CE=VIL, OE=VIH , VPP=9.5V - 15 30 mA Standby Current I CC5 CE= RESET=VCC ± 0.2V - 25 70 µA Standby Current During Reset I CC6 RESET = VSS ± 0.2V - 25 70 µA Automatic Sleep Mode(Note 3) I CC7 CE=VSS ± 0.2V, Other Pins=VIL or VIH VIL = VSS ± 0.2V, VIH = VCC ± 0.2V -2 5 7 0 µA Input Low Voltage V IL -0.5 - 0.4 V Input High Voltage V IH VCC-0.4 - V CC+0.4 V Output Low Voltage V OL IOL = 100 µA , VCC=VCCmin - - 0.1 V Output High Voltage V OH IOH = -100 µA , VCC=VCCmin V CC-0.1 - - V Voltage for Accelerated Program V ID 8.5 9.0 9.5 V Low VCC Lock-out Voltage V LKO 1.0 - 1.3 V RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND ) Parameter Symbol Min Typ. Max Unit Supply Voltage V CC 1.7 1.8 1.95 V Supply Voltage VSS 000V Notes: 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. ICC active while Internal Erase or Internal Program is in progress. 3. Device enters automatic sleep mode when addresses are stable for tAA + 60ns.

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary AC TEST CONDITION Parameter Value Input Pulse Levels 0V to V CC Input Rise and Fall Times 5ns Input and Output Timing Levels VCC/2 Output Load CL = 30pF VCC VCC/2 VCC/2 Input Pulse and Test Point Input & Output Test Point CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz) Note : Capacitance is periodically sampled and not 100% tested. Item Symbol Test Condition Min Max Unit Input Capacitance C IN VIN=0V - 10 pF Output Capacitance C OUT VOUT=0V - 10 pF Control Pin Capacitance C IN2 VIN=0V -1 0 p F AC CHARACTERISTICS Synchronous/Burst Read Parameter Symbol (54 MHz) (66 MHz) Unit Min Max Min Max Initial Access Time t IAA - 88.5 - 70 ns Burst Access Time Valid Clock to Output Delay t BA - 14.5 - 11 ns AVD Setup Time to CLK t AVDS 5-5 - n s AVD Hold Time from CLK t AVDH 7-6 - n s AVD High to OE Low t AVDO 0-0 - n s Address Setup Time to CLK t ACS 5-5 - n s Address Hold Time from CLK t ACH 7-6 - n s Data Hold Time from Next Clock Cycle t BDH 4-4 - n s Output Enable to Data t OE - 20 - 20 ns Output Enable to RDY valid t OER - 14.5 - 11 ns CE Disable to High Z t CEZ - 20 - 20 ns OE Disable to High Z t OEZ - 15 - 15 ns CE Setup Time to CLK t CES 7-6 - n s CLK to RDY Setup Time t RDYA - 14.5 - 11 ns RDY Setup Time to CLK t RDYS 4-4 - n s CLK High or Low Time t CH/L 4.5 - 3.5 - ns CLK Fall or Rise Time t CHCL -3- 3 n s Output Load Device Under Test * CL = 30pF including scope and Jig capacitance

5 cycles for initial access shown. Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. Figure 7. 8 word Linear Burst Mode (No Wrap Case)

Figure 8. Asynchronous Mode Read Note: VA=Valid Read Address, RD=Read Data.

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Erase/Program Operation Notes: 1. Not 100% tested. 2. In write timing, addresses are latched on the falling edge of WE. 3. Include the preprogramming time. Parameter Symbol 7B, 7C Unit Min Typ Max WE Cycle Time(Note 1) t WC 100 - - ns Address Setup Time(Note 2) t AS 0-- n s Address Hold Time(Note 2) t AH 50 - - ns Data Setup Time t DS 50 - - ns Data Hold Time t DH 0-- n s Read Recovery Time Before Write t GHWL -0- n s CE Setup Time tCS 5-- n s CE Hold Time t CH 5-- n s WE Pulse Width t WP 70 - - ns WE Pulse Width High t WPH 30 - - ns Latency Between Read and Write Operations t SR/W 0-- n s Word Programming Operation t PGM -1 1 . 5- µs Accelerated Single word Programming Operation t ACCPGM -6 . 5- µs Accelerated Quad word Programming Operation t ACCPGM_QUAD -6 . 5- µs Block Erase Operation (Note 3) t BERS -0 . 7- s e c VPP Rise and Fall Time t VPP 500 - - ns VPP Setup Time (During Accelerated Programming) t VPS 1-- µs VCC Setup Time t VCS 50 - - µs AC CHARACTERISTICS FLASH Erase/Program Performance Notes: 1. 25°C, VCC = 1.8V, 100,000 cycles, typical pattern. 2. System-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each word. In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure. 3. 100K Program/Erase Cycle in all Bank Parameter Limits Unit Comments Min. Typ. Max. Block Erase Time 32 Kword - 0.7 14 sec Includes 00h programming prior to erasure 4 Kword - 0.2 4 Chip Erase Time - 360 - Word Programming Time - 11.5 210 µs Excludes system level overhead Accelerated Sinlge Programming Time (@word) - 6.5 120 Accelerated Quad Programming Time (@word) - 1.6 30 Chip Programming Time - 193 - secAccelerated Single word Chip Programming Time - 109 - Accelerated Quad word Chip Programming Time - 27 - Erase/Program Endurance (Note 3) 100,000 - - Cycles Minimum 100,000 cycles guaran- teed in all Bank

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A16–A23 are don’t care during command sequence unlock cycles.
4. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
5. AVD Setup/Hold Time to CE Enable are same to Asynchronous Mode Read

Figure 10. Program Operation Timing

1. BA is the block address for Block Erase.
2. Address bits A16–A23 are don’t cares during unlock cycles in the command sequence.
3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
4. AVD Setup/Hold Time to CE Enable are same to Asynchronous Mode Read

Figure 11. Chlp/Block Erase Operations

Figure 12. Unlock Bypass Operation Timings

1. VPP can be left high for subsequent programming pulses.
2. Use setup and hold times from conventional program operations.
3. Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp.
4. AVD Setup/Hold Time to CE Enable are same to Asynchronous Mode Read

erase operation in the “busy” bank. Figure 15. Read While Write Operation

bits are "00") and "4N+1" for the address of which the residue is "1"(or the two LSB bits are "01"), etc. "4N+1" address, "4N+2" address or "4N+3" address respectively.

1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.
2. Address 000000H is also a boundry crossing.
3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 16. Crossing of first word boundary in burst read mode.

1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.
2. Address 000000H is also a boundry crossing.
3. No additional clock cycles are needed except for 1st boundary crossing.

1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.
2. Address 000000H is also a boundry crossing.
3. No additional clock cycles are needed except for 1st boundary crossing.

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary 128M Bit(8M x16) Synchronous Burst UtRAM M-die

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary Fig.4 STANDBY MODE STATE MACHINES Default mode after power up is Asynchronous mode(4 Page Read and Asynchronous Write). But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. For entry to PAR mode, drive MRS pin into VIL for over 0.5µs(suspend period) during standby mode after MRS setting has been completed(A4=1, A3=0). If MRS pin is driven into VIH during PAR mode, the device gets back to the standby mode without wake up sequence. CS=VIH CS=VIL, UB or LB=VIL MRS=VIH Power On Initial State (Wait 200µs) Active Standby Mode CS=VIH PAR ModeMRS Setting CS=UB=LB=VIL, WE=VIL, MRS=VILMRS=VIH MRS Setting CS=VIL, WE=VIL, MRS=VIL MRS=VIH MRS=VIL POWER UP SEQUENCE After applying VCC upto minimum operating voltage(2.5V), drive CS High first and then drive MRS High. Then the device gets into the Power Up mode. Wait for minimum 200µs to get into the normal operation mode. During the Power Up mode, the standby current can not be guaranteed. To get the stable standby current level, at least one cycle of active operation should be implemented regardless of wait time duration. To get the appropriate device operation, be sure to keep the following power up sequence. 1. Apply power. 2. Maintain stable power(Vcc min.=2.5V) for a minimum 200µs with CS and MRS high. Fig.3 POWER UP TIMING 200µs VCC VCCQ VCC(Min) VCCQ(Min) Min. 200µs MRS CS Normal Operation Min. 0ns Power Up Mode Min. 0ns

Table 3. ASYNCHRONOUS 4 PAGE READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/0)

1. X must be low or high state.
2. In asynchronous mode, Clock and ADV are ignored.
3. /WAIT pin is High-Z in Asynchronous mode.

Table 5. SYNCHRONOUS BURST READ & SYNCHRONOUS BURST WRITE MODE(A15/A14=1/0)

1. X must be low or high state.
2. X means "Don’t care"(can be low, high or toggling).
3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function.
4. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy

write cycle before change mode into synchronous burst read and synchronous burst write mode.

1. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous

burst write operation to Asynchronous write operation is prohibited.

chronous Burst Write mode, Standby mode and Partial Array Refresh(PAR) mode. Burst Length, Burst Type, Wait Polarity and Latency Count at Synchronous Burst Read/Write mode. tions. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. and Driver Strength uses A16~A17. Refer to the Table below for detailed Mode Register Setting. A18~A22 addresses are "Don’t care" in Mode Register Setting. Table 6. Mode Register Setting according to field of function Table 7. Mode Register Set NOTE : The address bits other than those listed in the table above are reserved for future use. Each field has its own default mode and these default modes are written in blue-bold in the table above. But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. A12 is a reserved bit for future use. A12 must be set as "0". Not all the mode settings are tested. Per the mode settings to be tested, please contact Samsung Product Planning team. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.

• Latency 3 is supported in 52.9MHz with tCD 12ns.

ment at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. transition from Synchronous burst write operation to Asynchronous write operation is prohibited.

0 Low Enable 0 Must 00 0 3* 0 Linear 010 4 w o r d

1 High Enable 1 - 0 0 1 4 1 Interleave 0 1 1 8 word

11 PAR Disable 1 Top Array 0 1 3/4 Array

input) is not issued within 0.5µs, then the device might get into the PAR mode.

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary ASYNCHRONOUS OPERATION Asynchronous 4 Page Read Operation Asynchronous normal read operation starts when CS, OE and UB or LB are driven to VIL under the valid address without tog- gling page addresses(A0, A1). If the page addresses(A0, A1) are toggled under the other valid address, the first data will be out with the normal read cycle time(tRC) and the second, the third and the fourth data will be out with the page cycle time(tPC). (MRS and WE should be driven to VIH during the asynchronous (page) read operation) Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation. Asynchronous Write Operation Asynchronous write operation starts when CS, WE and UB or LB are driven to VIL under the valid address.(MRS and OE should be driven to VIH during the asynchronous write opera- tion.) Clock, ADV, WAIT signals are ignored during the asyn- chronous (page) read operation. SYNCHRONOUS BURST OPERATION Burst mode operations enable the system to get high perfor- mance read and write operation. The address to be accessed is latched on the rising edge of clock or ADV (whichever occurs first). CS should be setup before the address latch. During this first clock rising edge, WE indicates whether the operation is going to be a Read(WE High) or a Write(WE Low). For the optimized Burst Mode to each system, the system should determine how many clock cycles are required for the first data of each burst access(Latency Count), how many words the device outputs at an access(Burst Length) and which type of burst operation(Burst Type : Linear or Interleave) is needed. The Wait Polarity should also be determined.(See Table "Mode Register Set") Synchronous Burst Read Operation The Synchronous Burst Read command is implemented when the clock rising is detected during the ADV low pulse. ADV and CS should be set up before the clock rising. During Read com- mand, WE should be held in VIH. The multiple clock risings(dur- ing low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be out with Latency count and tCD. Synchronous Burst Write Operation The Synchronous Burst Write command is implemented when the clock rising is detected during the ADV and WE low pulse. ADV, WE and CS should be set up before the clock rising. The multiple clock risings(during low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be written in the Latency clock with tDS. A22~A2 A1~A0 CS UB, LB OE Data out High-Z High-Z High-Z Address CS UB, LB WE Data in Data out Fig.6 ASYNCHRONOUS 4-PAGE READ Fig.7 ASYNCHRONOUS WRITE CLK ADV Addr. UB, LB OE Data out CS WAIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Fig.8 SYNCHRONOUS BURST READ(Latency 5, BL 4, WP : Low Enable) Fig.9 SYNCHRONOUS BURST WRITE(Latency 5, BL 4, WP : Low Enable) CLK ADV Addr. UB, LB WE Data in CS WAIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13

write operation is synchronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH. be available on its data pins. This value depends on the input clock frequency. The supported Latency Count is as follows. Table 9. Latency Count support : 3, 4, 5 Table 10. Number of Clocks for 1st Data NOTE : The first data will always keep the Latency. From the second data, some period of wait time might be caused by WAIT pin. burst read or write. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. The first data will be out with the set Latency + tCD. From the second data, the data will be out with tCD from each clock. burst operation can be issued only after the previous burst operation is finished. which accounts for big portion in usage for the mobile handset application environment.

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary SYNCHRONOUS BURST OPERATION TERMINOLOGY WAIT Control(WAIT) The WAIT signal is the device’s output signal which indicates to the host system when the device’s data-out or data-in is valid. To be compatible with the Flash interfaces of various microprocessor types, the WAIT polarity(WP) can be configured. The polarity can be programmed to be either low enable or high enable. For the timing of WAIT signal, the WAIT signal should be set active one clock prior to the data regardless of Read or Write cycle. Burst Type The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in burst sequence table in next page. 123456789 1 0 1 1 1 2 1 3 ADV Read CLK DQ0 DQ1 DQ2 Fig.11 WAIT Control and Read/Write Latency Control(LATENCY : 5, Burst Length : 4, WP : Low Enable) Write D0 D1 D2 DQ3 Data out Data in CS Latency 5 Latency 5 High-ZWAIT High-ZWAIT

Table 11. Burst Sequence

1. Wrap : Burst Address wraps within word boundary and ends after fulfilled the burst length.
2. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.

more refresh cycles, which lead to standby current increase. below 40°C in the phone standby mode. ation. The device supports full drive, 1/2 drive and 1/4 drive. to be refreshed and so the previously stored data will get lost. array as long as MRS pin is not driven to low for over 0.5µs. Table 12. PAR MODE CHARACTERISTIC

1. Only the data in the refreshed block are valid
2. PAR Array can be selected through Mode Register Set(See Page 66)
3. Standby mode is supposed to be set up after at least one active operation.after power up.

ISB1 is measured after 60ms from the time when standby mode is set up.

Table 15. RECOMMENDED DC OPERATING CONDITIONS1)

1. TA=-30 to 85°C, otherwise specified.
2. Overshoot: VCC+1.0V in case of pulse width ≤20ns.
3. Undershoot: -1.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.

Table 14. ABSOLUTE MAXIMUM RATINGS1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional ope ration should be

Table 16. CAPACITANCE1)(f=1MHz, TA=25°C)

1. Capacitance is sampled, not 100% tested.

Table 17. DC AND OPERATING CHARACTERISTICS

1. Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1).
2. Standby mode is supposed to be set up after at least one active operation.after power up.

ISB1 is measured after 60ms from the time when standby mode is set up.

1. tWP(min)=70ns for continuous write operation over 50 times.

Figure 14. AC Output Load Circuit Vtt=0.5 x VCCQ

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
3. In asynchronous read cycle, Clock, ADV and WAIT signals are ignored.

Table 19. ASYNCHRONOUS READ AC CHARACTERISTICS

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
3. In asynchronous 4 page read cycle, Clock, ADV and WAIT signals are ignored.

Table 20. ASYNCHRONOUS PAGE READ AC CHARACTERISTICS

Table 21. ASYNCHRONOUS WRITE AC CHARACTERISTICS(WE Controlled)

1. tWP(min)=70ns for continuous write operation over 50 times.
2. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

1. tCW is measured from the CS going low to the end of write.
2. tAS is measured from the address valid to the beginning of write.
3. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
4. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.
5. Condition for continuous write operation over 50 times : tWP(min)=70ns

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

1. tCW is measured from the CS going low to the end of write.
2. tAS is measured from the address valid to the beginning of write.
3. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
4. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.

Table 22. ASYNCHRONOUS WRITE AC CHARACTERISTICS(UB & LB Controlled)

1. tWP(min)=70ns for continuous write operation over 50 times.

Figure 24. AC Output Load Circuit

Table 29. BURST OPERATION AC CHARACTERISTICS

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 30. BURST READ AC CHARACTERISTICS(CS Toggling Consecutive Burst)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.
5. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 31. BURST READ AC CHARACTERISTICS(CS Low Holding Consecutive Burst)

1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
3. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 32. BURST READ AC CHARACTERISTICS(Last Data Sustaining)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. Multiple clock risings are allowed during low ADV

period. The burst operation starts from the first clock rising.

1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
2. D2 is masked by UB and LB.
3. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 33. BURST WRITE AC CHARACTERISTICS(CS Toggling Consecutive Burst)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
4. D2 is masked by UB and LB.
5. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.
6. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 34. BURST WRITE AC CHARACTERISTICS(CS Low Holding Consecutive Burst)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBSADV
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.

Table 35. BURST READ STOP AC CHARACTERISTICS

1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.

Table 36. BURST WRITE STOP AC CHARACTERISTICS

1. If clock input is halted during burst read operation, the data out will be suspended. During the burst read suspend period, OE high

drives data out to high-Z. If clock input is resumed, the suspended data will be out first.

1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
2. During suspend period, OE high drives DQ to High-Z and OE low drives DQ to Low-Z.

If OE stays low during suspend period, the previous data will be sustained.

1. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 37. BURST READ SUSPEND AC CHARACTERISTICS

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
5. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation. Table 38. BURST READ to ASYNCH. WRITE(Address Latch Type) AC CHARACTERISTICS

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
5. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation. Table 39. BURST READ to ASYNCH. WRITE(Low ADV Type) AC CHARACTERISTICS

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
5. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation. Table 40. ASYNCH. WRITE(Address Latch Type) to BURST READ AC CHARACTERISTICS

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
5. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation. Table 41. ASYNCH. WRITE(Low ADV Type) to BURST READ AC CHARACTERISTICS

Table 42. BURST READ to BURST WRITE AC CHARACTERISTICS

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 43. BURST WRITE to BURST READ AC CHARACTERISTICS

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.

K5L5628JT(B)M Revision 1.0 November 2004 MCP MEMORY Preliminary PACKAGE DIMENSION 115-Ball FINE PITCH BGA Package (measured in millimeters)

0.10 MAX

0.45±0.05 0.32±0.05 1.30±0.10 TOP VIEW 8.00±0.10 12.00±0.10 #A1 12.00±0.10 115-∅ 0.45±0.05 0.80

0.20 M A B ∅

(Datum A) 142765 38 #A1 INDEX MARK 8.00±0.10 12.00±0.10 0.80 910 0.80x9=7.20 0.80x13=10.40 A B C E G D F H J L K M N P (Datum B) 5.20 3.60 A B BOTTOM VIEW