K5A3X40YTC SAMSUNG | Alldatasheet
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MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 1 - Preliminary Document Title Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the spec ifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision History
Revision No. 0.0 Remark Preliminary History Initial Draft Draft Date November 6, 2002
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 2 - Preliminary Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM The K5A3x40YT(B)C featuring single 3.0V power supply is a Multi Chip Package Memory which combines 32Mbit Dual Bank Flash and 4Mbit fCMOS SRAM. The 32Mbit Flash memory is organized as 4M x8 or 2M x16 bit and 4Mbit SRAM is organized as 512K x8 or 256K x16 bit. The memory architecture of flash memory is designed to divide its memory arrays into 71 blocks and this provides highly flexible erase and program capability. This device is capable of reading data from one bank while programming or erasing in the other bank with dual bank organization. The Flash memory performs a program operation in units of 8 bits (Byte) or 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is com- pleted for typically 0.7sec. The 4Mbit SRAM supports low data retention voltage for battery backup operation with low data retention current. The K5A3x40YT(B)C is suitable for the memory of mobile com- munication system to reduce mount area. This device is available in 69-ball TBGA Type package.
FEATURES
- Power Supply voltage : 2.7V to 3.3V
- Organization - Flash : 4,194,304 x 8 / 2,097,152 x 16 bit - SRAM : 524,288 x 8 / 262,144 x 16 bit
- Access Time (@2.7V) - Flash : 70 ns, SRAM : 55 ns
- Power Consumption (typical value) - Flash Read Current : 14 mA (@5MHz) Program/Erase Current : 15 mA Standby mode/Autosleep mode : 5 µA Read while Program or Read while Erase : 25 mA - SRAM Operating Current : 20 mA Standby Current : 0.5 µA
- Secode(Security Code) Block : Extra 64KB Block (Flash)
- Block Group Protection / Unprotection (Flash)
- Flash Bank Size : 8Mb / 24Mb , 16Mb / 16Mb
- Flash Endurance : 100,000 Program/Erase Cycles Minimum
- SRAM Data Retention : 1.5 V (min.)
- Industrial Temperature : -40 °C ~ 85 °C
- Package : 69-ball TBGA Type - 8 x 11mm, 0.8 mm pitch 1.2mm(max.) Thickness GENERAL DESCRIPTION SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. BALL CONFIGURATION BALL DESCRIPTION Ball Name Description A 0 to A 17 Address Input Balls (Common) A-1, A 18 to A 20 Address Input Balls (Flash Memory) DQ 0 to DQ 15 Data Input/Output Balls (Common) RESET Hardware Reset (Flash Memory) WP /ACC Write Protection / Acceleration Program (Flash Memory) Vcc S Power Supply (SRAM) Vcc F Power Supply (Flash Memory) Vss Ground (Common) UB Upper Byte Enable (SRAM) LB Lower Byte Enable (SRAM) BYTE S BYTE S Control (SRAM) BYTE F BYTE F Control (Flash Memory) SA Address Inputs (SRAM) CE F Chip Enable (Flash Memory) CS 1 S Chip Enable (SRAM Low Active) CS2 S Chip Enable (SRAM High Active) WE Write Enable (Common) OE Output Enable (Common) RY/ BY Ready/Busy (Flash memory) N.C No ConnectionTop View (Ball Down) A 7 U B A 8 A 3 A 6 R E S E T L B C S 2 S A 1 9 A 2 A 5 A 1 8 R Y /B Y A 2 0 A 9 A 4 D Q 6 C E F O E D Q 9 D Q 3 D Q 4 D Q 1 3 1 2 3 4 5 6 A B C D E F W P / W E V s s A 1 0 D Q 1A 0 A 1 A 1 7 A 1 1 A 1 2 A 1 5 A 1 3 N .C A 1 4 S A A 1 6 D Q 1 5 B Y T E F 7 8 N .C D Q 8 D Q 2 D Q 1 1 D Q 5 H D Q 1 4 C S 1 S D Q 0 D Q 1 0 V c c F V c c S D Q 1 2 G D Q 7 V s s B Y T E S /A - 1 N .C N .C N .CN .CN .C N .C N .C N .C N .C N .C N .CN .C N .C 9 1 0 K J 69 Ball TBGA , 0.8mm Pitch A C C
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 3 - Preliminary
ORDERING INFORMATION
K 5 A 3 x 4 0 Y T C - T 7 55 Samsung MCP Memory Device Type Dual Bank Boot Block NOR + fCMOS SRAM NOR Flash Density (Bank Size), (Organization) 32 : 32Mbit, (8Mb, 24Mb) (x8/x16 Selectable) 33 : 32Mbit, (16Mb, 16Mb) (x8/x16 Selectable) Block Architecture T = Top Boot Block B = Bottom Boot Block Version C = 4th Generation SRAM Access Time 55 = 55 ns Operating Voltage Range 2.7V to 3.3V Package T = 69 TBGA SRAM Density , Organization 4Mbit, x8/x16 Selectable Bottom Boot Block Figure 1. FUNCTIONAL BLOCK DIAGRAM
Table 1. Flash Memory Top Boot Block Address (K5A3240YT/K5A3340YT)
NOTE: The address range is A20 ∼ A-1 in the byte mode ( BYTE F = V IL ) or A20 ∼ A0 in the word mode ( BYTE F = V IH ). The bank address bits is A20 ∼ A19 for K5A3240YT, A20 for K5A3340YT. Table 2. Secode Block Addresses for Top Boot Devices
Table 3. Flash Memory Bottom Boot Block Address (K5A3240YB/K5A3340YB)
NOTE: The address range is A20 ∼ A-1 in the byte mode ( BYTE F = V IL ) or A20 ∼ A0 in the word mode ( BYTE F = V IH ). The bank address bits is A20 ∼ A19 for K5A3240YB, A20 for K5A3340YB. Table 4. Secode Block Addresses for Bottom Boot Devices
to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mo de. commands are valid only while the Block Erase Operation is in progress. Table 5. Command Sequences
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 9 - Preliminary NOTES: 1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data DA : Dual Bank Address (A19 - A20), BA : Block Address (A12 - A20), X = Don’t care . 2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register. 3. The 4th cycle data of Autoselect mode is output data. The 3rd and 4th cycle bank addresses of Autoselect mode must be same. 4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspen d mode. 5. The Erase Suspend command is applicable only to the Block Erase operation. 6. DQ8 - DQ15 are don’t care in command sequence, except for RD and PD. 7. A11 - A20 are also don’t care, except for the case of special notice. Table 6. Flash Memory Autoselect Codes
Description
BYTE F = V IH BYTE F = V IL Manufacturer ID X X ECH Device Code K5A3240YT (Top Boot Block) 22H X A0H Device Code K5A3240YB (Bottom Boot Block) 22H X A2H Device Code K5A3340YT (Top Boot Block) 22H X A1H Device Code K5A3340YB (Bottom Boot Block) 22H X A3H Block Protection Verification X X 01H (Protected), 00H (Unprotected) Secode Block Indicator Bit (DQ7) X X 80H (Factory locked), 00H (Not factory locked) Table 7. Flash Memory Operation Table
- L = V IL (Low), H = V IH (High), V ID = 8.5V~12.5V, D IN = Data in, D OUT = Data out, X = Don't care.
- WP /ACC and RESET ball are asserted at Vcc F ±0.3 V or Vss ±0.3 V in the Stand-by mode.
- Addresses must be composed of the Block address (A12 - A20).
The Block Protect and Unprotect operations may be implemented via programming equipment too. Refer to the "Block Group Protection and Unprotection". will be temporarily unprotected.
Table 8. SRAM Operation Table 1) Address input for byte operation.
whenever CE F or OE is high. lected by making CE F high ( CE F = V IH ). Refer to the DC characteristics for more details on stand-by modes. The device outputs are disabled when OE is High ( OE = V IH ). The output balls are in high impedance state. and always available to the system. When addresses are changed, the device provides new data without wait time. allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. autoselect operation, write Reset command (F0H) into the command register. Figure 2. Auto Sleep Mode Operation
sequence comprises only two bus cycles. gram address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode. Figure 5. Chip Erase Command Sequence or CE F , while the Block Erase command is latched on the rising edge of WE or CE F . except the Erase Suspend command.
when blocks from Bank1 and another blocks from Bank2 are loaded all together for the multi-block erase operation. programming equipment at the user’s site. The device is shipped with all block groups unprotected. ation is executing. The block protection and unprotection can be implemented by the following method. Table 9. Block Group Protection & Unprotection (Algorithm) and Switching Waveforms of Block Group Protect & Unprotect Operation. at V IL , the two outermost boot blocks remain protected. Figure 8. Temporary Block Group Unprotect Sequence
Figure 9. Block Group Protection & Unprotection Algorithms NOTE: All blocks must be protected before unprotect operation is executing.
Table 10. Flash Memory Block Group Address (Top Boot Block)
Table 11. Flash Memory Block Group Address (Bottom Boot Block)
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 19 - Preliminary Write Protect ( WP ) The WP /ACC ball has two useful functions. The one is that certain boot block is protected by the hardware method not to use V ID . The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph) . When the WP /ACC ball is asserted at V IL , the device can not perform program and erase operation in the two "outermost" 8K byte boot blocks independently of whether those blocks were protected or unprotected using the method described in "Block Group pro- tection/Unprotection". The write protected blocks can only be read. This is useful method to preserve an important program data. The two outermost 8K byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or the two blocks containing the highest addresses in a top-boot-congfigured device. (K5A3240YT/K5A3340YT : BA69 and BA70, K5A3240YB/K5A3340YB : BA0 and BA1) When the WP /ACC ball is asserted at V IH , the device reverts to whether the two outermost 8K byte boot blocks were last set to be protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last prote cted or unprotected using the method described in "Block Group protection/unprotection". Recommend that the WP /ACC ball must not be in the state of floating or unconnected, or the device may be led to malfunction. Secode(Security Code) Block Region The Secode Block feature provides a Flash memory region to be stored unique and permanent identification code, that is, Electron ic Serial Number (ESN), customer code and so on. This is primarily intended for customers who wish to use an Electronic Serial Num - ber (ESN) in the device with the ESN protected against modification. Once the Secode Block region is protected, any further modifi- cation of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Secode Block is factory locked or customer lockable. Before the device is shipped, the factory locked Secode Block is writte n on the special code and it is protected. The Secode Indicator bit (DQ7) is permanently fixed at "1" and it is not changed. The customer lockable Secode Block is unprotected, therefore it is programmed and erased. The Secode Indicator bit (DQ7) of it is permanently fixed at "0" and it is not changed. But once it is protected, there is no procedure to unprotect and modify the Secode Block. The Secode Block region is 64K bytes in length and is accessed through a new command sequence (see Table 5). After the system has written the Enter Secode Block command sequence, the system may read the Secode Block region by using the same addresses of the boot blocks (8KBx8). The K5A3240YT/K5A3340YT occupies the address of the byte mode 3F0000H to 3FFFFFH (word mode 1F8000H to 1FFFFFH) and the K5A3240YB/K5A3340YB type occupies the address of the byte mode 000000H to 00FFFFH (word mode 000000H to 007FFFH). This mode of operation continues until the system issues the Exit Secode Block com- mand sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to read mode. Accelerated Program Operation Accelerated program operation reduces the program time. This is one of two functions provided by the WP /ACC ball. When the WP / ACC ball is asserted as V HH , the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP /ACC ball returns the device to normal operation. Recommend that the WP /ACC ball must not be asserted at V HH except accelerated program operation, or the device may be damaged. In addition, the WP /ACC ball must not be in the state of floating or unconnected, otherwise the device may be led to malfunc- tion. Software Reset The reset command provides that the device is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a pro- gram command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode. If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the Erase Suspend state.
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 20 - Preliminary Hardware Reset Flash memory offers a reset feature by driving the RESET ball to V IL . The RESET ball must be kept low (V IL ) for at least 500ns. When the RESET ball is driven low, any operation in progress will be terminated and the internal state machine will be reset to the standby mode after 20us. If a hardware reset occurs during a program operation, the data at that particular location will be lo st. Once the RESET ball is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that all the data output balls are tri-stated for the duration of the RESET pulse. The RESET ball may be tied to the system reset ball. If a system reset occurs during the Internal Program and Erase Routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware f rom the Flash memory. Power-up Protection To avoid initiation of a write cycle during Vcc F Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the read mode. Low Vcc F Write Inhibit To avoid initiation of a write cycle during Vcc F power-up and power-down, a write cycle is locked out for Vcc F less than 1.8V. If Vcc F < V LKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode. Subsequent writes will be ignored until the Vcc F level is greater than V LKO . It is the user ′s responsi- bility to ensure that the control balls are logically correct to prevent unintentional writes when Vcc F is above 1.8V. Write Pulse Glitch Protection Noise pulses of less than 5ns(typical) on CE F , OE , or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited under any one of the following conditions : OE = V IL , CE F = V IH or WE = V IH . To initiate a write, CE F and WE must be "0", while OE is "1". Commom Flash Memory Interface Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific info rma- tion of the device, such as memory size, byte/word configuration, and electrical features. Once this information has been obtain ed, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H in word mode(or address AAH in byte mode), the device enters the CFI mode. And then if the system writes the address shown in Table 12, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command.
Table 12. Common Flash Memory Interface Code
- The number of blocks in Bank2 is device dependent.
Table 13. Hardware Sequence Flags
- DQ2 will toggle when the device performs successive read operations from the erase suspended block.
- If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.
data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block. a block that is not being erased, toggling is halted and valid data is produced at DQ6. the device then returns to the Read Mode without erasing the data in the block. If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 24 - Preliminary RY/ BY : Ready/ Busy Flash memory has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept any read/write or erase operation. When the RY/ BY ball is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If Flash memory is placed in an Erase Suspend mode, the RY/ BY output will be High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase, RY/ BY is also valid after the rising edge of the sixth WE pulse. The ball is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required for proper operation. Vcc F Ready / Busy open drain output Device Vss where Σ IL is the sum of the input currents of all devices tied to the Ready / Busy ball. DQ3 : Block Erase Timer The status of the multi-block erase operation can be detected via the DQ3 ball. DQ3 will go High if 50 µs of the block erase time win- dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept fu rther write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block eras e time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command. DQ2 : Toggle Bit 2 The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the devi ce executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase Suspend mode, DQ2 toggles only if an address in the erasing block is read. If a non-erasing block address is read during the Era se Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while th e device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation from the program operation. Rp Rp = Vcc F (Max.) - V OL (Max.) IOL + Σ IL 2.9V 2.1mA + Σ IL
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 26 - Preliminary RECOMMENDED OPERATING CONDITIONS (Voltage reference to Vss) Parameter Symbol Min Typ. Max Unit Supply Voltage Vcc F , Vcc S 2.7 3.0 3.3 V Supply Voltage Vss 0 0 0 V ABSOLUTE MAXIMUM RATINGS NOTES: voltage on RESET and WP /ACC balls are 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns. 3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended period s may affect reliability. Parameter Symbol Rating Unit Voltage on any ball relative to Vss Vcc Vcc F , Vcc S -0.3 to +3.6 V RESET V IN -0.3 to +12.5 WP /ACC -0.3 to +12.5 All Other Balls -0.3 to Vcc+0.3V(Max.3.6V) Temperature Under Bias T bias -40 to +125 °C Storage Temperature T stg -65 to +150 °C Operating Temperature T A -40 to +85 °C DC CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Com- mon Input Leakage Current ILI V IN =Vss to Vcc, Vcc=Vcc max -1.0 - +1.0 µA Output Leakage Current ILO V OUT =Vss to Vcc, Vcc=Vcc max, OE =V IH -1.0 - +1.0 µA Input Low Level V IL -0.3 - 0.5 V Input High Level V IH 2.2 - Vcc +0.3 V Output Low Level V OL IOL = 2.1mA, Vcc = Vcc min - - 0.4 V Output High Level V OH IOH = -1.0mA, Vcc = Vcc min 2.3 - - V Flash RESET Input Leakage Current ILIT Vcc F =Vcc max, RESET =12.5V - - 35 µA WP/ ACC Input Leakage Current ILIW Vcc F =Vcc max, WP/ ACC=12.5V - - 35 µA Active Read Current (1) ICC 1 CE F =V IL , OE =V IH 5MHz - 14 20 mA 1MHz - 3 6 Active Write Current (2) ICC 2 CE F =V IL , OE =V IH - 15 30 mA Read While Program Current (3) ICC 3 CE F =V IL , OE =V IH - 25 50 mA Read While Erase Current (3) ICC 4 CE F =V IL , OE =V IH - 25 50 mA Program While Erase Suspend Current ICC 5 CE F =V IL , OE =V IH - 15 35 mA ACC Accelerated Program Current IACC CE F =V IL , OE =V IH ACC Ball - 5 10 mAVcc F Ball - 15 30 Standby Current ISB 1 Vcc F =Vccmax, CE F =Vcc F ± 0.3V, RESET =Vcc F ± 0.3V, WP /ACC=Vcc F ± 0.3V or Vss ± 0.3V - 5 18 µA Standby Curren During Reset ISB 2 Vcc F =Vcc F max , RESET =Vss ±0.3V, WP /ACC=Vcc F ± 0.3V or Vss ± 0.3V - 5 18 µA
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 27 - Preliminary DC CHARACTERISTICS (Continued) NOTES: 1. The I CC current listed includes both the DC operating current and the frequency dependent component(at 5 MHz). The read current is typically 14 mA (@ Vcc F =3.0V , OE at V IH .) 2. I CC active during Internal Routine(program or erase) is in progress. 3. I CC active during Read while Write is in progress. 4. The high voltage ( V HH or V ID ) must be used in the range of Vcc F = 3.0V ± 0.3V 5. Not 100% tested. 6. Typical values are measured at Vcc F = Vcc S = 3.0V, Ta=25 °C , not 100% tested. Parameter Symbol Test Conditions Min Typ Max Unit Flash Automatic Sleep Mode ISB 3 V IH =Vcc F ±0.3V, V IL =V SS ±0.3V, OE =V IL, IOL =I OH =0 - 5 18 µA Voltage for WP /ACC Block Temporarily Unprotect and Program Acceleration (4) V HH Vcc F = 3.0V ± 0.3V 8.5 - 12.5 V Voltage for Autoselect and Block Protect (4) V ID Vcc F = 3.0V ± 0.3V 8.5 - 12.5 V Low Vcc F Lock-out Voltage (5) V LKO 1.8 - 2.5 V SRAM Operating Current ICC 1 Cycle time=1 µs, 100% duty, CS 1 S ≤0.2, CS2 S ≥Vcc S -0.2V, LB ≤0.2V and/or UB ≤0.2V All outputs open, V IN ≤0.2V or V IN ≥Vcc S -0.2V, BYTE S =Vcc S ± 0.3V or Vss ± 0.3V - - 3 mA ICC 2 Cycle time=Min, 100% duty, CS 1 S =V IL , CS2 S =V IH , LB =V IL and/or UB = V IL , All outputs open, V IN =V IL or V IH, BYTE S =Vcc S ± 0.3V or Vss ± 0.3V - 20 27 mA Standby Current ISB CS 1 S ≥Vcc S -0.2V, CS2 S ≥Vcc S -0.2V ( CS 1 S controlled) or CS2 S ≤0.2V (CS2 S controlled), BYTE S =Vcc S ± 0.3V or Vss ± 0.3V, Other input =0~Vcc S - 0.5 10 µA AC TEST CONDITION Parameter Value Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2 Output Load C L = 30pF CAPACITANCE (T A = 25 °C, Vcc F = Vcc S = 3.3V, f = 1.0MHz) NOTE: Capacitance is periodically sampled and not 100% tested. Item Symbol Test Condition Min Max Unit Input Capacitance C IN V IN =0V - 18 pF Output Capacitance C OUT V OUT =0V - 20 pF Control Ball Capacitance C IN2 V IN =0V - 18 pF Vcc Vcc/2 Vcc/2 Input Pulse and Test Point Input & Output Test Point Output Load * CL= 30pF including Scope C L Device and Jig Capacitance
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 28 - Preliminary Alternate WE Controlled Write NOTES: 1. Not 100% tested. 2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms. Parameter Symbol 70ns 80ns Unit Min Max Min Max Write Cycle Time (1) tWC 70 - 80 - ns Address Setup Time tAS 0 - 0 - ns tASO 55 - 55 - ns Address Hold Time tAH 45 - 45 - ns tAHT 0 - 0 - ns Data Setup Time tDS 35 - 35 - ns Data Hold Time tDH 0 - 0 - ns Output Enable Setup Time (1) tOES 0 - 0 - ns Output Enable Hold Time Read (1) tOEH1 0 - 0 - ns Toggle and Data Polling (1) tOEH2 10 - 10 - ns CE F Setup Time tCS 0 - 0 - ns CE F Hold Time tCH 0 - 0 - ns Write Pulse Width tWP 35 - 35 - ns Write Pulse Width High tWPH 25 - 25 - ns Programming Operation Word tPGM 14(typ.) 14(typ.) µs Byte 9(typ.) 9(typ.) µs Accelerated Programming Operation Word tACCPGM 9(typ.) 9(typ.) µs Byte 7(typ.) 7(typ.) µs Block Erase Operation (2) tBERS 0.7(typ.) 0.7(typ.) sec Vcc F Set Up Time tVCS 50 - 50 - µs Write Recovery Time from RY/ BY tRB 0 - 0 - ns RESET High Time Before Read tRH 50 - 50 - ns RESET to Power Down Time tRPD 20 - 20 - µs Program/Erase Valid to RY/ BY Delay tBUSY 90 - 90 - ns V ID Rising and Falling Time tVID 500 - 500 - ns RESET Pulse Width tRP 500 - 500 - ns RESET Low to RY/ BY High tRRB - 20 - 20 µs RESET Setup Time for Temporary Unprotect tRSP 1 - 1 - µs RESET Low Setup Time tRSTS 500 - 500 - ns RESET High to Address Valid tRSTW 200 - 200 - ns Read Recovery Time Before Write tGHWL 0 - 0 - ns CE High during toggling bit polling tCEPH 20 - 20 - ns OE High during toggling bit polling tOEPH 20 - 20 - ns Write(Erase/Program)Operations Flash AC CHARACTERISTICS
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 29 - Preliminary Flash AC CHARACTERISTICS Write(Erase/Program)Operations Alternate CE F Controlled Writes NOTES: 1. Not 100% tested. 2.This does not include the preprogramming time. Parameter Symbol 70ns 80ns Unit Min Max Min Max Write Cycle Time (1) tWC 70 - 80 - ns Address Setup Time tAS 0 - 0 - ns Address Hold Time tAH 45 - 45 - ns Data Setup Time tDS 35 - 35 - ns Data Hold Time tDH 0 - 0 - ns Output Enable Setup Time (1) tOES 0 - 0 - ns Output Enable Hold Time Read (1) tOEH1 0 - 0 - ns Toggle and Data Polling (1) tOEH2 10 - 10 - ns WE Setup Time tWS 0 - 0 - ns WE Hold Time tWH 0 - 0 - ns CE F Pulse Width tCP 35 - 35 - ns CE F Pulse Width High tCPH 25 - 25 - ns Programming Operation Word tPGM 14(typ.) 14(typ.) µs Byte 9(typ.) 9(typ.) µs Accelerated Programming Operation Word tACCPGM 9(typ.) 9(typ.) µs Byte 7(typ.) 7(typ.) µs Block Erase Operation (2) tBERS 0.7(typ.) 0.7(typ.) sec BYTE Switching Low to Output HIGH-Z tFLQZ 25 - 25 - ns ERASE AND PROGRAM PERFORMANCE NOTES: 1. 25 °C, Vcc F = 3.0V 100,000 cycles, typical pattern . 2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte. In the preprogramming step of the Internal Erase Routine, all bytes are programmed to 00H before erasure. Parameter Limits Unit Comments Min Typ Max Block Erase Time - 0.7 15 sec Excludes 00H programming prior to erasure Chip Erase Time - 49 - sec Word Programming Time - 14 330 µs Excludes system-level overhead Byte Programming Time - 9 210 µs Excludes system-level overhead Accelerated Byte/Word Program Time Word Mode - 9 210 µs Excludes system-level overhead Byte Mode - 7 150 µs Excludes system-level overhead Chip Programming Time Word Mode - 28 84 sec Excludes system-level overhead Byte Mode - 36 108 sec Erase/Program Endurance 100,000 - - cycles Minimum 100,000 cycles guaran- teed
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 30 - Preliminary Read Operations Flash SWITCHING WAVEFORMS OE Address tCE tOEH1 CE F Outputs WE HIGH-Z Output Valid tRC Address Stable tAA tOE tOH HIGH-Z tDF RY/ BY HIGH NOTE: 1. Not 100% tested. Parameter Symbol 70ns 80ns Unit Min Max Min Max Read Cycle Time tRC 70 - 80 - ns Address Access Time tAA - 70 - 80 ns Chip Enable Access Time tCE - 70 - 80 ns Output Enable Time tOE - 25 - 25 ns CE F & OE Disable Time (1) tDF - 16 - 16 ns Output Hold Time from Address, CE F or OE tOH 0 - 0 - ns OE Hold Time tOEH1 0 - 0 - ns
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 31 - Preliminary Hardware Reset/Read Operations Flash SWITCHING WAVEFORMS Parameter Symbol 70ns 80ns Unit Min Max Min Max Read Cycle Time tRC 70 - 80 - ns Address Access Time tAA - 70 - 80 ns Chip Enable Access Time tCE - 70 - 80 ns Output Hold Time from Address, CE F or OE tOH 0 - 0 - ns RESET Pulse Width tRP 500 - 500 - ns RESET High Time Before Read tRH 50 - 50 - ns RESET Address CE F Outputs High-Z tRC Address Stable tAA tCE tOH tRH tRHtRP Output Valid
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 32 - Preliminary Alternate WE Controlled Program Operations Flash SWITCHING WAVEFORMS NOTES: 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence. OE Address tCS CE F DATA WE tAH tOH tDF tAS tRC tOE tCE tDS tDH tWP tOES tPGM Status DOUT 555H PA PA A0H Data Polling tCH PD tWPH RY/ BY tBUSY tRB tWC Parameter Symbol 70ns 80ns Unit Min Max Min Max Write Cycle Time tWC 70 - 80 - ns Address Setup Time tAS 0 - 0 - ns Address Hold Time tAH 45 - 45 - ns Data Setup Time tDS 35 - 35 - ns Data Hold Time tDH 0 - 0 - ns CE F Setup Time tCS 0 - 0 - ns CE F Hold Time tCH 0 - 0 - ns OE Setup Time tOES 0 - 0 - ns Write Pulse Width tWP 35 - 35 - ns Write Pulse Width High tWPH 25 - 25 - ns Programming Operation Word tPGM 14(typ.) 14(typ.) us Byte 9(typ.) 9(typ.) us Accelerated Programming Operation Word tACCPGM 9(typ.) 9(typ.) µs Byte 7(typ.) 7(typ.) µs Read Cycle Time tRC 70 - 80 - ns Chip Enable Access Time tCE - 70 - 80 ns Output Enable Time tOE - 25 - 25 ns CE F & OE Disable Time tDF - 16 - 16 ns Output Hold Time from Address, CE F or OE tOH 0 - 0 - ns Program/Erase Valide to RY/ BY Delay tBUSY 90 - 90 - ns Recovery Time from RY/ BY tRB 0 - 0 - ns
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 33 - Preliminary Alternate CE F Controlled Program Operations Flash SWITCHING WAVEFORMS NOTES: 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence. OE Address WE DATA CE F tAH tAS tDS tDH tCP tOES A0H 555H PA PA Status DOUT Data Polling tCPHtWS tPGM RY/ BY tBUSY tRB PD tWC Parameter Symbol 70ns 80ns Unit Min Max Min Max Write Cycle Time tWC 70 - 80 - ns Address Setup Time tAS 0 - 0 - ns Address Hold Time tAH 45 - 45 - ns Data Setup Time tDS 35 - 35 - ns Data Hold Time tDH 0 - 0 - ns OE Setup Time tOES 0 - 0 - ns WE Setup Time tWS 0 - 0 - ns WE Hold Time tWH 0 - 0 - ns CE F Pulse Width tCP 35 - 35 - ns CE F Pulse Width High tCPH 25 - 25 - ns Programming Operation Word tPGM 14(typ.) 14(typ.) µs Byte 9(typ.) 9(typ.) µs Accelerated Programming Operation Word tACCPGM 9(typ.) 9(typ.) µs Byte 7(typ.) 7(typ.) µs Program/Erase Valide to RY/ BY Delay tBUSY 90 - 90 - ns Recovery Time from RY/ BY tRB 0 - 0 - ns
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 34 - Preliminary Flash SWITCHING WAVEFORMS Parameter Symbol 70ns 80ns Unit Min Max Min Max Chip Enable Access Time tCE - 70 - 80 ns CE F to BYTE Switching Low or High tELFL /t ELFH - 5 - 5 ns BYTE Switching Low to Output HIGH-Z tFLQZ - 25 - 25 ns BYTE Switching High to Output Active tFHQV - 25 - 25 ns OE tFLQZ CE F DQ0-DQ7 BYTE WE BYTE Timing Diagram for Write Operation The falling edge of the last WE signal CE F BYTE tHOLD (t AH ) DQ15/A-1 tELFL Address Input (A-1) tSET (t AS ) Word to Byte Timing Diagram for Read Operation Byte to Word Timing Diagram for Read Operation Data Output (DQ0-DQ7) DQ8-DQ14 Data Output (DQ8-DQ14) Data Output (DQ15) OE tFHQV CE F DQ0-DQ7 BYTE DQ15/A-1 tELFH Data Output DQ8-DQ14 Address Input (A-1) Data Output (DQ8-DQ14) (DQ15) tCE tCE Data Output (DQ0-DQ7)
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 35 - Preliminary Flash SWITCHING WAVEFORMS Chip/Block Erase Operations Parameter Symbol 70ns 80ns Unit Min Max Min Max Write Cycle Time tWC 70 - 80 - ns Address Setup Time tAS 0 - 0 - ns Address Hold Time tAH 45 - 45 - ns Data Setup Time tDS 35 - 35 - ns Data Hold Time tDH 0 - 0 - ns OE Setup Time tOES 0 - 0 - ns CE F Setup Time tCS 0 - 0 - ns Write Pulse Width tWP 35 - 35 - ns Write Pulse Width High tWPH 25 - 25 - ns Read Cycle Time tRC 70 - 80 - ns Vcc F Set Up Time tVCS 50 - 50 - µs OE Address tCS CE F DATA WE tAH tAS tRC tDS tDH 80H AAHAAH 55H 30H 10H for Chip Erase 555H 2AAH 555H 555H 2AAH BA 555H for Chip Erase tWPH tWP tOES 55H RY/ BY tWC tVCS Vcc F NOTE: BA : Block Address
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 36 - Preliminary Read While Write Operations Flash SWITCHING WAVEFORMS Parameter Symbol 70ns 80ns Unit Min Max Min Max Write Cycle Time tWC 70 - 80 - ns Write Pulse Width tWP 35 - 35 - ns Write Pulse Width High tWPH 25 - 25 - ns Address Setup Time tAS 0 - 0 - ns Address Hold Time tAH 45 - 45 - ns Data Setup Time tDS 35 - 35 - ns Data Hold Time tDH 0 - 0 - ns Read Cycle Time tRC 70 - 80 - ns Chip Enable Access Time tCE - 70 - 80 ns Address Access Time tAA - 70 - 80 ns Output Enable Access Time tOE - 25 - 25 ns OE Setup Time tOES 0 - 0 - ns OE Hold Time tOEH2 10 - 10 - ns CE F & OE Disable Time tDF - 16 - 16 ns Address Hold Time tAHT 0 - 0 - ns CE F High during toggle bit polling tCEPH 20 - 20 - ns NOTE: This is an example in the program-case of the Read While Write function. D A1 : Address of Bank1, DA2 : Address of Bank 2 PA = Program Address at one bank , RA = Read Address at the other bank , PD = Program Data In , RD = Read Data Out OE CE F DQ WE tRC Read Command CommandRead Read Read tAH tAA tCE tAS tAHT tAS tCEPH tOE tOES tWP tOEH2 tDF tDS tDH tDF DA1 DA2 DA1 DA1DA2 DA2 (555H) ( PA ) ( PA ) Valid Output Valid Output Valid In put Valid Output Valid In put Status Address (A0H) (PD) tRCtRC tRCtWC tWC
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 37 - Preliminary Data Polling During Internal Routine Operation Flash SWITCHING WAVEFORMS Parameter Symbol 70ns 80ns Unit Min Max Min Max Program/Erase Valid to RY/ BY Delay tBUSY 90 - 90 - ns Chip Enable Access Time tCE - 70 - 80 ns Output Enable Time tOE - 25 - 25 ns CE F & OE Disable Time tDF - 16 - 16 ns Output Hold Time from Address, CE F or OE tOH 0 - 0 - ns OE Hold Time tOEH2 10 - 10 - ns OE tCE tOEH2 CE F DQ7 WE tOE HIGH-Z tDF NOTE: *DQ7=Vaild Data (The device has completed the internal operation). DQ7 *DQ7 = Valid Data tOH tPGM or t BERS HIGH-ZValid DataDQ0-DQ6 Data In Data In WE RY/ BY Timing Diagram During Program/Erase Operation The rising edge of the last WE signal CE F RY/ BY tBUSY Entire progrming or erase operation Status Data
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 38 - Preliminary Toggle Bit During Internal Routine Operation Flash SWITCHING WAVEFORMS tDH CE F Address* OE DQ6/DQ2 WE RY/ BY Data In tAHT tAHTtASO tAS tCEPHtOEH2 tOEPH Status Data tO E Status Data Status Data Array Data Out NOTE: Address for the write operation must include a bank address (A19~A20) where the data is written. DQ 6 WE DQ 2 Enter Embedded Erasing Erase Suspend Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Erase Suspend Read Erase Erase Complete Erase Suspend Read NOTE: DQ2 is read from the erase-suspended block. Toggle DQ 2 and DQ 6 with OE or CE F Parameter Symbol 70ns 80ns Unit Min Max Min Max Output Enable Access Time tOE - 25 - 25 ns OE Hold Time tOEH2 10 - 10 - ns Address Hold Time tAHT 0 - 0 - ns Address Setup tASO 55 - 55 - ns Address Setup Time tAS 0 - 0 - ns Data Hold Time tDH 0 - 0 - ns CE F High during toggle bit polling tCEPH 20 - 20 - ns OE High during toggle bit polling tOEPH 20 - 20 - ns
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 39 - Preliminary RESET Timing Diagram Flash SWITCHING WAVEFORMS Parameter Symbol 70ns 80ns Unit Min Max Min Max RESET Pulse Width tRP 500 - 500 - ns RESET Low to Valid Data (During Internal Routine) tREADY - 20 - 20 µs RESET Low to Valid Data (Not during Internal Routine) tREADY - 500 - 500 ns RESET High Time Before Read tRH 50 - 50 - ns RY/ BY Recovery Time tRB 0 - 0 - ns RESET High to Address Valid tRSTW 200 - 200 - ns RESET Low Set-up Time tRSTS 500 - 500 - ns RESET tRP Power-up and RESET Timing Diagram CE F or OE RY/ BY tREADY tRB RESET CE F or OE RY/ BY tRH tREADY tRP Reset Timings NOT during Internal Routine Reset Timings during Internal Routine High RESET tAA Vcc F Address DATA tRSTS
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 40 - Preliminary Block Group Protect & Unprotect Operations Flash SWITCHING WAVEFORMS CE F Temporary Block Group Unprotect Program or Erase Command Sequence R ESET WE tRSP RY/ BY tVID V ID Vss,V IL , or V IH Vss,V IL , or V IH tRRB tVID BGA,A6 A1,A0 RESET CE F WE D ATA OE Vss,V IL , 60H 60H 40H Status* Block Group Protect / Unprotect Verify 1 µs Block Group Protect:150 µs Block Group UnProtect:15ms NOTES: Block Group Protect (A6= V IL , A1= V IH , A0= V IL ) , Status=01H Block Group Unprotect (A6= V IH , A1= V IH , A0= V IL ) , Status=00H BGA = Block Group Address (A12 ~ A20) RY/ BY V ID Valid ValidValid tBUSY tRB or V IH Vss,V IL , or V IH
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 41 - Preliminary SRAM DATA RETENTION CHARACTERISTICS 1. CS 1 S ≥Vcc S -0.2V, CS2 S ≥Vcc S -0.2V( CS 1 S controlled) or CS2 S ≤0.2V(CS2 S controlled) 2. Typical values are measured at Vcc=3.0V, Ta=25 °C , not 100% tested. Item Symbol Test Condition Min Typ Max Unit Vcc S for data retention V DR CS 1 S ≥Vcc S -0.2V 1.5 - 3.3 V Data retention current IDR Vcc S =3.0V, CS 1 S ≥Vcc S -0.2V - 0.5 10 µA Data retention set-up time tSDR See data retention waveform 0 - - ns Recovery time tRDR tRC - - SRAM AC CHARACTERISTICS Parameter List Symbol 55ns Units Min Max Read Read cycle time tRC 55 - ns Address access time tAA - 55 ns Chip select to output tCO1 , t CO2 - 55 ns Output enable to valid output tOE - 25 ns UB , LB Access Time tBA - 55 ns Chip select to low-Z output tLZ1 , t LZ2 10 - ns UB , LB enable to low-Z output tBLZ 10 - ns Output enable to low-Z output tOLZ 5 - ns Chip disable to high-Z output tHZ1 , t HZ2 0 20 ns UB , LB disable to high-Z output tBHZ 0 20 ns Output disable to high-Z output tOHZ 0 20 ns Output hold from address change tOH 10 - ns Write Write cycle time tWC 55 - ns Chip select to end of write tCW 45 - ns Address set-up time tAS 0 - ns Address valid to end of write tAW 45 - ns UB , LB Valid to End of Write tBW 45 - ns Write pulse width tWP 40 - ns Write recovery time tWR 0 - ns Write to output high-Z tWHZ 0 20 ns Data to write time overlap tDW 20 - ns Data hold from write time tDH 0 - ns End write to output low-Z tOW 5 - ns
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 42 - Preliminary SRAM TIMING DIAGRAMS Address Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled , CS 1 S = OE =V IL , CS2 S = WE =V IH , UB or/and LB =V IL ) TIMING WAVEFORM OF READ CYCLE(2) ( WE =V IH ) Data ValidHigh-Z tRC CS 1 S Address UB , LB OE Data out tAA tRC tOH tOHtAA tCO1 tBA tOE tOLZ tBLZ tLZ tOHZ tBHZ tHZ NOTES (READ CYCLE) 1. tHZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection. CS2 S tCO2
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 43 - Preliminary SRAM TIMING DIAGRAMS TIMING WAVEFORM OF WRITE CYCLE(1) ( WE Controlled) Address CS 1 S Data Undefined UB , LB WE Data in Data out TIMING WAVEFORM OF WRITE CYCLE(2) ( CS 1 S Controlled) Address Data Valid UB , LB WE Data in Data out High-Z High-Z tWC tCW(2) tWR(4) tAW tBW tWP(1) tAS(3) tDHtDW tWHZ tOW tWC tCW(2) tAW tBW tWP(1) tDHtDW tWR(4) High-Z High-ZData Valid tAS(3) CS 2 S CS 1 S CS 2 S tCW(2)
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 44 - Preliminary Address Data Valid UB , LB WE Data in Data out High-Z High-Z TIMING WAVEFORM OF WRITE CYCLE(3) ( UB , LB Controlled) NOTES (WRITE CYCLE) 1. A wri te occurs during the overlap(t WP ) of low CS 1 S and low WE . A write begins when CS 1 S goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran- sition when CS 1 S goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS 1 S going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS 1 S or WE going high. tWC tCW(2) tBW tWP(1) tDHtDW tWR(4) tAW SRAM DATA RETENTION WAVE FORM CS 1 S controlled V cc S 2.7V 2.2V V DR CS 1 S Vss Data Retention Mode CS 1 S ≥Vcc S - 0.2V tSDR tRDR tAS(3) CS 1 S CS 2 S CS 2 S controlled V cc S 2.7V 0.4V V DR CS 2 S Vss Data Retention Mode tSDR tRDR CS 2 S ≤0.2V tCW(2)
MCP MEMORYK5A3x40YT(B)C Revision 0.0 November 2002 - 45 - Preliminary PACKAGE DIMENSION 69-Ball Tape Ball Grid Array Package (measured in millimeters) Top View Bottom View Side View 0.45 ± 0.05 0.08MAX 0 .3 2 ± 0 .0 5 1 .1 0 ± 0 .1 0 #A1 14 27 6 5 38 A B C E G D F H 0.80 x9=7.20 A 0 .8 0 x 9 = 7 .2 0 1 1 .0 0 ± 0 .1 0 3.60 69- ∅ 0.45 ± 0.05 910 J K 3 .6 0 0 .8 0 B 8.00 ± 0.10
0.20 M A B ∅
(Datum A) (Datum B) 1 1 .0 0 ± 0 .1 0 8.00 ± 0.10 11.00 ± 0.10 0.80