K524G2GACB-A050 SAMSUNG | Alldatasheet
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Revision 1.3 November 2009 K524G2GACB-A050 - 1 - MCP MEMORY MCP Specification 4Gb NAND Flash + 2Gb Mobile DDR * Samsung Electronics reserves the right to change products or specification without notice. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
Revision 1.3 November 2009 K524G2GACB-A050 - 2 - MCP MEMORY Document Title Multi-Chip Package MEMORY 4Gb (256M x16) NAND Flash Memory / 2Gb (64M x32) Mobile DDR SDRAM 1. Revision History Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site. http://samsungelectronics.com/semiconductors/products/products_index.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any ques- tions, please contact the SAMSUNG branch office near you. Revision No. History Draft Date Remark 0.0 1.0 1.1 1.2 1.3 Initial issue. - 4Gb NAND Flash W-die_ Ver 0.0 - 2Gb M-DDR SDRAM B-die_Ver 1.0 <NAND>_Ver 1.0 - Corrected Errata - ECC requirement updated - Final issue <DRAM>_Ver 1.2 Ver 1.1 - Corrected errata. Ver 1.2 - Finalized. <Common> - Finalized <NAND>_Ver 1.01 1. ECC requirement updated <NAND>_Ver 1.1 1. ECC requirement updated 2. Chapter 3.10 : Updated note for Random data input <M-DDR>_Ver 1.3 <Common> - Added DDR333. May. 8, 2009 Aug. 17, 2009 Sep. 03, 2009 Oct. 8, 2009 Nov. 26, 2009 Preliminary Final Final Final Final
Revision 1.3 November 2009 K524G2GACB-A050 - 3 - MCP MEMORY Multi-Chip Package MEMORY 4Gb (256M x16) NAND Flash Memory / 2Gb (64M x32) Mobile DDR SDRAM 2. FEATURES SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. <Common>
- Operating Temperature : -25°C ~ 85°C
- Package : 137-ball FBGA Type - 10.5 x 13 x 1.2mmt, 0.8mm pitch <NAND Flash>
- Voltage Supply : 1.7V ~ 1.95V
- Organization - Memory Cell Array : (256M + 8M) x 16bit for 4Gb (512M + 16M) x 16bit for 8Gb DDP - Data Register : (1K + 32) x 16bit
- Automatic Program and Erase - Page Program : (1K + 32)Word - Block Erase : (64K + 2K)Word
- Page Read Operation - Page Size : (1K + 32)Word - Random Read : 40µs(Max.) - Serial Access : 42ns(Min.)
- Fast Write Cycle Time - Page Program time : 250µs(Typ.) - Block Erase Time : 2ms(Typ.)
- Command/Address/Data Multiplexed I/O Port
- Hardware Data - Program/Erase Lockout During Power Transitions
- Reliable CMOS Floating-Gate Technology -Endurance : 100K Program/Erase Cycles with 1bit/256Word ECC for x16
- Command Driven Operation
- Unique ID for Copyright Protection <Mobile DDR>
- VDD/VDDQ = 1.8V/1.8V
- Double-data-rate architecture; two data transfers per clock cycle
- Bidirectional data strobe(DQS)
- Four banks operation
- Differential clock inputs(CK and CK
- MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave)
- EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control
- Internal Temperature Compensated Self Refresh
- All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
- Data I/O transactions on both edges of data strobe, DM for masking.
- Edge aligned data output, center aligned data input.
- No DLL; CK to DQS is not synchronized.
- DM0 - DM3 for write masking only.
- Auto refresh duty cycle - 7.8us
- Clock stop capability Note: 1) CAS Latency - DM is internally loaded to match DQ and DQS identically. Operating Frequency DDR333 DDR400 Speed @CL31) 166MHz 200MHz Address configuration Organization Bank Row Column 64Mx32 BA0,BA1 A0 - A13 A0 - A9
Revision 1.3 November 2009 K524G2GACB-A050 - 4 - MCP MEMORY 3. GENERAL DESCRIPTION The K524G2GACB is a Multi Chip Package Memory which combines 4Gbit NAND Flash Memory an 2Gbi t DDR synchronous high data rate Dynamic RAM. NAND cell provides the most cost-effective solution for the so lid state application market. A program operation can be performe d in typical 250µs on the (1K+32)Word page and an erase operation can be performed in typical 2ms on a (64K+2K)Word block. Data in the data register can be read out at 42ns cycle time per Word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functi ons including pulse repetition, w here required, and internal ver ification and margining of data. Even the write-intensive systems can take advantage of the device ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an opt imum solution for large nonvolat ile storage applications such as solid state file storage and other portable applications requiring non-volatility. In 2Gbit Mobile DDR, Synchronous design ma ke a device controlled precisely with the use of system clock. Range of operating fre quencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The K524G2GACB is suitable for use in data memory of mobile comm unication system to reduce not only mount area but also power c on- sumption. This device is available in 137-ball FBGA Type.
Revision 1.3 November 2009 K524G2GACB-A050 - 5 - MCP MEMORY 4. Pin CONFIGURATION
137 FBGA: Top View (Ball Down)
- 123456789 1 0 BN C N C /REn CLEn VCCn /CEn /WEn VDDd VSSd NC C VSSd A4d /WPn ALEn VSSn R/Bn DQ31d DQ30d VDDQd VSSQd D VDDd A5d A7d A9d DQ25d DQ27d DQ29d DQ28d VSSQd VDDQd E A6d A8d CKEd DQ18d DQS3d DQ22d DM3d DQ26d VDDQd VSSQd F A12d A11d NC DQ17d DQ19d DQ24d DQ23d DM2d VSSQd VDDQd GN C /RASd DQ15d DQ16d DQS1d DM1d DQ9d CKd VDDQd VSSQd H VDDd /CASd DQ20d DQ21d DQ13d DQ12d DQS2d /CKd VSSd VDDd J VSSd /CSd BA0d DQ14d DQ11d DQ10d DQS0d DM0d VSSQd VDDQd K /WEd BA1d A10d A0d DQ7d DQ8d DQ6d DQ4d VDDQd VSSQd L A1d A2d A3d DQ0d DQ1d DQ2d DQ3d DQ5d VDDQd VSSQd M VDDd VSSd A13d NC IO3n IO5n IO14n IO7n VSSQd VDDQd N IO0n IO1n IO2n IO10n VCCn IO6n IO13n IO15n VDDQd VSSQd PN C IO8n IO9n IO11n IO12n VSSn IO4n VDDd VSSd NC NAND M-DDR Power Ground NC/DNU
Revision 1.3 November 2009 K524G2GACB-A050 - 6 - MCP MEMORY 5. PIN DESCRIPTION Pin Name Pin Function(M-DDR) Pin Name Pin Function(NAND Flash) CKd,/CKd System Clock & Differential Clock /CEn Chip Enable CKEd Clock Enable /REn Read Enable /CSd Chip Selection /WPn Write Protection /RASd Row Address Strobe /WEn Write Enable /CASd Column Address Strobe ALEn Address Latch Enable /WEd Write Enable CLEn Command Latch Enable A0d ~ A13d Address Input R/B n Ready/Busy Output BA0d ~ BA1d Bank Address Input IO0n ~ IO15n Data Input/Output DM0d ~ DM3d Input Data Mask VCCn Power Supply DQS0d~DQS3d Data Input / Output VSSn Ground DQ0d ~ DQ31d Data Input / Output VDDd Power Supply Pin Name Pin Function VDDQd Data Out Power NC No Connection VSSd Ground DNU Do Not Use VSSQd DQ Ground
Revision 1.3 November 2009 K524G2GACB-A050 - 7 - MCP MEMORY 6. ORDERING INFORMATION K5 2 4G 2G A C B - A 0 50 Samsung MCP Memory(2chips) Device Type NAND Flash + Mobile DDR NAND Flash Density, Organization 4G : 4Gbit, x16 Flash Block Architecture C : Uniform Block Version B : 3rd Generation M-DDR Speed 50 : 400Mbps@CL3 Operating Voltage A: 1.8V / 1.8V Package A : FBGA(HF, LF) Mobile DDR Density, Organization 2G : 2Gbit, x32 NAND Flash Speed 0 : None
Revision 1.3 November 2009 K524G2GACB-A050 - 8 - MCP MEMORY 7. FUNCTIONAL BLOCK DIAGRAM /WPn CLEn /WEn /REn R/Bn /CEn IO0n to IO15n ALEn 4Gb NAND Flash Memory VCCn VSSn DQ0d~DQ31d2Gb Mobile DDR VDDd VDDQd VSSd VSSQd CKEd /CSd /RASd /CASd CKd,/CKd /WEd A0d ~ A13d BA0d ~ BA1d DM0d ~ DM3d DQS0d ~ DQS3d
Revision 1.3 November 2009 K524G2GACB-A050 - 9 - MCP MEMORY 8. PACKAGE DIMENSION Units:millimeters
0.10 MAX
0.32±0.05 1.10±0.10 TOP VIEW 10.50±0.10 13.00±0.10 #A1 137-∅0.45±0.05 0.80
0.20 M A B ∅
(Datum A) 142765 38 #A1 INDEX MARK 10.50±0.10 13.00±0.10 0.80 910 0.80 x 9 = 7.20 0.80 x 14 = 11.20 A B C E G D F H J L K M N R (Datum B) 5.60 3.60 BOTTOM VIEW P 137-Ball Fine pitch Ball Grid Array Package (measured in millimeters) A B
Revision 1.3 November 2009 K524G2GACB-A050 - 10 - MCP MEMORY 4Gb (256M x16) NAND Flash W-die
Figure 1. Functional Block Diagram(x8) Figure 2. Array Organization(x8) Table 1. Array address : (x8) Column Address : Starting Address of the Register.
- The device ignores any additional input of address cycles than required.
- A30 is Row address for 8G DDP .
64 Bytes
1 Block = 64 Pages
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)Byte x 64 Pages
1 Device = (2K+64)B x 64Pages x 4,096 Blocks
1 Device = (2K+64)B x 64Pages x 8,192 Blocks
Figure 3. Functional Block Diagram(x16) Figure 4. Figure 2-2. Array Organization(x16) Table 2. Array address : (x16) Column Address : Starting Address of the Register.
- The device ignores any additional input of address cycles than required.
- A29 is Row address for 8G DDP .
32 Words
1 Page = (1K + 32)Word
1 Block = (1K + 32)Word x 64 Pages
1 Device = (1K + 32)Word x 64Pages x 4,096 Blocks
1 Device = (1K + 32)Word x 64Pages x 8,192 Blocks
1.0 Product Introduction
five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. are removed, system performance for solid-state disk application is significantly increased. Table 3. Command Sets 1) Random Data Input/Output can be executed in a page. Any undefined command inputs are prohibited except for above command set of Table 3.
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1.1 ABSOLUTE MAXIMUM RATINGS
NOTE : 1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1.2 RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA=-25 to 85°C)
1.3 DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions otherwise noted.) NOTE : 1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2) Typical value is measured at Vcc=1.8V, TA=25°C. Not 100% tested. Parameter Symbol Rating Unit Voltage on any pin relative to VSS VCC -0.6 to + 2.45 VVIN -0.6 to + 2.45 VI/O -0.6 to Vcc + 0.3 (< 2.45V) Temperature Under Bias T BIAS -30 to +125 °C Storage Temperature T STG -65 to +150 °C Short Circuit Current IOS 5m A Parameter Symbol Min Typ. Max Unit Supply Voltage V CC 1.7 1.8 1.95 V Supply Voltage V SS 000V Parameter Symbol Test Conditions Min Typ Max Unit Operating Current Page Read with Serial Access ICC1 tRC=42ns CE=VIL, IOUT=0mA - 15 25 mA Program I CC2- - Erase I CC3- - Stand-by Current(TTL) I SB1 4Gb,CE=VIH, WP=0V/VCC -- 1 8Gb DDP ,CE=VIH, WP=0V/VCC -- 2 Stand-by Current(CMOS) I SB2 4Gb,CE=VCC-0.2, WP=0V/VCC -1 0 5 0 µA 8Gb DDP , CE=VCC-0.2, WP=0V/VCC -2 0 1 0 0 Input Leakage Current I LI VIN=0 to Vcc(max) - - ±10 Output Leakage Current I LO VOUT=0 to Vcc(max) - - ±10 Input High Voltage VIH(1) -0 . 8 x V CC - VCC+0.3 V Input Low Voltage, All inputs VIL(1) - -0.3 - 0.2xVcc Output High Voltage Level V OH IOH=-100µAV c c - 0 . 1 - - Output Low Voltage Level V OL IOL=100uA - - 0.1 Output Low Current(R/B)I OL(R/B)V OL= 0 . 1 V 34- m A
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1.4 VALID BLOCK
NOTE : 1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2) The 1st block, which is placed on 00h block address, is g uaranteed to be a valid block up to 1K program/erase cycles with x 8 : 1bit/ 512Byte, x16 : 1bit/ 256Word ECC. 3) Each mono chip in th KF88GxxQ2W has maximum 40 invalid blocks.
1.5 AC TEST CONDITION
(TA=-25 to 85°C, Vcc=1.7V~1.95V unless otherwise noted) 1.6 CAPACITANCE(TA=25°C, VCC=1.8V, f=1.0MHz) NOTE : Capacitance is periodically sampled and not 100% tested.
1.7 MODE SELECTION
NOTE : 1) X can be VIL or VIH. 2) WP should be biased to CMOS high or CMOS low for standby. Parameter Symbol Min Typ. Max Unit 4Gb N VB 4,016 - 4,096 Blocks 8Gb DDP N VB 8.032 - 8,192 Blocks Parameter Value Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2 Output Load 1 TTL GATE and CL=30pF Item Symbol Test Condition Min Max Unit Input/Output Capacitance (Mono) C I/O VIL=0V - 10 pF Input Capacitance (Mono) C IN VIN=0V - 10 pF Input/Output Capacitance (DDP) C I/O VIL=0V - 20 pF Input Capacitance (DDP) CIN VIN=0V - 20 pF CLE ALE CE WE RE WP Mode HLL HX Read Mode Command Input L H L H X Address Input(5clock) HLL HH Write Mode Command Input L H L H H Address Input(5clock) L L L H H Data Input L L L H X Data Output X X X X H X During Read(Busy) X X X X X H During Program(Busy) X X X X X H During Erase(Busy) X X (1) X X X L Write Protect XXHXX 0V/VCC(2) Stand-by
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1.8 Read / Program / Erase Characteristics
NOTE : 1) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V Vcc and 25°C temperature.
1.9 AC Timing Characteristics for Command / Address / Data Input
NOTE : 1) The transition of the corresponding control pins must occur only once while WE is held low 2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle Parameter Symbol Min Typ Max Unit Program Time t PROG - 250 750 µs Number of Partial Program Cycles Nop - - 4 cycles Block Erase Time t BERS -2 1 0 m s Parameter Symbol Min Max Unit CLE Setup Time tCLS(1) 21 - ns CLE Hold Time t CLH 5- n s CE Setup Time tCS(1) 21 - ns CE Hold Time tCH 5- n s WE Pulse Width t WP 21 - ns ALE Setup Time tALS(1) 21 - ns ALE Hold Time tALH 5- ns Data Setup Time tDS(1) 20 - ns Data Hold Time tDH 5- n s Write Cycle Time t WC 40 - ns WE High Hold Time tWH 10 - ns Address to Data Loading Time tADL(2) 100 - ns
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1.10 AC Characteristics for Operation
NOTE : 1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5 µs. Parameter Symbol Min Max Unit Data Transfer from Cell to Register t R -4 0 µs ALE to RE Delay t AR 10 - ns CLE to RE Delay t CLR 10 - ns Ready to RE Low t RR 20 - ns RE Pulse Width t RP 21 - ns WE High to Busy t WB -1 0 0 ns WP Low to WE Low (disable mode) tWW 100 - ns WP High to WE Low (enable mode) Read Cycle Time t RC 42 - ns RE Access Time t REA -3 0 n s CE Access Time t CEA -3 5 n s RE High to Output Hi-Z t RHZ - 100 ns CE High to Output Hi-Z tCHZ -3 0 n s CE High to ALE or CLE Don’t Care t CSD 0- n s RE High to Output Hold t ROH 15 - ns CE High to Output Hold tCOH 15 - ns RE High Hold Time t REH 10 - ns Output Hi-Z to RE Low t IR 0- n s RE High to WE Low t RHW 100 - ns WE High to RE Low t WHR 60 - ns Device Resetting Time(Read/Program/Erase) t RST - 5/10/500(1) µs
2.0 NAND Flash Technical Notes
2.1 Initial Invalid Block(s)
to be a valid block up to 1K program/erase cycles with x8:1bit/ 512Byte, x16:1bit/256Word ECC.
2.2 Identifying Initial Invalid Block(s)
ure 5). Any intentional erasure of the original initial invalid block information is prohibited. Figure 5. Flow chart to create initial invalid block table
Revision 1.3 November 2009 K524G2GACB-A050 - 19 - MCP MEMORY NAND Flash Technical Notes (Continued)
2.3 Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the a ctual data. Block replacement should be done upon erase or program error. ECC : Error Correcting Code --> Hamming code Example) 1bit correction & 512-byte Note) A repetitive page read operation on the same block without erase may cause bit errors, which could be accumulated over time and exceed the coverage of ECC. Software scheme such as caching into RAM is recommended. Program Flow Chart Failure Mode Detection and Countermeasure sequence Write Erase Failure Status Read af ter Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement Read Up to 1 Bit-Failure Verity ECC -> ECC Correction Start I/O 6 = 1 ? I/O 0 = 0 ? No* Write 80h Write Address Write Data Write 10h Read Status Register Program Completed or R/B = 1 ? Program Error Yes No Yes : If program operation results in an error, map out the block including the page in error and copy the target data to another block.
Revision 1.3 November 2009 K524G2GACB-A050 - 20 - MCP MEMORY NAND Flash Technical Notes (Continued) Block Replacement * Step1 When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’) * Step3 Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’. * Step4 Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme. Erase Flow Chart Read Flow Chart Start I/O 6 = 1 ? I/O 0 = 0 ? No* Write 60h Write Block Address Write D0h Read Status Register or R/B = 1 ? Erase Error Yes No : If erase operation results in an error, map out the failing block and replace it with another block. * Erase Completed Yes Start Verify ECC No Write 00h Write Address Read Data ECC Generation Reclaim the Error Page Read Completed Yes Write 30h Buffer memory of the controller. 1st Block A Block B (n-1)th nth (page) 1st (n-1)th nth (page) an error occurs.
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2.4 Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0. From the LSB page to MSB page DATA IN: Data (1) Data (64) (1) (2) (3) (32) (64) Data register Page 0 Page 1 Page 2 Page 31 Page 63 Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) (2) (32) (3) (1) (64) Data register Page 0 Page 1 Page 2 Page 31 Page 63
Revision 1.3 November 2009 K524G2GACB-A050 - 23 - MCP MEMORY NOTE : Device I/O DATA ADDRESS I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 4Gb(x8) I/O 0 ~ I/O 7 ~2,112byte A0~A7 A8~A11 A12~A19 A20~A27 A28~A29 8Gb DDP(x8) I/O 0 ~ I/O 7 ~2,112byte A0~A7 A8~A11 A12~A19 A20~A27 A28~A30 4Gb(x16) I/O 0 ~ I/O 15 ~1,056Word A0~A7 A8~A10 A11~A18 A19~A26 A27~A28 8Gb DDP(x16) I/O 0 ~ I/O 15 ~1,056Word A0~A7 A8~A10 A11~A18 A19~A26 A27~A29
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3.0 TIMING DIAGRAMS
3.1 Command Latch Cycle
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3.2 Address Latch Cycle
3.3 Input Data Latch Cycle
Col. Add1 tCS tWC tWP tALS tDS tDH tALH tALS tWH tWC tWP tDS tDH tALH tALS tWH tWC tWP tDH tALH tALS tWH tDS tDH tWP I/Ox Col. Add2 Row Add1 Row Add2 tWC tWH tALH tALS tDS tDH Row Add3 tALH tCLS tDS CE CLE WE DIN 0 DIN 1 DIN final ALE tALS tCLH tWC tCH tDS tDH tDS tDH tDS tDH tWP tWH tWP tWP I/Ox ≈≈≈
Revision 1.3 November 2009 K524G2GACB-A050 - 26 - MCP MEMORY 3.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L) NOTE : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
3.5 Status Read Cycle
≈≈≈≈ I/Ox tCHZ tRHZ tRP CE WE CLE RE 70h Status Output tCLR tCLH tWP tCH tDS tDH tREA tIR tRHOH tCOHtWHR tCEA tCLS I/Ox tCHZ tRHZ tCS
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3.6 Read Operation
3.7 Read Operation(Intercepted by CE)
00h Col. Add1 Col. Add2 Row Add1 Dout N Dout N+1 Column Address Row Address tWB tAR tR tRC tRHZ tRR Dout M tWC Row Add2 30h tCLR I/Ox Row Add3 CE CLE R/B WE ALE RE Busy 00h Dout N Dout N+1 Dout N+2 Row AddressColumn Address tWB tAR tCHZ tR tRR tRC 30hI/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 tCOH tCLR tCSD
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3.8 Random Data Output In a Page
B tAR tR tRR 30h 05h Column Address Dout M Dout M+1I/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Col Add1 Col Add2Row Add3 tCLR E0h tWHR tREAtRC tRHW
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3.9 Page Program Operation
NOTE : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. CE CLE R/B WE ALE RE 80h 70h I/O0 Din N Din 10hM SerialData Input Command Column Address Row Address 1 up to m Byte Serial Input Program Command Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program tPROGtWB tWC tWC tWC I/Ox Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3 tADL tWHR
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3.10 Page Program Operation with Random Data Input
N Din 10hM Serial Data Input Command Column Address Row Address Serial Input Program Command Read Status Command tPROGtWB tWC tWC ≈ ≈ 85h Random Data Input CommandColumn Address tWC Din J Din K Serial Input ≈ ≈I/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Col. Add1 Col. Add2Row Add3 tADL tADL tWHR NOTE : 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2) After serial input of data for random data input, status read(70h) command can be issued for reading status, and only status bit(I/O 6) is valid.
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3.11 Copy-Back Program Operation with Random Data Input
Column Address Row Address Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program tPROG tWB tWC Busy tWB tR Busy 10h Copy-Back Data Input Command 35h Column Address Row Address Data 1 Data N ≈≈Col Add1 Col Add2 Row Add1 Row Add2 Col Add1 Col Add2 Row Add1 Row Add2 Row Add3Row Add3 70h tADL tWHR Data 1 Data N tRC CE CLE R/B WE ALE RE I/Ox NOTE : 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
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3.12 Block Erase Operation
I/O0=1 Error in Erase D0h 70h I/O 0 Busy tWB tBERS I/O0=0 Successful Erase Row Address tWC ≈Auto Block Erase Setup Command I/Ox Row Add1 Row Add2 Row Add3 tWHR
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3.13 Read ID Operation
3.13.1 ID Definition Table
90 ID : Access command = 90H
Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle 4Gb(x8) ACh 00h 15h 56h 8Gb DDP(x8) A3h 01h 15h 5Ah 4Gb(x16) BCh 00h 55h 56h 8Gb DDP(x16) B3h 01h 55h 5Ah
Description
Page Size, Block Size,Redundant Area Size, Organization Plane Number, Plane Size, ECC Level CE CLE WE ALE RE 90h Read ID Command Maker Code Device Code 00h ECh tREA Address 1cycle I/Ox tAR Device 4th cyc.Code 3rd cyc. 5th cyc.
Revision 1.3 November 2009 K524G2GACB-A050 - 34 - MCP MEMORY 3rd ID Data 4th ID Data ITEM Description I/O # 7 6 5 4 3 2 1 0 Internal Chip Number Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
Cache Program Not supported supported ITEM Description I/O # 7 6 5 4 3 2 1 0 Page Size (without Redundant Area) 1KB 2KB 4KB 8KB Block Size (without Redundant Area) 64KB 128KB 256KB 512KB Redundant Area Size (Byte/512byte) Reserved Reserved Organization X8 X16 Reserved 0 or 1
Revision 1.3 November 2009 K524G2GACB-A050 - 35 - MCP MEMORY 5th ID Data ITEM Description I/O # 7 6 5 4 3 2 1 0 ECC level 1bit ECC/512Byte 2bit ECC/512Byte 4bit ECC/512Byte Reserved Plane Number Plane Size (without Redundant Area) 64KB 128KB 256KB 512KB 1Gb 2Gb 4Gb 8Gb Reseved Reserved 0
4.0 Device Operation
4.1 PAGE READ
selected column address up to the last column address. data output can be operated multiple times regardless of how many times it is done in a page. Figure 8. Read Operation
4.2 PAGE PROGRAM
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. mand(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. valid command is written to the command register. Figure 9. Program & Read Status Operation Figure 10. Random Data Input In a Page
4.3 COPY-BACK PROGRAM
buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need to be reloaded. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 12. Figure 11. Page Copy-Back Program Operation 1) Copy-Back Program operation is allowed only within the same memory plane. Figure 12. Page Copy-Back Program Operation with Random Data Input
4.4 BLOCK ERASE
accidentally erased due to external noise conditions. operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence. There is no limitation for the number of repetition.
Figure 13. Block Erase Operation
4.5 READ STATUS
Table 4. Status Register Definition for 70h Command 1) I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
4.6 Read ID
ister remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence. Figure 14. Read ID Operation
4.7 RESET
B pin changes to low for tRST after the Reset command is written. Refer to Figure 15 below. Figure 15. RESET Operation Table 5. Device Status Device 4th Cyc.CodeECh 3rd Cyc. 5th Cyc.
4.8 READY/BUSY
Figure 16. Rp vs tr ,tf & Rp vs ibusy where IL is the sum of the input currents of all devices tied to the R/B pin.
5.0 DATA PROTECTION & POWER UP SEQUENCE
ure 17. The two step command sequence for program/erase provides additional software protection. Figure 17. AC Waveforms for Power Transition
5.1 WP AC TIMING GUIDE
Enabling WP during erase and program busy is prohibited. Figure 18. Program Operation Figure 19. Erase Operation
Revision 1.3 November 2009 K524G2GACB-A050 - 44 - MCP MEMORY 2Gb (64M x32) M-DDR SDRAM B-die
Figure 1. State diagram
2.1 Mode Register Set(MRS)
A7 ~ A13 is used for test mode. BA0 and BA1 must be set to low for proper MRS operation. Figure 2. Mode Register Set
0 Sequential
1 Interleave
0 BT Burst Length 0 R F U 1) 0 0 0 CAS Latency
Table 1. Burst address ordering for burst length
2.2 Extended Mode Register Set(EMRS)
are used for partial array self refresh and A5 - A7 are used for driver strength control. "High" on BA1 and"Low" on BA0 are u sed for EMRS. Figure 3. Extended Mode Register Set
2.3 Internal Temperature Compensated Self Refresh (TCSR)
- In order to save power consumption, this Mobile DRAM includes the internal temperature sensor and control units to control the self refresh-
cycle automatically according to the real device temperature.
- TCSR ranges for IDD6 shown in the table are as an example only. Max IDD6 valus for 45°C, 85°C are guaranteed. Typical values for 85 °C,
70 °C, 45 °C and 15 °C are obtained from device characterization.
- If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
2.4 Partial Array Self Refresh (PASR)
- In order to save power consumption, Mobile DDR SDRAM includes PASR option.
- Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array.
Figure 4. EMRS code and TCSR , PASR
Revision 1.3 November 2009 K524G2GACB-A050 - 50 - MCP MEMORY 3. Absolute maximum ratings NOTE : 1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. 2) Functional operation should be restricted to recommend operation condition. 3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 4. DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, Tc = -25°C to 85°C) NOTE : 1) Under all conditions, VDDQ must be less than or equal to VDD. 2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 3) Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 2.7 V Voltage on VDD supply relative to VSS VDD -0.5 ~ 2.7 V Voltage on VDDQ supply relative to VSS VDDQ -0.5 ~ 2.7 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 1.0 W Short circuit current IOS 50 mA Parameter Symbol Min Max Unit Note Supply voltage(for device with a nominal VDD of 1.8V) VDD 1.7 1.95 V 1 I/O Supply voltage VDDQ 1.7 1.95 V 1 Input logic high voltage ( for Add.) VIH(DC) 0.8 x VDDQ VDDQ+0.3 V Input logic high voltage (for Data) 0.7 x VDDQ VDDQ+0.3 V Input logic low voltage ( for Add.) VIL(DC) -0.3 0.2 x VDDQ V Input logic low voltage (for Data) -0.3 0.3 x VDDQ V Output logic high voltage VOH(DC) 0.9 x VDDQ - V IOH = -0.1mA Output logic low voltage VOL(DC) - 0.1 x VDDQ V IOL = 0.1mA Input leakage current II -2 2 uA 3 Output leakage current IOZ -5 5 uA
Revision 1.3 November 2009 K524G2GACB-A050 - 51 - MCP MEMORY 5. DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C) NOTE : 1) IDD5 is measured in the below test condition. 2) IDD specifications are tested after the device is properly intialized. 3) Input slew rate is 1V/ns. 4) Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ ; HIGH is defined as V IN ≥ 0.9 * VDDQ ; STABLE is defined as inputs stable at a HIGH or LOW level ; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. 5) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request. Please contact Samsung for more information. Parameter Symbol Test Condition DDR 400 DDR
333 Unit Note
(One Bank Active) IDD0 tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE 85 70 mA Precharge Standby Cur- rent in power-down mode IDD2P all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 1.0 mA IDD2PS all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 1.0 Precharge Standby Cur- rent in non power-down mode IDD2N all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE mA IDD2NS all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Active Standby Current in power-down mode IDD3P one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE mA IDD3PS one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Active Standby Current in non power-down mode (One Bank Active) IDD3N one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE mA IDD3NS one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Operating Current (Burst Mode) IDD4R one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA address inputs are SWITCHING; 50% data change each burst transfer 115 100 mA IDD4W one bank active; BL = 4; tCK = tCKmin ; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer 100 80 Refresh Current IDD5 tRC ≥ tRFC; tCK = tCKmin ; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 170 170 mA 1 Self Refresh Current IDD6 CKE is LOW; t CK = t CKmin ; Extended Mode Register set to all 0’s; address and control inputs are STABLE; data bus inputs are STABLE TCSR Range Values Typ Max Full Array 85°C 1100 1800 uA 70°C 750 45°C 450 900 15°C 300 1/2 Array 85°C 700 1500 uA 70°C 500 45°C 300 750 15°C 250 1/4 Array 85°C 500 1300 uA 70°C 350 45°C 250 650 15°C 200 Density 128Mb 256Mb 512Mb 1Gb 2Gb Unit tRFC 80 80 110 140 140 ns
Revision 1.3 November 2009 K524G2GACB-A050 - 52 - MCP MEMORY 6. AC Operating Conditions & Timming Specification NOTE : 1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2) The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Parameter/Condition Symbol Min Max Unit Note Input High (Logic 1) Voltage, all inputs VIH(AC) 0.8 x VDDQ VDDQ+0.3 V 1 Input Low (Logic 0) Voltage, all inputs VIL(AC) -0.3 0.2 x VDDQ V 1 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.4 x VDDQ 0.6 x VDDQ V 2
Revision 1.3 November 2009 K524G2GACB-A050 - 53 - MCP MEMORY 7. AC Timming Parameters & Specifications Parameter Symbol DDR400 DDR333 Unit NoteMin Max Min Max Clock cycle time CL=3 tCK 5 6 ns 1,2 Row cycle time tRC 55 60 ns Row active time tRAS 40 70,000 42 70,000 ns RAS to CAS delay tRCD 20 18 ns Row precharge time tRP 15 18 ns Row active to Row active delay tRRD 10 12 ns Write recovery time tWR 12 12 ns Last data in to Active delay tDAL - - - 3 Last data in to Read command tCDLR 2 1 tCK Col. address to Col. address delay tCCD 1 1 tCK Clock high level width tCH 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 tCK DQ Output data access time from CK/CK CL=3 tAC 2 5 2 5.5 ns 4 DQS Output data access time from CK/CK CL=3 tDQSCK 2 5 2 5.5 ns Data strobe edge to ouput data edge tDQSQ 0.4 0.5 ns Read Preamble CL=3 tRPRE 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 ns 5 DQS-in hold time tWPREH 0.25 0.25 tCK DQS-in high level width tDQSH 0.4 0.6 0.4 0.6 tCK DQS-in low level width tDQSL 0.4 0.6 0.4 0.6 tCK DQS falling edge to CK setup time tDSS 0.2 0.2 tCK DQS falling edge hold time from CK tDSH 0.2 0.2 tCK DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 tCK Address and Control Input setup time fast slew rate tIS 0.9 1.1 ns slow slew rate 1.1 1.3 8 Address and Control Input hold time fast slew rate tIH 0.9 1.1 ns 7 slow slew rate 1.1 1.3 8 Address & Control input pulse width tIPW 2.2 2.2 DQ & DM setup time to DQS fast slew rate tDS 0.48 0.6 ns 6,7 slow slew rate 0.58 0.7 6,8 DQ & DM hold time to DQS fast slew rate tDH 0.48 0.6 ns 6,7 slow slew rate 0.58 0.7 6,8 DQ & DM input pulse width tDIPW 1.2 1.2 ns DQ & DQS low-impedence time from CK/CK tLZ 1.0 1.0 ns DQ & DQS high-impedence time from CK/CK tHZ 5 5.5 ns DQS write postamble time tWPST 0.4 0.6 0.4 0.6 tCK
Revision 1.3 November 2009 K524G2GACB-A050 - 54 - MCP MEMORY NOTE : 1) tCK(max) value is measured at 100ns. 2) The only time that the clock Frequency is allowed to be changed is during clock stop, power-down, self-refresh modes. 3) In case of below 33MHz (tCK=30ns) condition, SEC could support tDAL(=2*tCK). tDAL =(tWR/tCK) + (tRP/tCK) 4) tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C). tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C). tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page). 5) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating This derating table is used to increase tDS/tDH in the case wher e the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/ 7) Input slew rate 1.0 V/ ns. 8) Input slew rate 0.5V/ns and < 1.0V/ns. 9) Maximum burst refresh cycle : 8 Parameter Symbol DDR400 DDR333 Unit NoteMin Max Min Max DQS write preamble time tWPRE 0.25 0.25 tCK Refresh interval time tREF 64 64 ms Mode register set cycle time tMRD 2 2t C K Power down exit time tPDEX 2 1t C K CKE min. pulse width(high and low pulse width) tCKE 2 2 tCK Auto refresh cycle time tRFC 120 120 ns 9 Exit self refresh to active command tXSR 120 120 ns Data hold from DQS to earliest DQ edge tQH tHPmin - tQHS tHPmin - tQHS ns Data hold skew factor tQHS 0.5 0.65 ns Clock half period tHP tCLmin or tCHmin tCLmin or tCHmin ns Data Rise/Fall Rate ∆tDS ∆tDH (ns/V) (ps) (ps) 00 0 ±0.25 +50 +50 ±0.5 +100 +100
Revision 1.3 November 2009 K524G2GACB-A050 - 56 - MCP MEMORY 9. Input/Output Capacitance(VDD=1.8, VDDQ=1.8V, TC = 25°C, f=100MHz) Parameter Symbol Min Max Unit Input capacitance (A0 ~ A13, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) CIN1 1.5 3.0 pF Input capacitance( CK, CK ) CIN2 1.5 3.5 pF Data & DQS input/output capacitance COUT 2.0 4.5 pF Input capacitance(DM) CIN3 2.0 4.5 pF
Revision 1.3 November 2009 K524G2GACB-A050 - 58 - MCP MEMORY 12. Command Truth Table (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) NOTE : 1) OP Code : Operand Code. A0 ~ A13 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2) EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3) Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4) BA0 ~ BA1 : Bank select addresses. 5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6) During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7) Burst stop command is valid at every burst length. 8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM. Command CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A13,A11, A9~A0 Note Register Mode Register Set H X L L L L OP CODE 1, 2 Refresh Auto Refresh H H LL LH X Self Refresh Entry L 3 Exit L H LH HH X HX XX 3 Bank Active & Row Addr. H X L L H H V Row Address Read & Column Address Auto Precharge Disable HX L H L H V L Column Address (A0~A9) Auto Precharge Enable H 4 Write & Column Address Auto Precharge Disable HX L H L L V L Column Address (A0~A9) Auto Precharge Enable H 4, 6 Burst Stop H X L H H L X 7 Precharge Bank Selection HX L L H L VL X All Banks X H 5 Active Power Down Entry H L HX XX XLH HH Exit L H X X X X Precharge Power Down Entry H L HX XX X LH HH Exit L H HX XX LH HH DM H X X 8 No operation (NOP) : Not defined H X HX XX X LH HH 9
Revision 1.3 November 2009 K524G2GACB-A050 - 59 - MCP MEMORY 13. Functional Truth Table Current State CS RAS CAS WE Address Command Action PRECHARGE STANDBY L H H L X Burst Stop ILLEGAL2) L H L X BA, CA, A10 READ/WRITE ILLEGAL2) L L H H BA, RA Active Bank Active, Latch RA L L H L BA, A10 PRE/PREA ILLEGAL4) LLLH X R e f r e s h AUTO-Refresh5) L L L L Op-Code, Mode-Add MRS Mode Register Set5) ACTIVE STANDBY L H H L X Burst Stop NOP L H L H BA, CA, A10 READ/READA Begin Read, Latch CA, Determine Auto-Precharge L H L L BA, CA, A10 WRITE/WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA Active Bank Active/ILLEGAL2) LLHL BA, A10 PRE/PREA Precharge/Precharge All L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ L H H L X Burst Stop Terminate Burst L H L H BA, CA, A10 READ/READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge3) L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active Bank Active/ILLEGAL2) L L H L BA, A10 PRE/PREA Terminate Burst, Precharge10) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge3) L H L L BA, CA, A10 WRITE/WRITEA Terminate Burst, Latch CA, Begin new Write, Determine Auto- Precharge3) L L H H BA, RA Active Bank Active/ILLEGAL2) L L H L BA, A10 PRE/PREA Terminate Burst With DM=High, Precharge10) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ with AUTO PRECHARGE6) (READA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA 6) L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active 6) LLHL BA, A10 PRE/PREA 6) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL
Revision 1.3 November 2009 K524G2GACB-A050 - 60 - MCP MEMORY Current State CS RAS CAS WE Address Command Action WRITE with AUTO RECHARGE7) (WRITEA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA 7) L H L L BA, CA, A10 WRITE/WRITEA 7) L L H H BA, RA Active 7) L L H L BA, A10 PRE/PREA 7) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL PRECHARGING (DURING tRP) L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL2) L L H H BA, RA Active ILLEGAL2) L L H L BA, A10 PRE/PREA NOP4)(Idle after tRP) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING (FROM ROW ACTIVE TO tRCD) L H H L X Burst Stop ILLEGAL2) L H L X BA, CA, A10 READ/WRITE ILLEGAL2) L L H H BA, RA Active ILLEGAL2) LLHL BA, A10 PRE/PREA ILLEGAL2) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE RECOVERING (DURING tWR OR tCDLR) L H H L X Burst Stop ILLEGAL2) L H L H BA, CA, A10 READ ILLEGAL2) L H L L BA, CA, A10 WRITE WRITE L L H H BA, RA Active ILLEGAL2) L L H L BA, A10 PRE/PREA ILLEGAL2) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL RE- FRESHING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MODE REGISTER SETTING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL LLHL BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL
Revision 1.3 November 2009 K524G2GACB-A050 - 61 - MCP MEMORY (H=High Level, L=Low level, X=Don′t Care) NOTE : 1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2) ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. (ILLEGAL = Device operation and/or data integrity are not guaranteed.) 3) Must satisfy bus contention, bus turn around and write recovery requirements. 4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5) ILLEGAL if any bank is not idle. 6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information. 7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information. 8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9) Power-Down, Self-Refresh can be entered only from All Bank Idle state. Current State CKE n-1 CKE n CS RAS CAS WE Add Action SELF- REFRESHING8) L H H X X X X Exit Self-Refresh LHLHHHX E x i t S e l f - R e f r e s h LHLHHLX I L L E G A L LHLHLXX I L L E G A L LHLLXXX I L L E G A L L L X X X X X NOP (Maintain Self-Refresh) POWER DOWN L H X X X X X Exit Power Down(Idle after tPDEX) L L X X X X X NOP (Maintain Power Down) ALL BANKS IDLE H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down HLLHHLX I L L E G A L H L L H L X X ILLEGAL HLLLXXX I L L E G A L L X X X X X X Refer to Current State=Power Down
Revision 1.3 November 2009 K524G2GACB-A050 - 62 - MCP MEMORY MOBILE DDR SDRAM Device Operations & Timing Diagram
Revision 1.3 November 2009 K524G2GACB-A050 - 63 - MCP MEMORY Device Operations
banks simultaneously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initi ated. the same bank can be initiated. Table 1. Bank selection for precharge by Bank address bits
- No Operation(NOP) & Device Deselect
1 X X All Banks
A to Bank B and vice versa) is the Bank to Bank delay time, tRRD(min). in reduction of product life. Figure 1. Bank Activation Command Cycle timing <tRCD=3CLK , tRRD=2CLK> time will be determined by the values programmed during the MRS cycle. the values programmed during the MRS cycle.
ing and rising edge of Data Strobe(DQS) adopted by Mobile DDR SDRAM until the burst length is completed. Figure 2. Burst read operation timing
Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. Figure 3. Burst write operation timing 2) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
- Read Interrupted by a Precharge
vals. The latency from a precharge command to invalid output is equivalent to the CAS latency. Figure 6. Read interrupted by a precharge timing Bank Activate command may be issued to the same bank.
- For the earliest possible Precharge command without interrupting a burst Read, the Precharge command may be given on the rising clock
to the same bank after tRP (Row Precharge time).
- When a Precharge command interrupts a burst Read operation, the Precharge command given on a rising clock edge terminates the burst
last data word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same bank after tRP.
- For a Read with Autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP from rising clock that
interrupting the Read burst as described in 1 above.
- For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge
Precharge command which does not interrupt the burst.
- Write Interrupted by a Write
the new address and data will be written into the device until the programmed burst length is satisfied. Figure 7. Write interrupted by a write timing
- Write Interrupted by a Precharge & DM
A burst write operation can be interrupted by a precharge of the same bank before completion of the burst. Random column access is allowed. from the burst write cycle must be masked by DM. Figure 8. Write interrupted by a precharge and DM timing tWR, is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. strobes in the precharge command.
- For the earliest possible Precharge command following a burst Write without interrupting the burst, the minimum time for wri te recovery is
- When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between
required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.
- For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP
external Precharge command without interrupting the Write burst as described in 1 above.
- In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied.
- Write Interrupted by a Read & DM
memory. Read command interrupting write can not be issued at the next clock edge of that of write command. Figure 9. Write interrupted by a Read and DM timing The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory.
- For Read commands interrupting a burst Write, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to
Read delay is 1 clock cycle is disallowed.
- For Read commands interrupting a burst Write, the DM pin must be used to mask the input data words whcich immediately preced e the
- For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the dr iving chip (i.e., the memory co ntroller) in
time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation.
- If input Write data is masked by the Read command, the DQS input is ignored by the Mobile DDR SDRAM.
- Refer to Burst write operation.
Figure 10. Burst stop timing
- The Burst Stop command may only be issued on the rising edge of the input clock, CK.
- Burst Stop is only a valid command during Read bursts.
- Burst Stop during a Write burst is undefined and shall not be used.
- Burst Stop applies to all burst lengths.
- Burst Stop is an undefined command during Read with autoprecharge and shall not be used.
- When terminating a burst Read command, the BST command must be issued L
edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
- When the burst terminates, the DQ and DQS pins are tristated.
The Burst Stop command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). The burst read ends after a delay equal to the CAS latency.
is activated(DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data.(DM to data-mask latency is zero). DM must be issued at the rising or falling edge of data strobe. Figure 11. DM masking timing
- Read With Auto Precharge
Figure 12. Read with auto precharge timing 2) The row active command of the precharge bank can be issued after tRP from this point.
- Write with Auto Precharge
should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). Figure 13. Write with auto precharge timing 2) The row active command of the precharge bank can be issued after tRP from this point. 2) DM : Refer to "27. Write Interrupted by Precharge & DM ".
power down mode, therefore the device cannot remain in power down mode longer than the refresh period(tREF) of the device. Figure 16. Power down entry and exit timing 1) Device must be in the all banks idle state prior to entering Power Down mode. 2) The minimum power down duration is specified by tCKE.
Revision 1.3 November 2009 K524G2GACB-A050 - 80 - MCP MEMORY Timing Diagram
- Power Up Sequence for Mobile DDR SDRAM
Figure 18. Power Up Sequence for Mobile DDR SDRAM 1) Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2) Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3) Issue precharge commands for all banks of the devices. 4) Issue 2 or more auto-refresh commands. 5) Issue a mode register set command to initialize the mode register. 6) Issue a extended mode register set command for the desired operating modes after normal MRS. The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the initialization sequence, it may lead to unspecified operation. All banks have to be in idle state prior to adjusting MRS and EMRS set.
Figure 19. Basic Timing (Setup, Hold and Access Time @BL=4, CL=3)
- Multi Bank Interleaving READ
Figure 20. Multi Bank Interleaving READ (@BL=4, CL=3)
- Multi Bank Interleaving WRITE
Figure 21. Multi Bank Interleaving WRITE (@BL=4)
- Read with Auto Precharge
Figure 22. Read with Auto Precharge (@BL=8) 1) The row active command of the precharge bank can be issued after tRP from this point.
- Write with Auto Precharge
Figure 23. Write with Auto Precharge (@BL=8)
- Write followed by Precharge
Figure 24. Write followed by Precharge (@BL=4)
- Write Interrupted by Precharge & DM
Figure 25. Write Interrupted by Precharge & DM (@BL=8)
- Write Interrupted by a Read
Figure 26. Write Interrupted by a Read (@BL=8, CL=3)
- Read Interrupted by Precharge
Figure 27. Read Interrupted by Precharge (@BL=8, CL=3)
- Read Interrupted by a Write & Burst Stop
Figure 28. Read Interrupted by a Write & Burst Stop (@BL=8, CL=3)
- Read Interrupted by a Read
Figure 29. Read Interrupted by a Read (@BL=8, CL=3)
Figure 30. DM Function (@BL=8) only for write
Figure 31. Mode Register Set