K522H1HACF-B050 SAMSUNG | Alldatasheet
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- 1 - K522H1HACF-B050 Rev. 1.0, Oct. 2010 SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference pur poses only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein re main the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where product failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved. MCP Specification 2Gb (128M x16) NAND Flash + 1Gb (64M x16 ) Mobile DDR SDRAM datasheet
- 2 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
Revision History
Revision No. History Draft Date Remark Editor 1.0 Initial issue. - 2Gb NAND Flash W-die_ Ver 1.0 - 1Gb Mobile DDR F-die_ Ver 1.0 Oct. 21, 2010 Final K.N.Kang
- 3 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 1. FEATURES
- VDD/VDDQ = 1.8V/1.8V
- Double-data-rate architecture; two d ata transfers per clock cycle.
- Bidirectional data strobe (DQS).
- Four banks operation.
- Differential clock inputs (CK and CK).
- MRS cycle with address key programs.
- EMRS cycle with address key programs.
- Internal Temperature Compensated Self Refresh.
- All inputs except data & DM are sampled at the positive going edge of the sy stem clock (CK).
- Data I/O transactions on both edges of data strobe, DM for masking.
- Edge aligned data output, center aligned data input.
- No DLL; CK to DQS is not synchronized.
- DM for write masking only.
- Auto refresh duty cycle.
- Clock stop capability. <Common>
- Operating T emperature : -25°C ~ 85°C
- Package : 153ball FBGA Type - 8x9x1.0mmt, 0.5mm pitch <NAND Flash>
- Voltage Supply : 1.7V ~ 1.95V
- Organization - Memory Cell Array : (256M + 8M) x 8bit for 2Gb (512M + 16M) x 8bit for 4Gb DDP - Data Register : (2K + 64) x 8bit
- Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte
- Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 40μs(Max.) - Serial Access : 42ns(Min.)
- Fast Write Cycle Time - Page Program time : 250μs(Typ.) - Block Erase Time : 2ms(Typ.)
- Command/Address/Data Multiplexed I/O Port
- Hardware Data Protection - Program/Erase Lockout During Power Transitions
- Reliable CMOS Floating-Gate Technology -Endurance : 100K Program/Erase Cycles with 1bit/512Byte ECC for x8,
- Command Driven Operation
- Unique ID for Copyright Protection <Mobile DDR SDRAM> - CAS Latency (2, 3) Burst Length (2, 4, 8, 16) - Burst Type (Sequential & Interleave) - Partial Array Self Refresh (Full, 1/2, 1/4 Array) Output Driver Strength Control (Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8) - 7.8us for -25 to 85 °C NOTE : 1) CAS Latency - DM is internally loaded to match DQ and DQS identically. Operating Frequency DDR400 Speed @CL31) 200MHz Address configuration Organization Bank Row Column 64Mx16 BA0,BA1 A0 - A13 A0 - A9
- 4 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 2. GENERAL DESCRIPTION The K522H1HACF is a Multi Chip Package Memory which combines 2G bit NAND Flash and 1G bit Mobile DDR synchronous Dynamic RAM. NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250μs on the (2K+64)Byte page and an erase operation can be performed in typical 2m s on a (128K+4K)Byte block. Data in the data register can be read out at 42ns cycle time per Byte. The I/O pins serve as the ports for addr ess and data input/output as well as command input. The on-chip wr ite controller automates all program and erase functions including pulse repetition, where required, and in ternal verification and margining of data. Ev en the write-intensive sys- tems can take advantage of the device′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time map- ping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file stora ge and other portable applications requiring non-volatility. In 1Gbit Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, programma- ble burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system appli- cations. The K522H1HACF is suitable for use in data memory of mobile comm unication system to reduce not only mount area but also power c onsumption. This device is available in 153-ball FBGA Type.
- 5 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 3. PIN CONFIGURATION
153 FBGA: Top View (Ball Down)
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DNU DNU NC VSSn VCCn VSSQd VDDQd VDDQd VSSQd VSSd VDDd VSSQd DNU DNU B DNU VSSn /REn CLEn /WPn /WEn NC NC NC DQ12d NC NC VDDQd DNU C VSSd NC /WEd ALEn /CEn R/Bn DQ14d DQ8d DQ13d NC NC DQ9d UDMd VDDQd EN C /RASd A2d - VCCn NC NC NC NC NC - NC DQ15d UDQSd F /CASd A12d A0d - NC ---- NC - DQ11d DQ10d VSSQd G CKEd A9d BA1d - VSSn ---- NC - VDDd VDDQd CKd H VDDd A11d A7d - IO8n ---- IO15n - VSSd VDDQd /CKd J A4d VSSd A5d - IO9n ---- IO14n - LDQSd NC VSSQd K A6d A10d A3d - IO10n IO11n VCCn VSSn IO12n IO13n - DQ2d LDMd DQ4d M VSSd VDDd NC IO5n IO2n IO0n DQ6d DQ3d NC NC NC NC DQ0d VDDQd N DNU VCCn NC IO6n IO3n VSSQd NC DQ1d NC NC NC NC VDDQd DNU P DNU DNU VSSn IO7n IO4n IO1n VDDQd VDDQd VSSQd VSSd VDDd VSSQd DNU DNU NAND Flash Mobile DRAM Power Ground NC/DNU
- 6 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 4. PIN DESCRIPTION Pin Name Pin Function(NAND Flash) Pin Name Pin Function(Mobile DDR) IO0n ~ IO15n Data Input/Output CKd, /CKd System Clock & Differential Clock R/Bn Ready/Busy Output CKEd Clock Enable /REn Read Enable /CSd Chip Select /WEn Write Enable /RASd Row Address Strobe ALEn Address Latch Enable /CASd Column Address Strobe /WPn Write Protection /WEd Write Enable /CEn Chip Enable A0d ~ A13d Address Input CLEn Command Latch Enable BA0d ~ BA1d Bank Select Address VCCn Power Supply LDMd,UDMd Lower / Upper Input Data Mask VSSn Ground LDQSd , UDQSd Lower / Upper Data Strobe DQ0d ~ DQ15d Data Input/Output VDDd Power Supply Pin Name Pin Function VDDQd Data Out Power DNU Do Not Use VSSd Ground NC No Connected VSSQd DQ Ground
- 7 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 5. ORDERING INFORMATION K 5 2 2H 1H A C F - B 0 50 Samsung MCP Memory(2chips) Device Type NAND + Mobile DDR SDRAM NAND Density,Organization 2H: 2G, x16 Flash Block Architecture C : Uniform Block Version F : 7th Generation Mobile DDR Speed 50 : 400Mbps@CL3 Operating Voltage A: 1.8V / 1.8V Package B : FBGA(HF, OSP LF) Mobile DDR Density, Organization 1H: 1G, x16 NAND Speed 0: None
- 8 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 6. FUNCTIONAL BLOCK DIAGRAM /WPn CLEn /WEn /REn R/Bn /CEn IO0n to IO15n /CSd /CASd /RASd CKEd /WEd CKd, /CKd A0d ~ A13d LDMd, UDMd BA0d ~ BA1d LDQSd, UDQSd ALEn 2Gb NAND Flash Memory DQ0d to DQ15d 1Gb Mobile DDR SDRAM VDDd VDDQd VCCn VSSn VSSd VSSQd
- 9 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 7. PACKAGE DIMENSION 153-Ball Fine pitch Ball Grid Array Package (measured in millimeters) Units:millimeters 0.22±0.05 TOP VIEW 153-∅0.30±0.05
0.20 M A B ∅
(Datum A) 142765 38 #A1 INDEX MARK 8.00±0.10 9.00±0.10 910 0.50 x 13 = 6.50 0.50 x 13 = 6.50 A B C E G D F H J L K M N 3.25 BOTTOM VIEW P 14 13 12 11 3.25 0.50 (Datum B)
0.08 MAX
0.90±0.10 8.00±0.10 9.00±0.10 #A1 0.25 0.50 0.25 A B
- 10 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 2Gb (128M x16) NAND Flash W-die
Figure 2. Array Organization
64 Bytes
1 Block = 64 Pages
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)Byte x 64 Pages
1 Device = (2K+64)B x 64Pages x 2,048 Blocks
1 Device = (2K+64)B x 64Pages x 4,096 Blocks
Figure 1. Functional Block Diagram Column Address : Starting Address of the Register.
- The device ignores any additional input of address cycles than required.
- A29 is Row address for 4G DDP.
Figure 4. Figure 2-2. Array Organization
32 Words
1 Page = (1K + 32)Word
1 Block = (1K + 32)Word x 64 Pages
1 Device = (1K + 32)Word x 64Pages x 2,048 Blocks
1 Device = (1K + 32)Word x 64Pages x 4,096 Blocks
Figure 3. unctional Block Diagram Column Address : Starting Address of the Register.
- The device ignores any additional input of address cycles than required.
- A28 is Row address for 4G DDP.
- 13 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
1.0 Product Introduction
NAND Flash Memory has addresses multiplexed into 8 I/Os(x16 device case : lower 8 I/Os). This scheme dramatically reduces pin counts and allows sys- tem upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to mul- tiplex command and address respectively, via t he I/O pins. Some commands require one bus cycle. For example, Reset Command, Sta tus Read Com- mand, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. Page R ead and Page Program need the same five addres s cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific comman ds into the command register. Table 3 defines the specific commands of the device. In addition to the enhanced architecture and interface, the devic e incorporates copy-back program feature from one page to anot her page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system per- formance for solid-state disk application is significantly increased. [Table 3] Command Sets NOTE : 1) Random Data Input/Output can be executed in a page. Caution : Any undefined command inputs are prohibited except for above command set of Table 3. Function 1st Cycle 2nd Cycle Acceptable Command during Busy Read 00h 30h Read ID 90h - Read for Copy Back 00h 35h Reset FFh - O Page Program 80h 10h Copy-Back Program 85h 10h Block Erase 60h D0h Random Data Input 1) 85h - Random Data Output 1) 05h E0h Read Status 70h - O
- 14 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
1.1 ABSOLUTE MAXIMUM RATINGS
NOTE : 1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1.2 RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA=-25 to 85°C)
1.3 DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions otherwise noted.) NOTE : 1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2) Typical value is measured at Vcc=1.8V, TA=25°C. Not 100% tested. Parameter Symbol Rating Unit Voltage on any pin relative to VSS VCC -0.6 to + 2.45 VVIN -0.6 to + 2.45 VI/O -0.6 to Vcc + 0.3 (< 2.45V) Temperature Under Bias TBIAS -30 to +125 °C Storage Temperature TSTG -65 to +150 °C Short Circuit Current IOS 5m A Parameter Symbol Min Typ. Max Unit Supply Voltage VCC 1.7 1.8 1.95 V Supply Voltage VSS 000V Parameter Symbol Test Conditions Min Typ Max Unit Operating Current Page Read with Serial Access ICC1 tRC=42ns CE=VIL, IOUT=0mA - 15 25 mA Program ICC2 -- Erase ICC3 -- Stand-by Current(TTL) ISB1 2Gb,CE=VIH, WP=0V/VCC -- 1 4Gb DDP,CE=VIH, WP=0V/VCC -- 2 Stand-by Current(CMOS) ISB2 2Gb,CE=VCC-0.2, WP=0V/VCC -1 0 5 0 μA 4Gb DDP,CE=VCC-0.2, WP=0V/VCC - 20 100 Input Leakage Current ILI VIN=0 to Vcc(max) - - ±10 Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±10 Input High Voltage VIH 1) - 0.8xVCC - VCC+0.3 V Input Low Voltage, All inputs VIL Output High Voltage Level VOH IOH=-100μAV CC-0.1 -- Output Low Voltage Level VOL IOL=100uA -- 0 . 1 Output Low Current(R/B) IOL(R/B)V OL=0.1V 34- m A
- 15 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
1.4 VALID BLOCK
NOTE : 1) The device may include initial invalid blocks when first ship ped. Additional invalid blocks may develop while being used. Th e number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as bl ocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with x8 : 1bit/ 512Byte, x16 : 1bit/256Word ECC. 3) Each mono chip in th device has maximum 40 invalid blocks.
1.5 AC TEST CONDITION
(TA=-25 to 85°C, Vcc=1.7V~1.95V unless otherwise noted) 1.6 CAPACITANCE(TA=25°C, VCC=1.8V, f=1.0MHz) NOTE : Capacitance is periodically sampled and not 100% tested.
1.7 MODE SELECTION
NOTE : 1) X can be VIL or VIH. 2) WP should be biased to CMOS high or CMOS low for standby. Parameter Symbol Min Typ. Max Unit 2Gb NVB 2,008 - 2,048 Blocks 4Gb DDP NVB 4,016 - 4,096 Blocks Parameter Value Input Pulse Levels 0V to VCC Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2 Output Load 1 TTL GATE and CL=30pF Item Symbol Test Condition Min Max Unit Input/Output Capacitance (Mono) CI/O VIL=0V -1 0 p F Input Capacitance (Mono) CIN VIN=0V -1 0 p F Input/Output Capacitance (DDP) CI/O VIL=0V -2 0 p F Input Capacitance (DDP) CIN VIN=0V -2 0 p F CLE ALE CE WE RE WP Mode HLL HX Read Mode Command Input L H L H X Address Input(5clock) HLL HH Write Mode Command Input L H L H H Address Input(5clock) L L L H H Data Input LLLH X D a t a O u t p u t X X X X H X During Read(Busy) X X X X X H During Program(Busy) X X X X X H During Erase(Busy) X X (1) X X X L Write Protect XXHXX 0V/VCC 2) Stand-by
- 16 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
1.8 Read / Program / Erase Characteristics
NOTE : 1) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V Vcc and 25°C temperature.
1.9 AC Timing Characteristics for Command / Address / Data Input
NOTE : 1) The transition of the corresponding control pins must occur only once while WE is held low 2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle Parameter Symbol Min Typ Max Unit Read Time (Data Transfer from Cell to Register) t R -- 4 0 μs Program Time t PROG - 250 750 μs Number of Partial Program Cycles in the Same Page Nop - - 4 cycles Block Erase Time t BERS -2 1 0 m s Parameter Symbol Min Max Unit CLE Setup Time tCLS 1) 21 - ns CLE Hold Time tCLH 5- n s CE Setup Time tCS 1) 21 - ns CE Hold Time tCH 5- n s WE Pulse Width tWP 21 - ns ALE Setup Time tALS 1) 21 - ns ALE Hold Time tALH 5- n s Data Setup Time tDS 1) 20 - ns Data Hold Time tDH 5- n s Write Cycle Time tWC 40 - ns WE High Hold Time tWH 10 - ns Address to Data Loading Time tADL 2) 100 - ns
- 17 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
1.10 AC Characteristics for Operation
NOTE : 1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5 μs. Parameter Symbol Min Max Unit ALE to RE Delay tAR 10 - ns CLE to RE Delay tCLR 10 - ns Ready to RE Low tRR 20 - ns RE Pulse Width tRP 21 - ns WE High to Busy tWB - 100 ns WP Low to WE Low (disable mode) tWW 100 - ns WP High to WE Low (enable mode) Read Cycle Time tRC 42 - ns RE Access Time tREA -3 0 n s CE Access Time tCEA -3 5 n s RE High to Output Hi-Z tRHZ - 100 ns CE High to Output Hi-Z t CHZ -3 0 n s CE High to ALE or CLE Don’t Care tCSD 0- n s RE High to Output Hold tROH 15 - ns CE High to Output Hold t COH 15 - ns RE High Hold Time tREH 10 - ns Output Hi-Z to RE Low tIR 0- n s RE High to WE Low tRHW 100 - ns WE High to RE Low tWHR 60 - ns Device Resetting Time(Read/Program/Erase) tRST - 5/10/500(1) μs
2.0 NAND Flash Technical Notes
2.1 Initial Invalid Block(s)
Figure 5. Flow chart to create initial invalid block table 512Byte, x16:1bit/256Word ECC.
2.2 Identifying Initial Invalid Block(s)
block information is prohibited.
- 19 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 NAND Flash Technical Notes (Continued)
2.3 Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. Block replacement should be done upon erase or program error. ECC : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection NOTE : A repetitive page read operation on the same block without erase may cause bit errors, which could be accumulated over time and exceed the coverage of ECC. Soft- ware scheme such as caching into RAM is recommended. Program Flow Chart Failure Mode Detection and Countermeasure sequence Write Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement Read Up to 1 Bit-Failure Verity ECC -> ECC Correction Start I/O 6 = 1 ? I/O 0 = 0 ? No* Write 80h Write Address Write Data Write 10h Read Status Register Program Completed or R/B = 1 ? Program Error Yes No Yes : If program operation results in an error, map out the block including the page in error and copy the target data to another block.
- 20 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 NAND Flash Technical Notes (Continued) Block Replacement * Step1 When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’) * Step3 Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’. * Step4 Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme. Erase Flow Chart Read Flow Chart Start I/O 6 = 1 ? I/O 0 = 0 ? No* Write 60h Write Block Address Write D0h Read Status Register or R/B = 1 ? Erase Error Yes No : If erase operation results in an error, map out the failing block and replace it with another block. * Erase Completed Yes Start Verify ECC No Write 00h Write Address Read Data ECC Generation Reclaim the Error Page Read Completed Yes Write 30h Buffer memory of the controller. 1st Block A Block B (n-1)th nth (page) 1st (n-1)th nth (page) an error occurs.
- 21 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 NAND Flash Technical Notes (Continued)
2.4 Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0. From the LSB page to MSB page DATA IN: Data (1) Data (64) (1) (2) (3) (32) (64) Data register Page 0 Page 1 Page 2 Page 31 Page 63 Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) (2) (32) (3) (1) (64) Data register Page 0 Page 1 Page 2 Page 31 Page 63
- 23 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 NOTE : Device I/O DATA ADDRESS I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 2Gb(x8) I/O 0 ~ I/O 7 ~2,112byte A0~A7 A8~A11 A12~A19 A20~A27 A28 4Gb DDP(x8) I/O 0 ~ I/O 7 ~4,224byte A0~A7 A8~A11 A12~A19 A20~A27 A28~A29 2Gb(x16) I/O 0 ~ I/O 15 ~1,056Word A0~A7 A8~A10 A11~A18 A19~A26 A27 4Gb DDP(x16) I/O 0 ~ I/O 15 ~2,112Word A0~A7 A8~A10 A11~A18 A19~A26 A27~A28
- 24 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
3.0 TIMING DIAGRAMS
3.1 Command Latch Cycle
3.2 Address Latch Cycle
Col. Add1 tCS tWC tWP tALS tDS tDH tALH tALS tWH tWC tWP tDS tDH tALH tALS tWH tWC tWP tDH tALH tALS tWH tDS tDH tWP I/Ox Col. Add2 Row Add1 Row Add2 tWC tWH tALH tALS tDS tDH Row Add3 tALH tCLS tDS
- 25 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
3.3 Input Data Latch Cycle
≈≈≈ 3.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L) RE CE R/B Dout Dout Dout tRC tREA tRR tROH tREA tREH tREA tCOH tRHZ ≈≈≈≈ I/Ox tCHZ tRHZ tRP NOTE : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
- 26 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 3.5 CE WE CLE RE 70h Status Output tCLR tCLH tWP tCH tDS tDH tREA tIR tRHOH tCOHtWHR tCEA tCLS I/Ox tCHZ tRHZ tCS Status Read Cycle
3.6 Read Operation
00h Col. Add1 Col. Add2 Row Add1 Dout N Dout N+1 Column Address Row Address tWB tAR tR tRC tRHZ tRR Dout M tWC Row Add2 30h tCLR I/Ox Row Add3
- 27 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
3.7 Read Operation(Intercepted by CE)
00h Dout N Dout N+1 Dout N+2 Row AddressColumn Address tWB tAR tCHZ tR tRR tRC 30hI/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 tCOH tCLR tCSD
- 28 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
3.8 Random Data Output In a Page
B tAR tR tRR 30h 05h Column Address Dout M Dout M+1I/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Col Add1 Col Add2Row Add3 tCLR E0h tWHR tREAtRC tRHW
- 29 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
3.9 Page Program Operation
N Din 10hM SerialData Input Command Column Address Row Address 1 up to m Byte Serial Input Program Command Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program tPROGtWB tWC tWC tWC I/Ox Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3 tADL tWHR NOTE : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
- 30 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
3.10 Page Program Operation with Random Data Input
N Din 10hM Serial Data Input Command Column Address Row Address Serial Input Program Command Read Status Command tPROGtWB tWC tWC ≈ ≈ 85h Random Data Input CommandColumn Address tWC Din J Din K Serial Input ≈ ≈I/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Col. Add1 Col. Add2Row Add3 tADL tADL tWHR NOTE : 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
- 31 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
3.11 Copy-Back Program Operation with Random Data Input
Column Address Row Address Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program tPROG tWB tWC Busy tWB tR Busy 10h Copy-Back Data Input Command 35h Column Address Row Address Data 1 Data N ≈≈Col Add1 Col Add2 Row Add1 Row Add2 Col Add1 Col Add2 Row Add1 Row Add2 Row Add3Row Add3 70h tADL tWHR Data 1 Data N tRC CE CLE R/B WE ALE RE I/Ox NOTE : 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
- 32 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
3.12 Block Erase Operation
I/O0=1 Error in Erase D0h 70h I/O 0 Busy tWB tBERS I/O0=0 Successful Erase Row Address tWC ≈Auto Block Erase Setup Command I/Ox Row Add1 Row Add2 Row Add3 tWHR
- 33 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
3.13 Read ID Operation
Read ID Command Maker Code Device Code 00h ECh tREA Address 1cycle I/Ox tAR Device 4th cyc.Code 3rd cyc. 5th cyc. 3.13.1. ID Definition Table
90 ID : Access command = 90H
Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle 2Gb(x8) AAh 00h 15h 44h 4Gb DDP(x8) ACh 01h 15h 48h 2Gb(x16) BAh 00h 55h 44h 4Gb DDP(x16) BCh 01h 55h 48h
Description
Page Size, Block Size,Redundant Area Size, Organization Plane Number, Plane Size, ECC Level
- 34 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 3rd ID Data 4th ID Data ITEM Description I/O # 7 6 5 4 3 2 1 0 Internal Chip Number Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
Cache Program Not supported supported ITEM Description I/O # 7 6 5 4 3 2 1 0 Page Size (without Redundant Area) 1KB 2KB 4KB 8KB Block Size (without Redundant Area) 64KB 128KB 256KB 512KB Redundant Area Size (Byte/512byte) Reserved Reserved Organization X8 X16 Reserved 0 or 1
- 35 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 5th ID Data ITEM Description I/O # 7 6 5 4 3 2 1 0 ECC level 1bit ECC/512Byte 2bit ECC/512Byte 4bit ECC/512Byte Reserved Plane Number Plane Size (without Redundant Area) 64KB 128KB 256KB 512KB 1Gb 2Gb 4Gb 8Gb Reseved Reserved 0
4.0 Device Operation
Figure 8. Read Operation
4.1 PAGE READ
itive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. multiple times regardless of how many times it is done in a page.
Figure 10. Random Data Input In a Page Figure 9. Program & Read Status Operation
4.2 PAGE PROGRAM
atile programming period where the loaded data is programmed into the appropriate cell. may be operated multiple times regardless of how many times it is done in a page. remains in Read Status command mode until another valid command is written to the command register.
Figure 12. Page Copy-Back Program Operation with Random Data Input Figure 11. Page Copy-Back Program Operation
4.3 COPY-BACK PROGRAM
another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 12. 1) Copy-Back Program operation is allowed only within the same memory plane. There is no limitation for the number of repetition.
Figure 13. Block Erase Operation
4.4 BLOCK ERASE
completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
4.5 READ STATUS
during a random read cycle, the read command(00h) should be given before starting read cycles. 1) I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
4.6 Read ID
mode until further commands are issued to it. Figure 14 shows the operation sequence.
Figure 14. Read ID Operation Device 4th Cyc.CodeECh 3rd Cyc. 5th Cyc. Figure 15. RESET Operation
4.7 RESET
programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Reset command is written. Refer to Figure 15 below.
Figure 16. Rp vs tr ,tf & Rp vs ibusy
4.8 READY/BUSY
lowing reference chart(Fig.17). Its value can be determined by the following guidance. where IL is the sum of the input currents of all devices tied to the R/B pin.
Figure 17. AC Waveforms for Power Transition
5.0 DATA PROTECTION & POWER UP SEQUENCE
sequence for program/erase provides additional software protection.
Figure 19. Erase Operation Figure 18. Program Operation
5.1 WP AC TIMING GUIDE
Enabling WP during erase and program busy is prohibited.
- 4 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 1Gb (64M x16 ) Mobile DDR SDRAM
- 5 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
1.0 FUNCTIONAL BLOCK DIAGRAM
Timing Register DM Input Register Address Register Refresh Counter Row Buffer Row DecoderCol. Buffer Data Input Register Serial to parallel 6Mx32 6Mx32 6Mx32 6Mx32 Sense AMP 2-bit prefetch Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Strobe Gen. CK, CK ADD LCKE CK, CK CKE CS RAS CAS WE LCAS LRAS LCBR LWE LWCBR LRAS LCBR CK, CK 32 16 LDM X16 DQi Data Strobe DM LDM LWE
Figure 1. State diagram
2.0 FUNCTIONAL DESCRIPTION
3.0 MODE REGISTER DEFINITION
Figure 2. Mode Register Set
3.1 Mode Register Set (MRS)
1) RFU (Reserved for future use) should stay "0" during MRS cycle.
0 Sequential
1 Interleave
0 BT Burst Length 0 R FU1) 0 0 0 CAS Latency
- 8 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 [Table 1] Burst address ordering for burst length Burst Length Starting Address (A3, A2, A1, A0) Sequential Mode Interleave Mode xxx0 0, 1 0, 1 xxx1 1, 0 1, 0 xx00 0, 1, 2, 3 0, 1, 2, 3 xx01 1, 2, 3, 0 1, 0, 3, 2 xx10 2, 3, 0, 1 2, 3, 0, 1 xx11 3, 0, 1, 2 3, 2, 1, 0
Figure 3. Extended Mode Register Set
3.2 Extended Mode Register Set (EMRS)
low for proper EMRS operation. Refer to the table for specific codes. 1) RFU (Reserved for future use) should stay "0" during EMRS cycle.
000 F u l l
3.3 Internal Temperature Compensated Self Refresh (TCSR)
Figure 4. EMRS code and TCSR, PASR
- In order to save power consumption, this Mobile DRAM includes th e internal temperature sensor and control units to control the self refresh cycle auto-
matically according to the real device temperature.
- TCSR ranges for IDD6 shown in the table are only examples.
- If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
1) IDD6 85°C is guaranteed, IDD6 45°C is typical value.
3.4 Partial Array Self Refresh (PASR)
- In order to save power consumption, Mobile DDR SDRAM includes PASR option.
- Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array.
- 11 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
4.0 ABSOLUTE MAXIMUM RATINGS
NOTE : 1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. 2) Functional operation should be restricted to recommend operation condition. 3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
5.0 DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS=0V, TC = -25°C to 85°C) NOTE : 1) Under all conditions, VDDQ must be less than or equal to VDD. 2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 3) Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT - 0.5 ~ 2.7 V Voltage on VDD supply relative to VSS VDD - 0.5 ~ 2.7 V Voltage on VDDQ supply relative to VSS VDDQ - 0.5 ~ 2.7 V Storage temperature TSTG - 55 ~ + 150 °C Power dissipation PD 1.0 W Short circuit current IOS 50 mA Parameter Symbol Min Max Unit Note Supply voltage (for device with a nominal VDD of 1.8V) VDD 1.7 1.95 V 1 I/O Supply voltage VDDQ 1.7 1.95 V 1 Input logic high voltage Address VIH(DC) 0.8 x VDDQ VDDQ + 0.3 V Data 0.7 x VDDQ VDDQ + 0.3 V Input logic low voltage Address VIL(DC) -0.3 0.2 x VDDQ V Data -0.3 0.3 x VDDQ V Output logic high voltage VOH(DC) 0.9 x VDDQ - V IOH = - 0.1mA Output logic low voltage VOL(DC) - 0.1 x VDDQ V IOL = 0.1mA Input leakage current II -2 2 uA 3 Output leakage current IOZ -5 5 uA
- 12 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
6.0 DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TC = -25 to 85°C) NOTE : 1) IDD5 is measured in the below test condition. 2) IDD specifications are tested after the device is properly initialized. 3) Input slew rate is 1V/ns. 4) Definitions for IDD: LOW is defined as VIN ≤ 0.1 * VDDQ; HIGH is defined as VIN ≥ 0.9 * VDDQ; STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once p er two clock cycles; - data bus inputs: DQ changing between HIGH an d LOW once per clock cycle; DM and DQS are STABLE. 5) IDD6 85°C is guaranteed, IDD6 45°C is typical value. Parameter Symbol Test Condition DDR400 Unit Note Operating Current (One Bank Active) IDD0 tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE 60 mA Precharge Standby Current in power-down mode IDD2P all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 0.5 mA IDD2PS all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 0.5 Precharge Standby Current in non power-down mode IDD2N all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 8 mA IDD2NS all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 4 Active Standby Current in power-down mode IDD3P one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 5 mA IDD3PS one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 4 Active Standby Current in non power-down mode (One Bank Active) IDD3N one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 12 mA IDD3NS one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 10 Operating Current (Burst Mode) IDD4R one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA address inputs are SWITCHING; 50% data change each burst transfer 70 mA IDD4W one bank active; BL = 4; tCK = tCKmin; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer 50 Refresh Current IDD5 tRC ≥ tRFC; tCK = tCKmin; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 70 mA 1 Self Refresh Current IDD6 CKE is LOW; t CK = t CKmin; Extended Mode Register set to all 0’s; address and control inputs are STABLE; data bus inputs are STABLE TCSR Range Values Full Array 85°C 900 uA 45°C 200 1/2 Array 85°C 800 uA 45°C 150 1/4 Array 85°C 700 uA 45°C 120 Density 128Mb 256Mb 512Mb 1Gb 2Gb Unit tRFC 80 80 110 140 140 ns
- 13 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
7.0 AC OPERATING CONDITIONS & TIMMING SPECIFICATION
NOTE : 1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2) The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Parameter/Condition Symbol Min Max Unit Note Input High (Logic 1) Voltage, all inputs VIH (AC) 0.8 x VDDQ VDDQ + 0.3 V 1 Input Low (Logic 0) Voltage, all inputs VIL (AC) -0.3 0.2 x VDDQ V 1 Input Crossing Point Voltage, CK and CK inputs VIX (AC) 0.4 x VDDQ 0.6 x VDDQ V 2
- 14 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
8.0 AC TIMMING PARAMETERS & SPECIFICATIONS
Clock cycle time CL=3 tCK 5 ns 1,2 Row cycle time tRC 55 ns Row active time tRAS 40 70,000 ns RAS to CAS delay tRCD 15 ns Row precharge time tRP 15 ns Row active to Row active delay tRRD 10 ns Write recovery time tWR 12 ns Last data in to Active delay tDAL - - 3 Last data in to Read command tCDLR 2 tCK Col. address to Col. address delay tCCD 1 tCK Clock high level width tCH 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 tCK DQ Output data access time from CK / CK CL=3 tAC 2 5 ns 4 DQS Output data access time CL=3 tDQSCK 2 5 ns Data strobe edge to output data edge tDQSQ 0.4 ns Read Preamble CL=3 tRPRE 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 tCK DQS-in setup time tWPRES 0 ns 5 DQS-in hold time tWPREH 0.25 tCK DQS-in high level width tDQSH 0.4 0.6 tCK DQS-in low level width tDQSL 0.4 0.6 tCK DQS falling edge to CK setup time tDSS 0.2 tCK DQS falling edge hold time from CK tDSH 0.2 tCK DQS-in cycle time tDSC 0.9 1.1 tCK Address and Control Input setup time fast slew rate tIS 0.9 ns slow slew rate 1.1 8 Address and Control Input hold time fast slew rate tIH 0.9 ns 7 slow slew rate 1.1 8 Address & Control input pulse width tIPW 2.2 DQ & DM setup time to DQS fast slew rate tDS 0.48 ns 6,7 slow slew rate 0.58 6,8 DQ & DM hold time to DQS fast slew rate tDH 0.48 ns 6,7 slow slew rate 0.58 6,8 DQ & DM input pulse width tDIPW 1.2 ns DQ & DQS low-impedence time from CK / CK tLZ 1.0 ns DQ & DQS high-impedence time from CK / CK tHZ 5 ns DQS write postamble time tWPST 0.4 0.6 tCK
- 15 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 NOTE : 1) tCK(max) value is measured at 100ns. 2) The only time that the clock Frequency is allowed to be changed is during clock stop, power-down, self-refresh modes. 3) In case of below 33MHz (tCK=30ns) condition, SEC could support tDAL (=2*tCK). tDAL =(tWR/tCK) + (tRP/tCK) 4) tAC (min) value is measured at the high VDD (1.95V) and cold temperature (-25°C). tAC (max) value is measured at the low VDD (1.7V) and hot temperature (85°C). tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page). 5) The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depend ing on tDQSS. 6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating This derating table is used to increase t DS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V. 7) Input slew rate 1.0 V/ ns. 8) Input slew rate 0.5V/ns and < 1.0V/ns. 9) Maximum burst refresh cycle : 8 Parameter Symbol DDR400 Unit Note Min Max DQS write preamble time tWPRE 0.25 tCK Refresh interval time tREF 64 ms Mode register set cycle time tMRD 2 tCK Power down exit time tPDEX 2 tCK CKE min. pulse width (high and low pulse width) tCKE 2t C K Auto refresh cycle time tRFC 80 ns 9 Exit self refresh to active command tXSR 120 ns Data hold from DQS to earliest DQ edge tQH tHPmin - tQHS ns Data hold skew factor tQHS 0.5 ns Clock half period tHP tCLmin or tCHmin ns Data Rise/Fall Rate ΔtDS ΔtDH (ns/V) (ps) (ps) 00 0 ±0.25 +50 +50 ±0.5 +100 +100
- 17 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 10.0 INPUT/OUTPUT CAPACITANCE (VDD=1.8, VDDQ=1.8V, TC = 25°C, f=100MHz) Parameter Symbol Min Max Unit Input capacitance (A0 ~ A13, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) CIN1 1.5 3.0 pF Input capacitance (CK, CK) CIN2 1.5 3.5 pF Data & DQS input/output capacitance COUT 2.0 4.5 pF Input capacitance (DM) CIN3 2.0 4.5 pF
Figure 7. AC Overshoot and Undershoot Definition for Address and Control Pins Figure 8. AC Overshoot and Undershoot Definition for CLK, DQ, DQS and DM Pins
11.0 AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR ADDRESS & CONTROL PINS
12.0 AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR CLK, DQ, DQS AND DM PINS
- 19 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
13.0 COMMAND TRUTH TABLE
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) NOTE : 1) OP Code : Operand Code. A0 ~ A13 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2) EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3) Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4) BA0 ~ BA1 : Bank select addresses. 5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6) During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 7) Burst stop command is valid at every burst length. 8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM. Command CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A13~11, A9~A0 Note Register Mode Register Set H X L L L L OP CODE 1, 2 Refresh Auto Refresh H H LL LH X Self Refresh Entry L 3 Exit L H LH HH X HX X X 3 Bank Active & Row Addr. H X L L H H V Row Address Read & Column Address Auto Precharge Disable HX L H L H V L Column Address (A0~A9) Auto Precharge Enable H4 Write & Column Address Auto Precharge Disable HX L H L L V L Column Address (A0~A9) Auto Precharge Enable H4 , 6 Deep Power Down Entry H L L H H L X Exit L H H X X X Burst Stop H X L H H L X 7 Precharge Bank Selection HX L L H L VL X All Banks X H 5 Active Power Down Entry H L HX X X XLH HH Exit L H X X X X Precharge Power Down Entry H L HX X X X LH HH Exit L H HX X X LH HH DM H X X 8 No operation (NOP) : Not defined H X HX X X X LH HH 9
- 20 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0
14.0 FUNCTIONAL TRUTH TABLE
Current State CS RAS CAS WE Address Command Action PRECHARGE STANDBY L H H L X Burst Stop ILLEGAL 2) L H L X BA, CA, A10 READ/WRITE ILLEGAL 2) L L H H BA, RA Active Bank Active, Latch RA L L H L BA, A10 PRE/PREA ILLEGAL 4) LLLH X R e f r e s h AUTO-Refresh 5) LLLLO p - C o d e , M ode-Add MRS Mode Register Set 5) ACTIVE STANDBY L H H L X Burst Stop NOP L H L H BA, CA, A10 READ/READA Begin Read, Latch CA, Determine Auto-Precharge L H L L BA, CA, A10 WRITE/WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA Active Bank Active/ILLEGAL 2) LLHL BA, A10 PRE/PREA Precharge/Precharge All L L L H X Refresh ILLEGAL LLLLO p - C o d e , M ode-Add MRS ILLEGAL READ L H H L X Burst Stop Terminate Burst L H L H BA, CA, A10 READ/READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge3) L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active Bank Active/ILLEGAL 2) L L H L BA, A10 PRE/PREA Terminate Burst, Precharge 10) L L L H X Refresh ILLEGAL LLLLO p - C o d e , M ode-Add MRS ILLEGAL WRITE L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Pre- charge 3) L H L L BA, CA, A10 WRITE/WRITEA Terminate Burst, Latch CA, Begin new Write, Determine Auto-Pre- charge 3) L L H H BA, RA Active Bank Active/ILLEGAL 2) L L H L BA, A10 PRE/PREA Terminate Burst With DM=High, Precharge 10) L L L H X Refresh ILLEGAL LLLLO p - C o d e , M ode-Add MRS ILLEGAL READ with AUTO PRECHARGE 6) (READA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA NOTE6 L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active NOTE6 LLHL BA, A10 PRE/PREA NOTE6 L L L H X Refresh ILLEGAL LLLLO p - C o d e , M ode-Add MRS ILLEGAL
- 21 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 Current State CS RAS CAS WE Address Command Action WRITE with AUTO RECHARGE7) (WRITEA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA NOTE7 L H L L BA, CA, A10 WRITE/WRITEA NOTE7 L L H H BA, RA Active NOTE7 L L H L BA, A10 PRE/PREA NOTE7 L L L H X Refresh ILLEGAL LLLL O p - C ode, Mode-Add MRS ILLEGAL PRECHARGING (DURING t RP) LHHL X B u r s t S t o p ILLEGAL 2) L H L X BA, CA, A10 READ/WRITE ILLEGAL 2) L L H H BA, RA Active ILLEGAL 2) L L H L BA, A10 PRE/PREA NOP 4)(Idle after tRP) L L L H X Refresh ILLEGAL LLLL O p - C ode, Mode-Add MRS ILLEGAL ROW ACTIVATING (FROM ROW ACTIVE TO tRCD) LHHL X B u r s t S t o p ILLEGAL 2) L H L X BA, CA, A10 READ/WRITE ILLEGAL 2) L L H H BA, RA Active ILLEGAL 2) L L H L BA, A10 PRE/PREA ILLEGAL 2) L L L H X Refresh ILLEGAL LLLL O p - C ode, Mode-Add MRS ILLEGAL WRITE RECOVERING (DURING tWR OR tCDLR) LHHL X B u r s t S t o p ILLEGAL 2) L H L H BA, CA, A10 READ ILLEGAL 2) L H L L BA, CA, A10 WRITE WRITE L L H H BA, RA Active ILLEGAL 2) L L H L BA, A10 PRE/PREA ILLEGAL 2) L L L H X Refresh ILLEGAL LLLL O p - C ode, Mode-Add MRS ILLEGAL RE- FRESHING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL LLLL O p - C ode, Mode-Add MRS ILLEGAL MODE REGISTER SETTING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL LLLL O p - C ode, Mode-Add MRS ILLEGAL
- 22 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 (H=High Level, L=Low level, X=Don′t Care) NOTE : 1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2) ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. (ILLEGAL = Device operation and/or data integrity are not guaranteed.) 3) Must satisfy bus contention, bus turn around and write recovery requirements. 4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5) ILLEGAL if any bank is not idle. 6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information. 7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information. 8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9) Power-Down, Self-Refresh can be entered only from All Bank Idle state. Current State CKE n-1 CKE n CS RAS CAS WE Add Action SELF- REFRESHING 8) L H H X X X X Exit Self-Refresh L H L H H H X Exit Self-Refresh L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) POWER DOWN L H X X X X X Exit Power Down (Idle after tPDEX) L L X X X X X NOP (Maintain Power Down) ALL BANKS IDLE 9) H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X Enter Deep Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State = Power Down
- 1 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 Mobile DDR SDRAM Device Operation & Timing Diagram
- 2 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 Device Operations
- 3 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 1. PRECHARGE The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks si multane- ously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. [Table 1] Bank selection for precharge by Bank address bits 2. NO OPERATION(NOP) & DEVICE DESELECT The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control inputs. The Mobile DDR SDRAM is put in NOP mode when CS is activated and RAS, CAS and WE are deactivated. Both Device Deselect and NOP command can not affect oper- ation already in progress. So even if the device is deselected or NOP command is issued under operation, the operation will be completed. A10/AP BA1 BA0 Precharge
000 B a n k A O n l y
001 B a n k B O n l y
1 X X All Banks
Figure 1. Bank Activation Command Cycle timing <tRCD=3CLK, tRRD=2CLK> mined by the values programmed during the MRS cycle. grammed during the MRS cycle.
Figure 2. Burst read operation timing adopted by Mobile DDR SDRAM until the burst length is completed. 1) Burst Length=4, CAS Latency= 3.
Figure 3. Burst write operation timing mand is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. 2) The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
Figure 6. Read interrupted by a precharge timing
- READ INTERRUPTED BY A PRECHARGE
latency from a precharge command to invalid output is equivalent to the CAS latency. 1) Burst Length=8, CAS Latency=3 . command may be issued to the same bank.
- For the earliest possible Precharge command without interrupting a burst Read, the Precharge command may be given on the rising clock edge which
- When a Precharge command interrupts a burst Read operation, the Precharge command given on a rising clock edge terminates the burst with the last
output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same bank after tRP .
- For a Read with Autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP from rising cloc k that comes
- For all cases above, tRP is an analog delay that needs to be c onverted into clock cycles. The number of clock cycles between a Precharge command
timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.
Figure 7. Write interrupted by a write timing
- WRITE INTERRUPTED BY A WRITE
data will be written into the device until the programmed burst length is satisfied.
Figure 8. Write interrupted by a precharge and DM timing
- WRITE INTERRUPTED BY A PRECHARGE & DM
the required amount of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a comple x definition since the write data is sampled by the data strobe and the address is s ampled by the input clock. recovery parameter must make reference to only the clock domain that affects internal write operation, i.e., the input clock domain.
- For the earliest possible Precharge command following a burst Write without interrupting the burst, the minimum time for wri te recovery is defined by
- When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the ti me between the last
state of DM. The minimum time for write recovery is defined by tWR.
- For a Write with autoprecharge command, a new Bank Activate co mmand may be issued to the same bank after tWR+tRP where tWR+t RP starts on
interrupting the Write burst as described in 1 above.
- In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes
a Write command followed by the earliest possible Precharge command which does not interrupt the burst.
Figure 9. Write interrupted by a Read and DM timing
- WRITE INTERRUPTED BY A READ & DM
issued at the next clock edge of that of write command. 1) Burst Length=8, CAS Latency=3 . The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory.
- For Read commands interrupting a burst Write, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay
is 1 clock cycle is disallowed.
- For Read commands interrupting a burst Write, the DM pin mu st be used to mask the input data words which immediately precede the interrupting
- For all cases of a Read interrupting a Write, the DQ and DQS bus es must be released by the driving chip (i.e., the memory co ntroller) in time to allow
the buses to turn around before the Mobile DDR SDRAM drives them during a read operation.
- If input Write data is masked by the Read command, the DQS input is ignored by the Mobile DDR SDRAM.
- Refer to Burst write operation.
Figure 10. Burst stop timing latency set in the mode register. However, the burst stop command is not supported during a burst write operation. 1) Burst Length=4, CAS Latency= 3.
- The Burst Stop command may only be issued on the rising edge of the input clock, CK.
- Burst Stop is only a valid command during Read bursts.
- Burst Stop during a Write burst is undefined and shall not be used.
- Burst Stop applies to all burst lengths.
- Burst Stop is an undefined command during Read with autoprecharge and shall not be used.
- When terminating a burst Read command, the BST command must be issued L
edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
- When the burst terminates, the DQ and DQS pins are tristated.
The Burst Stop command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). The burst read ends after a delay equal to the CAS latency.
Figure 11. DM masking timing issued at the rising or falling edge of data strobe.
Figure 12. Read with auto precharge timing
- READ WITH AUTO PRECHARGE
be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied. 1) Burst Length=4, CAS Latency= 3. 2) The row active command of the precharge bank can be issued after tRP from this point.
Figure 13. Write with auto precharge timing
- WRITE WITH AUTO PRECHARGE
issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). 2) The row active command of the precharge bank can be issued after tRP from this point. 2) DM : Refer to "27. Write Interrupted by Precharge & DM ".
Figure 16. Power down entry and exit timing the device cannot remain in power down mode longer than the refresh period(tREF) of the device. 1) Device must be in the all banks idle state prior to entering Power Down mode. 2) The minimum power down duration is specified by tCKE.
Figure 17. Clock Stop Mode Entry and Exit Stopping a clock during idle periods is an effective method of reducing power consumption. tional clock pulses might be required depending on the system characteristics. Figure shows clock stop mode entry and exit.
- The clock can be stopped after Tn.
- 19 - K522H1HACF-B050 datasheet MCP Memory Rev. 1.0 Timing Diagram
Figure 18. Power Up Sequence for Mobile DDR SDRAM
- POWER UP SEQUENCE FOR MOBILE DDR SDRAM
1) Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2) Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3) Issue precharge commands for all banks of the devices. 4) Issue 2 or more auto-refresh commands. 5) Issue a mode register set command to initialize the mode register. 6) Issue a extended mode register set command for the desired operating modes after normal MRS. The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the initialization sequence, it may lead to unspecified operation. All banks have to be in idle state prior to adjusting MRS and EMRS set.
Figure 19. Basic Timing (Setup, Hold and Access Time @BL=4, CL=3)
Figure 20. Multi Bank Interleaving READ (@BL=4, CL=3)
- MULTI BANK INTERLEAVING READ
Figure 21. Multi Bank Interleaving WRITE (@BL=4)
- MULTI BANK INTERLEAVING WRITE
Figure 22. Read with Auto Precharge (@BL=8) 1) The row active command of the precharge bank can be issued after tRP from this point.
Figure 23. Write with Auto Precharge (@BL=8)
- WRITE WITH AUTO PRECHARGE
Figure 24. Write followed by Precharge (@BL=4)
- WRITE FOLLOWED BY PRECHARGE
Figure 25. Write Interrupted by Precharge & DM (@BL=8)
- WRITE INTERRUPTED BY PRECHARGE & DM
Figure 26. Write Interrupted by a Read (@BL=8, CL=3)
- WRITE INTERRUPTED BY A READ
Figure 27. Read Interrupted by Precharge (@BL=8, CL=3)
- READ INTERRUPTED BY PRECHARGE
Figure 28. Read Interrupted by a Write & Burst Stop (@BL=8, CL=3)
- READ INTERRUPTED BY A WRITE & BURST STOP
Figure 29. Read Interrupted by a Read (@BL=8, CL=3)
- READ INTERRUPTED BY A READ
Figure 30. DM Function (@BL=8) only for write