K4Y50024UC

K4Y50164UC SAMSUNG | Alldatasheet

Document overview

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Technical content

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 1 of 76 512Mbit XDR DRAM(C-die) Revision 1.1 August 2006 XDR is a trademark of Rambus Inc. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. TM

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 2 of 76 Change History Revision Month Year History

1.0 December 2005 - First Copy

• Based on the Rambus XDRTM DRAM Datasheet Version 0.88

1.1 August 2006 - Add comment on page 5

• Add TMIN on Table13, page 57

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 3 of 76 The XDR DRAM device is a general-purpose hi gh-performance memory device suitable fo r use in a broad range of applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 512Mb XDR DRAM device is a CMOS DRAM organized as 32M words by 16bits. The use of Differential Rambus Signaling Level(DRSL) technology permits 4000/3200/2400 Mb/s transfer rate s while using conventional system and board design technologies . XDR DRAM devices are capable of sustained data transfers up to 8000 MB/s. XDR DRAM device architecture allows t he highest sustained bandwidth for multiple, in terleaved randomly addressed memory transac - tions. The highly-efficient protocol yields over 95% utilization while allowing fine access granuarity. The device’s eight banks support up to four interleaved transactions.

0.0 Overview

♦ Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling ♦ Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count ♦ On-chip termination - Adaptive impedance matching - Reduced system cost and routing complexity ♦ Highest sustained bandwidth per DRAM device - Up to 8000 MB/s sustained data rate - Eight banks : bank-interleaved transaction at full bandwidth - Dynamic request scheduling - Early-read-after-write support for maximum efficiency - Zero overhead refresh ♦ Low Latency - 2.0/2.5/3.33ns request packets - Point-to-point data interconnect for fastest possible flight time - Support for low-latency, fast-cycle cores ♦ Low Power - 1.8V V DD - Programmable small-swing I/O signaling(DRSL) - Low power PLL/DLL design - Powerdown self-refresh support - Per pin I/O powerdown for narrow-width operation ♦ 0.49us refresh intervals(32K/16ms refresh) ♦ RoHS compliant

1.0 Features

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 4 of 76 Organization Bandwidth (1/tBIT)a a.Data rate measured in Mbit/s per DQ differential pair. See “Timing Conditions” on page 58 and “ Timing Characteristics” on page 60. Note that tBIT=tCYCLE/8 Latency(tRAC)b b.Read access time tRAC (= tRCD-R+tCAC) measured in ns. See “Timing Parameters” on page 61. Binc c.Timing parameter bin. See “Timing Parameters” on page 61. This is a measure of the number of interleaved read transactions needed for maximum efficiency (the value Ceiling(tRC-R/tRR-D). For bin A, tRC-R/tRR-D=4, and for bin B, tRC-R/tRR-D=5 for bin C, tRC-R/tRR-D =6. Part Number 32Mx16 2400 36 A K4Y50164UC-JCA2 3200 35 B K4Y50164UC-JCB3 4000 28 C K4Y50164UC-JCC4 64Mx8 2400 36 A K4Y50084UC-JCA2 3200 35 B K4Y50084UC-JCB3 4000 28 C K4Y50084UC-JCC4 128Mx4 2400 36 A K4Y50044UC-JCA2 3200 35 B K4Y50044UC-JCB3 4000 28 C K4Y50044UC-JCC4 256Mx2 2400 36 A K4Y50024UC-JCA2 3200 35 B K4Y50024UC-JCB3 4000 28 C K4Y50024UC-JCC4

2.0 Key Timing Parameters/Part Numbers

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 5 of 76 The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are th ree sets of pins used for no rmal signal name denotes the complementary signal of a differential pair. A transaction is a collection of packets needed to complete a memo ry access. A packet is a se t of bit windows on the signals of a bus. There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a set of 2 bit-windows on each signal, while the DQ bus uses a set of 16 bit-windows on each signal. In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T0 contains an activate (ACT) command. This causes row Ra of bank Ba in the memory component to be loaded into the sense amp ar ray for the bank. A second request packet at clock edge T1 contains a write (WR) command. This causes the data packet D(a1) at edge T4 to be written to column Ca1 of the sense amp array for bank Ba. A third request packet at clock edge T 3 contains another write (WR) comm and. This causes the data packet D(a2) at edge T6 to also be written to column Ca2. A final request packet at clock edge T13 contains a precharge (PRE) command. The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-W , tCC , and tWRP . In addition, the spacing between the request packets and data packets is constrained by the tCWD parameter. The spacing of the CFM/ CFMN clock edges is constrained by tCYCLE. The read transaction shows a request packet at clock edge T0 containing an ACT command. This causes row Ra of bank Ba of the mem- ory component to load into the sense amp array for the bank. A second request packet at clock edge T5 contains a read (RD) command. This causes the data packet Q(a1) at edge T11 to be read from column Ca1 of the sense amp array for bank Ba. A third request packet at clock edge T7 contains another RD command. This causes the data packet Q(a2) at edge T13 to also be read from column Ca2. A final request packet at clock edge T10 contains a PRE command. The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-R , tCC , and tRDP . In addition, the spacing between the request and data packets are constrained by the tCAC parameter. * Any system or application incorporating random access memory products should be properly designed, tested and qualified to ensure proper use or access of such memory products. Disproportionate, excessive and/or repeated access to a particular address or addresses may result in reduction of product life. Figure 1 : XDR DRAM Device Write and Read Transactions T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Transaction a: WR a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCC tCWD tCYCLE tWRP tRCD-W a1WR a2WR a3PRE a0ACT D(a2) D(a1) Write Transaction DQ15..0 DQN15..0 CFM CFMN RQ11..0 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Transaction a: RD a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCC tCAC tCYCLE tRDP tRCD-R a1RD a2RD a3PRE a0ACT Q(a2) Q(a1) Read Transaction DQ15..0 DQN15..0 CFM CFMN RQ11..0

3.0 General Description

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 6 of 76 The following table shows the pin assignment of 512Mb x16 XDR DRAM Package. The mechanical dimensions of this package are shown on page 72. Note - Pin #1 is at the A1 postion.

16 DQ10 DQ0 SDO V DD GND V DD VDD GND DQ1 DQ11

15 DQN10 DQN0 RST SCK DQN1 DQN11

14 DQ6 DQ12 GND RQ2 RQ5 RQ6 RQ8 CMD DQ13 DQ7

13 DQN6 DQN12 V

DD RQ1 V REF RQ7 RQ9 V DD DQN13 DQN7

12 V DD GND GND V DD GND GND V DD

11 GND V TERM VDD GND GND V DD GND V TERM GND

DD VDD GND GND GND GND GND 5V DD VDD VTERM VDD VTERM VDD VDD

4 DQ14 DQ4 GND RQ3 RSRV CFMN RQ11 GND DQ5 DQ15

3 DQN14 DQN4 RQ0 RQ4 RSRV CFM RQ10 V

2D Q 2 D Q 8 G N D V DD DQ9 DQ3

1 DQN2 DQN8 SDI V DD GND V DD GND V DD DQN9 DQN3

Top View A B C D E F G H J K L Chip Top View The pin #1(ROW1, COLA) is located at the A1 position on the top side and the A1 position is marked by the marker “ ”. Table 1-1 : x16 Package Pinout(Top View) : 104ball FBGA Package COL ROW

4.0 Pinouts and Definitions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 7 of 76 The following table shows the pin assignment of 512Mb x8 XDR DRAM Package. The mechanical dimensions of this package are shown on page 72. Note - Pin #1 is at the A1 postion.

16 RSRV DQ0 SDO V DD GND V DD VDD GND DQ1 RSRV

15 RSRV DQN0 RST SCK DQN1 RSRV

14 DQ6 RSRV GND RQ2 RQ5 RQ6 RQ8 CMD RSRV DQ7

13 DQN6 RSRV V

DD RQ1 V REF RQ7 RQ9 V DD RSRV DQN7 DD VDD GND GND GND GND GND 5V DD VDD VTERM VDD VTERM VDD VDD

4 RSRV DQ4 GND RQ3 RSRV CFMN RQ11 GND DQ5 RSRV

3 RSRV DQN4 RQ0 RQ4 RSRV CFM RQ10 V

2 DQ2 RSRV GND V DD RSRV DQ3

1D Q N 2 R S R V S D I V DD GND V DD GND V DD RSRV DQN3 Top View A B C D E F G H J K L Chip Top View The pin #1(ROW1, COLA) is located at the A1 position on the top side and the A1 position is marked by the marker “ ”. COL ROW Table 1-2 : x8 Package Pinout(Top View) : 104ball FBGA Package K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50164UC-JCC4 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50084UC-JCB3 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50164UC-JCC4 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50084UC-JCB3 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50164UC-JCC4 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50084UC-JCB3 SAMSUNG 520

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 8 of 76 The following table shows the pin assignment of 512Mb x4 XDR DRAM Package. The mechanical dimensions of this package are shown on page 72. Note - Pin #1 is at the A1 postion.

14 RSRV RSRV GND RQ2 RQ5 RQ6 RQ8 CMD RSRV RSRV

13 RSRV RSRV V

DD RQ1 V REF RQ7 RQ9 V DD RSRV RSRV DD VDD GND GND GND GND GND 5V DD VDD VTERM VDD VTERM VDD VDD

4 RSRV RSRV GND RQ3 RSRV CFMN RQ11 GND RSRV RSRV

3 RSRV RSRV RQ0 RQ4 RSRV CFM RQ10 V

1D Q N 2 R S R V S D I V DD GND V DD GND V DD RSRV DQN3 Top View A B C D E F G H J K L Chip Top View The pin #1(ROW1, COLA) is located at the A1 position on the top side and the A1 position is marked by the marker “ ”. COL ROW Table 1-3 : x4 Package Pinout(Top View) : 104ball FBGA Package K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50164UC-JCC4 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50044UC-JCB3 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50164UC-JCC4 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50044UC-JCB3 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50164UC-JCC4 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50044UC-JCB3 SAMSUNG 520

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 9 of 76 The following table shows the pin assignment of 512Mb x2 XDR DRAM Package. The mechanical dimensions of this package are shown on page 72. Note - Pin #1 is at the A1 postion. DD RQ1 V REF RQ7 RQ9 V DD RSRV RSRV DD VDD GND GND GND GND GND 5V DD VDD VTERM VDD VTERM VDD VDD

2 RSRV RSRV GND V DD RSRV RSRV

1 RSRV RSRV SDI V DD GND V DD GND V DD RSRV RSRV

Top View A B C D E F G H J K L Chip Top View The pin #1(ROW1, COLA) is located at the A1 position on the top side and the A1 position is marked by the marker “ ”. COL ROW Table 1- 4: x2 Package Pinout(Top View) : 104ball FBGA Package K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50164UC-JCC4 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50024UC-JCB3 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50164UC-JCC4 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50024UC-JCB3 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50164UC-JCC4 SAMSUNG 520 K4R SAMSUNG 040 K4Y5017UM -PC SAMSUNG 401 K4R SAMSUNG 040 K4Y50024UC-JCB3 SAMSUNG 520

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 10 of 76 Table2 summarizes the pin functionality of the XDR DRAM device. The first group of pins provide the necessary supply voltages. These include VDD and GND for the core and interface logic, VREF for receiving input signals, and VTERM for the driving output signals. read and write data signals, RQ11 ... RQ0 for carrying request si gnals, and CFM and CFMN for carrying timing information used b y the DQ, DQN and RQ signals. The final set of pins comprise the serial interface that is used for control register accesses. These include RST for initializing the state of the device, CMD for carrying command signals, SDI and SDO for carrying register read data, and SCK for carrying the timing information used by the RST, SDI, SDO, and CMD signals. Table 2 : Pin Description a. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1. All DQN, CFMN, RQ, RSL, and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1. b. The number of DQ pins changes by I/O configuration. See the table below. Signal I/O Type No. of pins Description VDD - - 22 Supply voltage for the core and interface logic of the device. GND - - 24 Ground reference for the core and interface logic of the device. VREF - - 1 Logic threshold reference voltage for RSL signals. VTERM - - 4 Termination voltage for DRSL signals. DQ15..0b I/O DRSLa 16b Positive data signals that carry write or read data to and from the device. DQN15..0b I/O DRSLa 16b Negative data signals that carry write or read data to and from the device. RQ11..0 I RSLa 12 Request signals that carry control and address information to the device. CFM I DIFFCLKa 1 Clock from master — Positive interfac e clock used for receiving RSL signals, and receiving and transmitting DRSL signals from the Channel. CFMN I DIFFCLKa 1 Clock from master — Negative interface clock used for receiving RSL signals, and receiving and transmitting DRSL signals from the Channel. RST I RSLa 1 Reset input — This pin is used to initialize the device. CMD I RSLa 1 Command input — This pin carries command, address, and control register write data into the device. SCK I RSLa 1 Serial clock input — Clock source used fo r reading from and writing to the control registers. SDI I RSLa 1 Serial data input — This pin carries cont rol register read data through the device. This pin is also used to initialize the device. SDO O CMOSa 1 Serial data output — This pin carries control register read data from the device. This pin is also used to initialize the device. RSRVb - - 2b Reserved pins — Follow Rambus XDR sy stem design guidelines for connecting RSRV pins Total pin count per package 104 x16 x8 x4 x2 Singnal No. of pins Singnal No. of pins Singnal No. of pins Singnal No. of pins RSRV 2 RSRV 18 RSRV 26 RSRV 30

5.0 Pin Description

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 11 of 76 A block diagram of the XDR DRAM device is shown in Figure2. It shows all interface pins and major internal blocks. The CFM and CFMN clock signals are received and used by the clock generation logic to produce three virtual clock signals : 1/tCYCLE, 2/tCYCLE, and 16/tCC. The frequency of these signals are 1x, 2x, and 8x that of the CFM and CFMN signals. These virtual signals show the effective data rate of the logic blocks to which they connect; they are not necessarily present in the actual memory component. clocking signal connected to the 1:2 Demux Block that assembles the 24-bit request pa cket. These 24bits are loaded into a regis - ter(clocked by the 1/tCYCLE clocking signal) and decoded by the Decode Block. The V REF pin supplies a reference voltage used by the RQ receivers. Three sets of control signals are produced by the Decode Block. These include the bank(BA) and row(R) addresses for an activate(ACT) command, the bank(BR) and row(REFr) addresses for a refresh activate(REFA) command, the bank(BP) address for a precharge(PRE) command, the bank(BR) adddress for a refresh precharge(REFP) command, and the bank(BC) and column(C and SC) addresses for a read(RD) or write(WR or WRM) command. In addition, a mask(M) is used for a masked write(WRM) command. These commands can all be optionally delayed in increments of tCYCLE under control of delay fields in the request. The control signals of the commands are loaded into registers and presented to the memory core. These registers are clocked at maximum rates determined by core timing parameters, in this case 1/t RR, 1/tPP, and 1/tCC(1/4, 1/4, and 1/2 the frequency of CFM in the -3200 component). These registers may be loaded at any t CYCLE rising edge. Once loaded, they should not be changed until a t RR, tPP, or tCC time later because timing paths of the memory core need time to settle. A bank address is decoded for an ACT command. The indicated row of the selected bank is sensed and placed into the associated sense amp array for the bank. Sensing a row is also referred to as “Opening a page”for the bank. Another bank address is decoded for a PRE command. The indicated bank and associated sense amp array are precharged to a state in which a subsequent ACT command can be applied. Precharging a bank is also called “closing the page” for the bank. After a bank is given an ACT command and before it is given a PRE command, it may receive read(RD) and write(WR) column commands. These commands permit the data in the bank’s associated sense amp array to be accessed. For a WR command, the bank address is decoded. The indicated column of the associated sense amp array of the selected bank is written with the data received from the DQ15 ... DQ0 pins. The bank address is decoded for a RD command. The indicated column of the selected bank’s associated sense amp array is read. The data is transmitted onto the DQ15 ... DQ0 pins. is indicated by the 16/tCC clocking signal connected to the 1:16 Demux Block t hat assembles the 16x16-bit write data packet. The write data is then driven to the selected Sense Amp Array Bank. 16 sixteen-bit words are accessed in the selected Sense Amp Array Bank for a read transaction. The DQ15 ... DQ0 pins transmit the read data packet(Q) in one tCC interval. This is indicated by the 16/tCC clocking signal connected to the 16:1 Mux Block. The VTERM pin supplies a termination voltage for the DQ pins. The RST, SCK, and CMD pins connect to the Control Register block. These pins supply the data, address and conrol needed to write the control registers. The read data for these registers is accessed through the SDO/SDI pins. These pins are also used to initialize the device. The control registers are used to transition between power modes, and are also used for calibrating the high speed transmit and receive circuits of the device. The control registers also supply bank(REFB) and row(REFr) address for refresh operations.

6.0 Block Diagram

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 12 of 76 Figure 2 : 512Mb (8x4Mx16) XDR DRAM Block Diagram 1:2 Demux Decode RQ11..0 1:16 Demux 16:1 Mux 16/tCC 2/tCYCLE reg 12 12 CFM CFMN 1/tCYCLE 1/tCYCLE12 12 RST,SCK,CMD,SDI Control Registers SDO 2/tCYCLE 16/ tCC Bank 0 ACT delay reg 1/tRR ACT logic ... ... {0..1}*tCYCLE decode Bank 0

1 ACT

... decode

1 PRE

{0..3}*tCYCLE ROW ... Sense Amp 0 ... reg 1/tCC ... decode R/W R/W COL COL RD,WR COL logic ... ... reg BA,BR,REFB R,REFr BP,BR,REFB BC C SC M ... Bank Array Sense Amp Array ... ... ... ... Width Demux (WR) reg termination VTERM VREF REFB,REFr WIDTH {0..1}*tCYCLE delay DQ15..0 DQN15..0 16 16 16 16 16/tCC 16x16*26 16x16 16x16 16x16 16x16 3 3 3 6+4 12 (23 - 1)Bank (23 - 1)Sense Amp 16x16*26 16x16*26*212 D[15:0][15:0] S[15:0][15:0] 16x16 16x16 16x16*26 WIDTH Q[15:0][15:0] Width Mux (RD) Byte Mask (WR) Power Mode Logic Calibration Logic Refresh Logic Initialization Logic

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 13 of 76 There are five types of request packets: 1. ROWA — specifies an ACT command 2. COL — specifies RD and WR commands 3. COLM — specifies a WRM command 4. ROWP — specifies PRE and REF commands 5. COLX — specifies the remaining commands Table 3 describes fields within different request packet types. Various request packet type formats are illustrated in Figure3. Each packet type consists of 24 bits sampled on the RQ11..0 pins on two successive edges of the CFM/CFMN clock. The request packet formats are distinguished by the OP3..0 field. This field also specifies the operation code of the desired command. In the ROWA packet, a bank address (BA), row address (R), and command delay (DELA) are specified for the activate (ACT) command. In the COL packet, a bank address (BC), column address (C), sub-column address (SC), comm and delay (DELC), and sub-opcode (WRX) are specified for the read (RD) and write (WR) commands. In the COLM packet, a bank address (BC), column address (C), sub-column address (SC), and mask field (M) are specified for th e masked write (WRM) command. In the ROWP packet, two independent commands may be specified. A bank address (BP) and sub-opcode (POP) are specified for the precharge (PRE) commands. An address field (RA) and sub-opcode (ROP) are specified for the refresh (REF) commands. In the COLX packet, a sub-operation code field (XOP) is specified for the remaining commands. Table 3 : Request Field Description Field Packet Types Description OP3..0 ROWA/ROWP /COL/COLM/COLX 4-bit operation code that specifies packet format. (Encoded commands are in Table 4 on page 15.) DELA ROWA Delay the associated row activate command by 0 or 1 tCYCLE . BA2..0 ROWA 3-bit bank address for row activate command. R11..0 ROWA 12-bit row address for row activate command. SR1..0 ROWA 2-bit sub-row address for sub-row sens ing (see “Sub-Row (Sub-Page) Sensing” on page 50) WRX COL Specifies RD (=0) or WR (=1) command. DELC COL Delay the column read or write command by 0 or 1 tCYCLE . BC2..0 COL/COLM 3-bit bank address fo r column read or write command. C9..4 COL/COLM 6-bit column address for column read or write command. SC3..0 COL/COLM 4-bit subcolumn addres s for column read or column write command for x2/x4/x8 DQ widths. M7..0 COLM 8-bit mask for masked-write command WRM. POP2..0 ROWP 3-bit operation code that specifies row precharge command with a delay of 0 to 3 tCYCLE. (Encoded commands are in Table 6 on page 16). BP2..0 ROWP 3-bit bank address for row precharge command. ROP2..0 ROWP 3-bit operation code that specifies refresh commands. (Encoded commands are in Table 5 on page 15). RA7..0 ROWP 8-bit refresh address field (specifies BR bank address, delay value, and REFr load value) XOP3..0 COLX 4-bit extended operation code that specifies calibration and powerdown commands. (Encoded commands are in Table 7 on page 16).

7.0 Request Packets

A request packet carries address and control information to the memory device. This section contains tables and diagrams for packet formats, field encodings and packet interactions.

7.1 Request Packet Formats

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 14 of 76 T0 T1 T2 T3 CFM RQ11..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN tCYCLE PRE RD WRM ACT RQ11 ROWA Packet RQ10 RQ9 RQ8 RQ7 RQ6 RQ5 RQ4 RQ3 RQ2 RQ1 RQ0 CFM CFMN OP DEL OP R R R R R R R R R SR SR COL Packet OP DEL OP rsrv OP rsrv WR C C BC BC COLM Packet OP M M M M M M C C ROWP Packet OP POP OP ROP OP ROP POP RA POP RA RA RA RA RA BP RA BP RA COLX Packet OP rsrv OP rsrv OP rsrv OP rsrv rsrv rsrv rsrv rsrv rsrv rsrv rsrv rsrv XOP rsrv XOP rsrv XOP rsrv XOP rsrv PDN tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE CA3 DQ15..0 DQN15..0 CFM CFMN RQ11..0 BA BA rsrvOP C C C M M ROP OP BC BC C R R R rsrv rsrv BA rsrv rsrv C rsrv BC C rsrv SC SC SC SC C rsrv BC C rsrv SC SC SC SC rsrv BP rsrv rsrv Figure 3 : Request Packet Formats

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 15 of 76 Operation code fields are encoded within di fferent packet types to specify commands. Table4 through Table7 provides packet type and encoding summaries. Table4 shows the OP field encoding for five packet types. T he COLM and ROWA packets each specify a single command : ACT and WRM. The COL, COLX, and ROWP packets each use additional fiel ds to specify multiple comm ands : WRX, XOP , and POP/ROP, respectively. The COLM packet specifies the masked write command WRM. This is like the WR unmasked write command, except that a mask field M7...0 indicates whether each by te of the write data packet is written or not written. The ROWA packet specifies t he row activate command ACT. The COL packet uses the WRX field to specify the column read and column write(unmasked) commands. Encoding of the ROP field in the ROWP pack et is shown in Table5. The first encoding specifies a NOPR (no operation) command. The REFP command uses the RA field to select a bank to be precha rged. The REFA and REFI commands use the RA field and REFH/M/L registers to select a bank and row to be activated for refresh. The REFI command also increments the REFH/M/L register. The REFP, REFA, and REFI commands may also be delayed by up to 3*t CYCLE using the RA[7:6] field. T he LRR0, LRR1, and LRR2 commands load the REFH/M/L registers from the RA[7:0] field. Table 4 : OP Field Encoding Summary OP [3:0] Packet Command Description 0000 - NOP No operation.

0001 COL

DELC*tCYCLE. DELC*tCYCLE. 0010 COLX CALy XOP3..0 specifies a calibrate or powerdown command — see Table 7 on page 16.

0011 ROWP

PREx POP2..0 specifies a row precharge command — see Table 6 on page 16. REFy,LRRr ROP2..0 specifies a row refresh command or load REFr register command — see Table 5 on page 15. bank after DELA*tCYCLE. 1xxx COLM WRM Column write command (masked) — ma sk M7..0 specifies which bytes are written. Table 5 : ROP Field Encoding Summary ROP[2:0] Command Description

000 NOPR No operation

001 REFP Refresh precharge command. Bank RA2..0 is precharged. This command is delayed by {0,1,2,3}*tCYCLE (the value is given by the expression (2*RA[7]+RA[6]).

010 REFA

Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp. This command is delayed by {0,1,2,3}*t CYCLE (the value is given by the expression (2*RA[7]+RA[6]).

011 REFI

Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp. This command is delayed by {0,1,2,3}*t CYCLE (the value is given by the expression (2*RA[7]+RA[6]). R[11:0] field of REFH/M/L register is incremented after the activate command has completed. 100 LRR0 Load Refresh Low Row register (REFL) . RA[7:0] is stored in R[7:0] field. 101 LRR1 Load Refresh Middle Row register (RE FM). RA[3:0] is stored in R[11:8] field. 110 LRR2 Load Refresh High Row register — not used with this device. 111 - Reserved

7.2 Request Field Encoding

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 16 of 76 The REFH/M/L registers are also refreshed to as the REFr regi sters. Note that only the bits that are needed for specifying the refresh row(11 bits in all) are implemented in the REFr registers - the rest are reserved. Note also t hat the RA2 ... RA0 field that sp ecifies the Table6 shows the POP field encoding in the ROWP packet. The first encoding specifies a NOPP(no operation) command. There are four variations of PRE(precharge) command. Each uses the BP field to specify the bank to be precharged. Each also specifies a differ ent delay of up to 3*t CYCLE using the POP[1:0] field. A precharge command may be specified in addition to a refresh command using the ROP field. Table7 shows the XOP field encoding in the COLX packet. This field encodes the remaining commands. The CALC and CALE commands perform calibration operations to ensure signal integrity on the Channel. See “Calibration Transactions” on page 44. The PDN command causes the device to enter a power-down state. See”Power State Management” on page 45. Table 6 : POP Field Encoding Summary POP [2:0] Command Description 000 NOPP No operation. 001 - Reserved. 010 - Reserved. 011 - Reserved. 100 PRE0 Row precharge command — Bank BP2..0 is precharged. This command is delayed by 0*t CYCLE. 101 PRE1 Row precharge command — Bank BP2..0 is precharged. This command is delayed by 1*tCYCLE. 110 PRE2 Row precharge command — Bank BP2..0 is precharged. This command is delayed by 2*tCYCLE. 111 PRE3 Row precharge command — Bank BP2..0 is precharged. This command is delayed by 3*tCYCLE. Table 7 : XOP Field Encoding Summary XOP [3:0] Command Command and Description XOP [3:0] Command Command and Description 0000 - Reserved. 1000 CALC Current calibration command. 0001 - Reserved. 1001 CALZ Impedance calibration command. 0010 - Reserved. 1010 CALE End calibration command (CALC). 0011 - Reserved. 1011 - Reserved. 0100 - Reserved. 1100 PDN Enter powerdown power state. 0101 - Reserved. 1101 - Reserved. 0110 - Reserved. 1110 - Reserved. 0111 - Reserved. 1111 - Reserved.

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 17 of 76 A summary of request packet interaction is shown in Table8. Each case is limited to request packets with commands that perform memory operations(including refresh commands ). This includes all commands in ROWA, ROWP, COL, and COLM packets. The commands in COLX packets are described in later sections. See “Maintenance Operations” on page 42. Request packet/command “a” is followed by request/ command “b”. The minimum possible spacing between these two packet/command is 0*tCYCLE. However, a larger time interval may be needed because of a resource interaction between the two packet/commands. If the minimum possible sapcing is 0*tCYCLE, then an entry of “No limit” is shown in the table. Note that the spacing values shown in the table are relative to the effective beginning of a pa cket/command. The use of the del ay field with a command will delay the position of the effective packet/command from the position of the actual packet/command. See “Dynamic Request Scheduling” on page 23 . Any of the packet/command encoding under one of the four operation types is equivalent in terms of the resource constraints. Therefore. both the horisontal columns(packet “a”) and vertical rows(packet “b”) of the interaction table are divided into four major groups. The four possible operation types for request packet a and b include : : [A] Active Row ROWA/ACT ROWP/REFA ROWP/REFI : [R] Read Column COL/RD : [W] Write Column COL/WR COLM/WRM : [P] Precharge Row ROWP/PRE ROWP/REFP Table 8 : Packet Interaction Summary First packet/command to bank Ba Second packet/command to bank Bb Activate Row [A] Read Column [R] Write Column [W] Precharge Row [P] ROWA - ACT Bb ROWP - REFA Bb ROWP - REFI Ba COL - RD Bb COL - WR Bb COLM - WRM Bb ROWP - PRE Bb ROWP - REFP Bb Activate Row [A] ROWA - ACT Ba ROWP - REFA Ba ROWP - REFI Ba Ba,Bb different Case AAd: tRR Case ARd: No limit Case AWd: No limit Case APd: No limit Ba,Bb same Case AAs: tRC Case ARs: t RCD-R Case AWs: t RCD-W Case APs: t RAS Read Column [R] COL - RD Ba Ba,Bb different Case RAd: No limit Case RRd: tCC Case RWd:a t∆RW a. t∆RW is equal to tCC + tRW-BUB,XDRDRAM+ tCAC - tCWD and is defined in Table 18. This also depends upon propagation delay - See “Propagation Delay” on page 32. Case RPd: No limit Ba,Bb same Case RAs:b tRDP+tRP b. A PRE command is needed between the RD and ACT/REFA commands or the WR/WRM and ACT/REFA commands. Case RRs: tCC Case RWs: a t∆RW Case RPs: tRDP Write Column [W] COL - WR Ba COLM - WRM Ba Ba,Bb different Case WAd: No limit Case WRd:c t∆WR c. t∆RW is defined in Table 18. Case WWd: tCC Case WPd: No limit Ba,Bb same Case WAsb:tWRP+tRP Case WRs: c t∆WR Case WWs: tCC Case WPs: t WRP Precharge Row [P] ROWP - PRE Ba ROWP - REFP Ba Ba,Bb different Case PAd: No limit Case PRd: No limit Case PWd: No limit Case PPd: tPP Ba,Bb same Case PAs: tRP Case PRs:d tRP+tRCD- R d. An ACT command is needed between the PRE/REFP and RD commands or the PRE/REFP and WR/WRM commands. Case PWs:d tRP+tRCD-W Case PPs: tRC See Examples: Figure 4 Figure 5 Figure 6 Figure 7

7.3 Request Packet Interactions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 18 of 76 In Figure4. the interaction interval for the AAd case is t RR. This parameter is the row-to-row time and is the minimum interval between activate commands to different banks of a device. The interaction interval for the AAs case is t RC. This is the row cycle time parameter and is the minimum interval between activate commands to same banks of a device. A precharge operation must be inserted between the two activate operations. The interaction interval for the RAs case is tRDP + tRP. A precharge operation must be inserted between the read and activate operation. The minimum interval between a read and a precharge operation to a bank is t RDP. The minimum interval between a precharge and an activate operation to a bank is tRP. The interaction interval for the WAs case is tWDP + tRP. A precharge operation must be inserted between the read and the activate oper- ation. The minimum interval between a wr ite and a precharge operation to a bank is t WDP. The minimum interval between a precharge and an activate operation to a bank is tRP. The interaction interval for the PAs case is tRP. The minimum interval between a precharge and an activate operation to a bank is tRP. In Figure5, the interaction inte rval for the ARs case is t RCD-R. This is the row-to-column-read time parameter and represents the minimum interval between an activate operation and a read operation to a bank. The interaction interval for the RRd and RRs cases is t CC. This is the column-to-column time parameter and represents the minimum interval between two read operations. The interaction interval for the WRd and WRs cases is t ∆WR. This is the write-to-read time parameter and represents the minimum interval between a write and a read operation to any banks. See “Read/Write Interaction” on page 31. The interaction interval for the PRs case is t RP + tRCD-R. An activate operation must be in serted between the precharge and the read operation. The minimum interval between a precharge and an activate operation to a bank is tRP. The minimum interval between an acti- vate and a read operation to a bank is tRCD-R. In Figure6. the interaction interval for the AWs case is t RCD-W. This is the row-to-column-write timing parameter and represents the minimum interval between an activate operation and a write operation to a bank. The interaction interval for the RWd and RWs cases is t ∆RW. This is the read-to-write time parameter and represents the minimum interval between a read and a write operation to any banks. See “Read/Write Interaction” on page 31. The interaction interval for the WWd and WWs cases is t CC. This is the column-to-column time parameter and represents the minimum interval between two write operations. The interaction interval for the PWs case is t RP + tRCD-W. An activate operation must be inse rted between the precharge and the write operation. The minimum interval between a precharge and an activate operation to a bank is tRP. The minimum interval between an acti- vate and a write operation to a bank is tRCD-W. In Figure7, the interaction interval for the APs case is tRAS. This parameter is the minimum activate-to-precharge time to a bank. The interaction interval for the RPs and WPs cases are t RDP and tWDP, respectively. These are the read-or write-to-precharge time parameters to a bank. Ths interaction interval for the PPd case is t PP. This parameter is the precharge-to-precharge time and the minimum interval between precharge commands to different banks of a device. The interaction interval for the PPs case is t RC. This is the row cycle time parameter and the minimum interval between precharge commands to same banks of a device. An activate operation must be inserted between the two activate operations. This activate opera- tion must be placed a time tRP after the first, and a time tRAS before the second precharge. The first request is shown along the vertical axis on the left of the table. The second request is shown along the horizontal axis at the top of the table. Each request includes a bank specification “Ba” and “Bb”. The first and second banks may be the same, or they may be different. These two subcases for each interaction are shown along the vertical axis on the letf. There are 32 possible interaction cases altogether. The table gives each case a label of the form “xyz”, where “x” and “y” are one of the four operation types(“A” for Activate, “R” for Read, “W” for Write, or “P” for Precharge) for the first and second request, respectively, and “z” indicates the same bank(“s”) or different bank(“d”). Along the horizontal axis at the bottom of the table are cross references to four figures(Figure4 through Figure7). Each figure illustrates the eight cases in the corresponding vertical column. Thus, Figure4 shows the eight cases when the second request is an activate oper- ation(“A”). In the following discussion of the cases, only those in which the interaction interval is greater than tCYCLE will be described.

7.4 Request Interactions Cases

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 19 of 76 T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 a: ROWA Packet with ACT,Ba,Ra T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 AAd Case (activate-activate-different bank) AAs Case (activate-activate-same bank) RAd Case (read-activate-different bank) RAs Case (read-activate-same bank) WAd Case (write-activate-different bank) WAs Case (write-activate-same bank) PAd Case (precharge-activate-different bank) PAs Case (precharge-activate-same bank) b: ROWA Packet with ACT,Bb,Rb Ba Bb a: ROWA Packet with ACT,Ba,Ra b: ROWA Packet with ACT,Bb,Rb Ba = Bb a: COL Packet with RD,Ba,Ca b: ROWA Packet with ACT,Bb,Rb Ba Bb a: COL Packet with RD,Ba,Ca b: ROWA Packet with ACT,Bb,Rb Ba = Bb a: COL Packet with WR,Ba,Ca b: ROWA Packet with ACT,Bb,Rb Ba Bb a: COL Packet with WR,Ba,Ca b: ROWA Packet with ACT,Bb,Rb Ba = Bb a: ROWP Packet with PRE,Ba b: ROWA Packet with ACT,Bb,Rb Ba Bb a: ROWP Packet with PRE,Ba b: ROWA Packet with ACT,Bb,Rb Ba = Bb No limit a PRE b ACT No limit a WR b ACT No limit a RD b ACT tRR b ACT tRCa ACT tRAS tRP a ACT b ACT a PRE tRDP+tRP tRDP tRP a RD b ACT a PRE tWRP+tRP tWRP tRP a WR b ACT a PRE tRPa PRE b ACT DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 Figure 4 : ACT-, RD-, WR-, PRE-to-ACT Packet Interactions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 20 of 76 Figure 5 : ACT-, RD-, WR-, PRE-to-RD Packet Interactions T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 a: ROWA Packet with ACT,Ba,Ra T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 ARd Case (activate-read different bank) ARs Case (activate-read same bank) RRd Case (read-read different bank) RRs Case (read-read same bank) WRd Case (write-read different bank) W Rs Case (write-read same bank) PRd Case (precharge-read different bank) PRs Case (pre charge-read same bank) b: COL Packet with RD,Bb,Cb Ba Bb a: ROWA Packet with ACT,Ba,Ra b: COL Packet with RD,Bb,Cb Ba = Bb a: COL Packet with RD,Ba,Ca b: COL Packet with RD,Bb,Cb Ba Bb a: COL Packet with RD,Ba,Ca b: COL Packet with RD,Bb,Cb Ba = Bb a: COL Packet with WR,Ba,Ca b: COL Packet with RD,Bb,Cb Ba Bb a: COL Packet with WR,Ba,Ca b: COL Packet with RD,Bb,Cb Ba = Bb a: ROWP Packet with PRE,Ba b: COL Packet with RD,Bb,Cb Ba Bb a: ROWP Packet with PRE,Ba b: COL Packet with RD,Bb,Cb Ba = Bb No limit a PRE b RD No limit a ACT b RD tRP+tRCD-R tRP tRCD-R a PRE b RD B ACT tRCD-Ra ACT b RD tCC b RD a RD t∆WR b RD a WR t∆WR b RD a WR tCC b RD a RD DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 21 of 76 Figure 6 : ACT-, RD-, WR-, PRE-to-WR Packet Interactions T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 a: ROWA Packet with ACT,Ba,Ra T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 AWd Case (activate-write different bank) AWs Case (activate-write same bank) RWd Case (read-write-different bank) RWs Case (read-write-same bank) WWd Case (write-write different bank) WWs Case (write-write same bank) PWd Case (precharge-write different bank) PWs Case (precharge-write same bank) b: COL Packet with WR,Bb,Cb Ba Bb a: ROWA Packet with ACT,Ba,Ra b: COL Packet with WR,Bb,Cb Ba = Bb a: COL Packet with RD,Ba,Ca b: COL Packet with WR,Bb,Cb Ba Bb a: COL Packet with RD,Ba,Ca b: COL Packet with WR,Bb,Cb Ba = Bb a: COL Packet with WR,Ba,Ca b: COL Packet with WR,Bb,Cb Ba Bb a: COP Packet with WR,Ba,Ca b: COL Packet with WR,Bb,Cb Ba = Bb a: ROWP Packet with PRR,Ba b: COL Packet with WR,Bb,Cb Ba Bb a: ROWP Packet with PRE,Ba b: COP Packet with WR,Bb,Cb Ba = Bb No limit a PRE b WR No limit a ACT b WR tRP+tRCD-W tRP a PRE b WR B ACT tRCD-W a ACT b WR t∆RW tCC b WR a WR tCC b WR a WR tCAC D(b) Q(a) tCWD tCYCLE a RD b WR t∆RW tCAC D(b) Q(a) tCWD tCYCLE a RD b WR DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..D0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 tCC tCC tRCD-W

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 22 of 76 Figure 7 : ACT-, RD-, WR-, PRE-to-PRE Packet Interactions T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 a: ROWA Packet with ACT,Ba,Ra T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 T0 T1 T2 T3 CFM RQ11..0 DQ15..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN DQN15..0 APd Case (activate-precharge different bank) APs Case (activate-precharge same bank) RPd Case (read-precharge different bank) RPs Case (r ead-precharge same bank) WPd Case (write-precharge different bank) WPs Case (write-precharge same bank) PPd Case (precharge-precharge different bank) PPs Case (precharge-precharge same bank) b: ROWP Packet with PRE,Bb Ba Bb a: ROWA Packet with ACT,Ba,Ra b: ROWP Packet with PRR,Bb Ba = Bb a: COL Packet with RD,Ba,Ca b: ROWP Packet with PRE,Bb Ba Bb a: COL Packet with RD,Ba,Ca b: ROWP Packet with PRR,Bb Ba = Bb a: COL Packet with WR,Ba,Ca b: ROWP Packet with PRE,Bb Ba Bb a: COL Packet with WR,Ba,Ca b: ROWP Packet with PRE,Bb Ba = Bb a: ROWP Packet with PRE,Ba b: ROWP Packet with PRE,Bb Ba # Bb a: ROWP Packet with PRE,Ba b: ROWP Packet with PRE,Bb Ba = Bb No limit a WR b PRE No limit a RD b PRE tRC tRP tRAS a PRE b PRE b ACT No limit a ACT b PRE tPP b PRE a PRE tRAS b PRE a ACT tRDP b PRE a RD tWRP b PRE a WR DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 23 of 76 Delay fields are present in the ROWA, COL, and ROWP packet. They permit the associated command to optionally wait for a time of one (or more) tCYCLE before taking effect. This allows a memory controller more scheduling flexibility when issuing request packets. Figure8 illustrates the use of the delay fields. In the first timing diagram, a ROWA packet with an ACT command is present at cycle T 0. The DELA field is set to “1”. This request packet will be equivalent to a ROWA packet with an ACT command at cycle T1 with the DELA field is set to “0”. This equivalence should be used when analyzing request packet interactions. In the second timing diagram, a COL packet with a RD command is present at cycle T0. The DELC field is set to “1”. This request packet will be equivalent to a COL packet with an RD command at cycle T 1 with the DELC field is set to “0”. This equivalence should be used when analyzing request packet interactions. In a similar fashion, a COL packet with a WR command is present at cycle T 12. The DELC field is set to”1”. This request packet will be equivalent to a COL packet with a WR command at cycle T 13 with the DELC field is set to “0”. This equivalence should be used when analyzing request packet interactions. In the COL packet with a RD command example, the read data delay, tCAC is measured between the Q read data packet and the virtual COL packet at cycle T1. Likewise, for the example with the COL packet with a WR command, the write data delay, t CWD is measured between the D write data packet and the virtual COL packet at cycle T13. In the third timing diagram, a ROWP packet with a PRE command is present at cycle T 0. The DEL field(POP[1:0]) is set to “11”. This request packet will be equivalent to a ROWP packet with a PRE command at cycle T1 with the DEL field is set to “10”, it will be equiva- lent to a ROWP packet with a PRE commmand at cycle T 2 with the DEL field is set to “01”, and it will be equivalent to a ROWP packet with a PRE command at cycle T3 with the DEL field is set to “00”. This equivalence should be used when analyzing request packet inter- actions. In the fourth timing diagram, a ROWP packet with a REFP command is present at cycle T 0. The DEL field(RA[7:6] ) is set to “11”. This request packet will be equivalent to a ROWP packet with a REFP command at cycle T1 with the DEL field is set to “10”, it will be equiva- lent to a ROWP packet with a REFP command at cycle T 2 with the DEL field is set to “01”, and it will be equivalent to a ROWP packet with a REFP command at cycle T 3 with the DEL field is set to “00”. This equi valence should be used when analyzing request packet interactions. The two examples for the REFA and REFI commands are identical to the example just described for the REFP command. The ROWP packet allows two independent operations to be specified. A PRE precharge command uses the POP and BP fields, and the REFP , REFA, or REFI commands use the ROP and RA fields. Both operations have an optional delay fi eld(the POP field for the PRE command and the RA field with the REFP , REFA, or REFI commands). The two delay mechanisms are independent of one another. The POP field does not affect the timing of the REFP, REFA, or REFI commands, and the RA field does not affect the timing of the PR E command. When the interactions of a ROWP packet are analyzed, it must be remembered that there are two independent commands specified, both of which may affect how soon the next request packet can be issued. The constraints from both commands in a ROWP packet must be considered, and the one that requires the l onger time interval to the next request pack et must be used by the memory control ler. Furthermore, the two commands within a ROWP packet may not reference the same bank in the BP and RA fields.

7.5 Dynamic Request Scheduling

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 24 of 76 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 tCYCLE tCAC tCYCLE DEL0 ACT Q T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 tCYCLE ROWA/ACT Command COL/RD and COL/WR Commands ROWP/PRE Command DEL0 RD tCWD D DEL0 WR DEL1 ACT DEL1 RD DEL1 WR DEL2 PRE DEL3 PRE DEL0 PRE DEL1 PRE ACT w/DEL=1 at T0 is equivalent to ACT w/DEL=0 at T1 RD w/DEL=1 at T0 is equivalent to RD w/DEL=0 at T1 WR w/DEL=1 at T12 is equivalent to WR w/DEL=0 at T13 PRE w/DEL=3 at T0 is equivalent to PRE w/DEL =2 at T1 or PRE w/DEL=1 at T2 or PRE w/DEL=0 at T3 Note DEL value is specified by {POP1, POP0} field. DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 tCYCLE ROWP/REFP,REFA,REFI Commands DEL2 REFP DEL3 REFP DEL0 REFP DEL1 REFP REFP w/DEL=3 at T0 is equivalent to REFP w/DEL=2 at T1 or REFP w/DEL=1 at T2 or REFP w/DEL=0 at T3 Note DEL value is specified by {RA7, RA6} field. DQ15..0 DQN15..0 CFM CFMN RQ11..0 DEL2 REFI DEL3 REFI DEL0 REFI DEL1 REFI REFI w/DEL=3 at T13 is equivalent to REFI w/DEL=2 at T14 or REFI w/DEL=1 at T15 or REFI w/DEL=0 at T16 DEL2 REFA DEL3 REFA DEL0 REFA DEL1 REFA at T7 or REFA w/DEL=1 at T8 or REFA w/DEL=0 at T9 REFA w/DEL=3 at T6 is equivalent to REFA w/DEL=2 Note DEL value is specified by DELA field. Note DEL value is specified by DELC field. Figure 8 : Request Scheduling Examples

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 25 of 76 Figure9 shows four examples of memory wr ite transactions. A transaction is one or mo re request packets (and the associated data packets) needed to perform a memory access. The state of the memory core and the address of the memory access determine how many request packets are needed to perform the access. The first timing diagram shows a page-hit write transaction. In this case, the selected bank is already open (a row is already present in the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the row already sensed (a page hit). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba. In this case, write data may be directly written into the sense amp array for the bank, and row operations(activated or precharge) are not needed. A COL packet with WR command to co lumn Ca1 of bank Ba is presented on edge T 0, and a second COL packet with WR command to column Ca1 of bank Ba is presented on edge T 2. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay tCWD. The two COL packets are separated by the column-cycle time t CC. This is also the length of each write data packet. The second timing diagram shows an example of a page-miss write transaction. In this case, the selected bank is already open (a row is already present in the sense amp array for the bank). However, the selected row for the memory access does not match the addres s of the row already sensed (a page miss). This comparsion must be done in the memory controller. In this example, the access is mad e to row Ra of bank Ba, and the bank contains a row other than Ra. In this case, write data may not be directly written into the s ense amp array for the bank. It is necessary to close the presen t row (precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T 0. An activate command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with WR command to column Ca1 of bank Ba is presented on edge T 7 a time t RCD-W later. A second COL packet with WR comm and to column Ca2 of bank Ba is presented on edge T9. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay t CWD. The two COL packets are separated by the column-cycle time tCC. This is also the length of each write data packet. The third timing diagram shows an example of a page-empty wirte transaction. In this case, the selected bank is already closed (no row is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory controller must still remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba. In this case, write data may not be directly written into the sense amp array for the bank. It is necessary to access the reque sted row (activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T0. A COL packet with WR command to column Ca1 of bank Ba is presented on edge T1 a time tRCD-W later. A second COL packet with WR command to column Ca2 of bank Ba is presented on edge T3. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay tCWD. The two COL packets are separated by the column-cycle time tCC. This is also the length of each write data packet. After the final write command, it may be neces- sary to close the present row (precharge). A precharge command (PRE to bank Ba) is presented on edge T 14 a time tWRP after the last COL packet with a WR command. The decisio n whether to close the bank or leave it open is made by memory controller and its page policy. The fourth timing diagram shows another example of a page-empty write transaction. This is similar to the previous example except that only a single write command is presented, rather than two write commands. This example shows that even with a minimum length write transaction, t RAS parameter will not be a constraint. The t RAS measures the minimum time between an activate command and a precharge command to a bank. This time inte rval is also constrained by the sum t RCD-W + tWRP which will be larger for a write transac- tion. These two constraints (tRAS and tRCD-W + tWRP) will be a function of the memory device’s speed bin and the data transfer length (the number of write commands issued between the activate and precharge commands), and the tRAS parameter could become a constraint for future speed bins. In this example, the sum tRCD-W + tWRPs is greater than tRAS by the amount ∆tRAS.

8.0 Memory Operations

8.1 Write Transactions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 26 of 76 Figure 9 : Write Transactions T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 tCC tCWD tCYCLE Transaction a: WR a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCC tCWD tCYCLE tRP tRCD-W WR WR WR WR PRE ACT D(a2) D(a1) D(a2) D(a1) T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Transaction a: WR a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCC tCWD tCYCLE tWRP tRCD-W WR WR PRE ACT D(a2) D(a1) T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Transaction a: WR a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCWD tCYCLE tRCD-W WR PRE ACT D(a1) tRAS Transaction b: WR b0 = {Bb,Rb} b1 = {Bb,Cb1} b2 = {Bb,Cb2} b3 = {Bb}Bb = Ba ACT tRP Page-hit Write Example Page-miss Write Example Page-empty Write Example Page-empty Write Example - Core Limited DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 tWRP ∆tRAS tCWD tDP

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 27 of 76 Figure10 shows four examples of memory read transactions. A trans action is one or more request packets (and the associated data packets) needed to perform a memory access. The state of the me mory core and the address of memo ry access determine how many request packets are needed to perform the access. The first timing diagram shows a page-hit r ead transaction. In this case, the selected bank is already open (a row is already p resent in the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the row already sensed (a page hit). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba. In this case, read data may be directly r ead from the sense amp array for the bank and no row operations (actiavate or precharg e) are needed. A COL packet with RD command to colu mn Ca1 of bank Ba is presented on edge T 0 and a second COL packet with RD command to column Ca2 of bank Ba is presented on edge T 2. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay t CAC. The two COL packets are separated by the column-cycle time t CC. This is also the length of each read data packet. The second timing diagram shows an example of a page-miss read transaction. In this case, the selected bank is already open (a row is already present in the sense amp array for the bank). However, the selected row for the memory access does not match the addres s of the row already sensed(a page miss). This co mparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba, and the bank contains a row other than Ra. In this case, read data may not be directly read from the sens e amp array for the bank. It is nec essary to close the present ro w (precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T 0. An activate command (ACT to row Ra of bank Ba) is presented on edge T6 a time tRP later. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T 11 a time t RCD-R later. A second COL packet with RD command to column Ca2 of bank Ba is presented on edge T13. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay t CAC. The two COL packets are separated by the column-cycle time tCC. This is also the length of each read data packet. The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is already closed (no row is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory controller must still remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba. In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to access the requested row (acti- vated). An activate command (ACT to row Ra of bank Ba) is presented on edge T 0. A COL packet with RD command to column Ca1 of bank Ba is presented on edge T5 a time tRCD-R later. A second COL packet with RD command to column Ca2 of bank Ba is presented on edge T7. Two read data packets Q(a1) and Q(a2) follow these COL packets after the read data delay t CAC. The two COL packets are separated by the column-cycle time tCC. This is also the length of each read data packet. After the final read command, it may be neces- sary to close the present row (precharge). A precharge command - PRE to bank Ba - is presented on edge T10 a time tRDP after the last COL packet with a RD command. Whether the bank is closed or left open depends on the memory controller and its page policy. The fourth timing diagram shows another example of a page-empty read transaction. This is similar to the previous example except that it uses one read command instead of two read commands. In this case, the core parameter tRAS may also be a constraint upon when the precharge command may be issued. The tRAS measures the minimum time between an activate command and a precharge command to a bank. This time interval is also constrained by the sum t RCD-R + tRDP and must be set to whichever is larger. These two constraints (tRAS and tRCD-R + tRDP) will be a function of the memory device’s speed bin and the data transfer length (the number of read commands issued between the activate and precharge commands). In this example, the tRAS is greater than the sum tRCD-R + tRDP by the amount ∆tRDP.

8.2 Read Transactions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 28 of 76 Figure 10 : Read Transactions T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Transaction a: RD a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCC tCAC tCYCLE Transaction a: RD a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCC tCAC tCYCLE tRP tRCD-R RD RD RD RD PRE ACT Q(a2) Q(a1) Q(a2) Q(a1) T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Transaction a: RD a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCC tCAC tCYCLE tRDP tRCD-R RD RD PRE ACT Q(a2) Q(a1) T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Transaction a: RD a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} tCAC tCYCLE tRCD-R RD PRE ACT Q(a1) tRAS Transaction b: RD b0 = {Bb,Rb} b1 = {Bb,Cb1} b2 = {Bb,Cb2} b3 = {Bb}Bb = Ba ACT tRP Page-hit Read Example Page-miss Read Example Page-empty Read Example Page-empty Read Example - Core Limited DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 tRDP ∆tRDP

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 29 of 76 Figure11 shows two examples of interleav ed transactions. Interleaved tr ansactions are overlapped with one another; a transactio n is started before an earlier one is completed. The timing diagram at the top of the figure shows interleaved write transactions. Each transaction assumes a page-empty access; that is, a bank is in a closed state prior to an access and is precharged after the access. With this assumption, each transaction requi res the same number of request packets at the same relative positions. If bank were allowed to be in an open state, then each transaction would require a different number of request packets depending upon whether the transaction was page-empty, page-hit or page-miss. This situ- ation is more complicated for the memory controller and will not be analyzed in this document. In the interleaved page-empty write example, there are four sets of request pins RQ11...0 shown along the left side of the timing diagram. The first three show the timing slots used by each of the three requests packet types (ACT, COL and PRE), and the fourth set (A LL) shows the previous three merged together. Th is allows the pattern used for allocating request slots for the different packets t o be seen more clearly. There should not be interference between t he interleaved transactions due to resource conflicts because each bank address - Ba, Bb, Bc, Bd and Be - is assumed to be different from another. If two of the bank addresses are the same, the later transaction would need to wait until the earlier transaction had completed its precharge operation. Five different banks are needed because the effective tRC (tRC + ∆tRC) is 20*tCYCLE. The slots at {T 1, T3, T5, T7, T9, T11, ...} are used for COL packets with WR comm ands. This frequency of the COL packet spacing is determined by the t CC parameter and by the fact that there are two column accesses per row access. The phasing of the COL packet spacing is determined by the tRCD-W parameter. If the value of tRCD-W required the COL packets to occupy the same request slots as the ROWA packets (this case is not shown), the DELC field in the COL packet could be used to place the COL packet one tCYCLEs earlier. to a bank in each transaction. The DQ bus is completely filled with write data; no idle cycles need to be introduced because there are no resource conflicts in this example. The slots at {T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of ROWP packet spacing is determined by the tPP parameter. The phasing of the ROWP packet spacing is determined by the t WRP paramter. If the value of t WRP required the ROWP packets to occupy the same request slots as the ROWA or COL packets already assigned (this case is not shown), the delay field in the ROWP packet could be used to place the ROWP packet one or more tCYCLE earlier. There is an example of an interleaved page-empt y read at the bottom of the figure. As before, there are four sets of request pi ns RQ11...0 shown along the left side of the timing diagram, allowing the pattern used for allocating request slots for the different packets to be seen more clearly. should not be interference between the interleaved transactions due to resource conflicts because each bank address - Ba, Bb, B c and Bd - is assumed to be different from another. Four different banks are needed because the effective tRC is 16 * tCYCLE. The slots at {T5, T7, T9, T11, ...} are used for COL packets with RD commands. This frequency of the COL packet spacing is determined by the tCC paramter and by the fact that there are two column accesses per row access. The phasing of the COL packet spacing is deter- mined by the tRCD-R parameter. If the value of tRCD-R required the COL packets to occupy the same request slots as the ROWA packets (this case is not shown), the DELC field in the COL packet could be used to place the packet one tCYCLE earlier. from a bank in each transaction. The DQ bus is completely f illed with read data - That is, no idle cycles need to be introduced because there are no resource conflicts in this example. The slots at {T 10, T14, T18, T22, ...} are used for ROWP packets with PRE comm ands. This frequency of the ROWP packet spacing is determined by the t PP parameter. The phasing of the ROWP packet spacing is determined by the t RDP parameter. If the value of t RDP required the ROWP packets to occupy the same request slots as the ROWA or COL packets already assigned (this case is not shown), the delay field in the ROWP packet could be used to place the ROWP packet one or more tCYCLEs earlier.

8.3 Interleaved Transactions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 30 of 76 Figure 11 : Interleaved Transactions T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Transaction a: WR a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} Transaction b: WR b0 = {Bb,Rb} b1 = {Bb,Cb1} b2 = {Bb,Cb2} b3 = {Bb} Transaction c: WR c0 = {Bc,Rc} c1 = {Bc,Cc1} c2 = {Bc,Cc2} c3 = {Bc} Transaction d: WR d0 = {Bd,Rd} d1 = {Bd,Cd1} a2 = {Bd,Cd2} d3 = {Bd} Transaction e: WR e0 = {Be,Re} e1 = {Be,Ce1} e2 = {Be,Ce2} e3 = {Be} Bf = Ba are different Ba,Bb,Bc,Bd,Be D(a2) D(a1) D(b2) D(b1) D(c2) Transaction a: RD a0 = {Ba,Ra} a1 = {Ba,Ca1} a2 = {Ba,Ca2} a3 = {Ba} Transaction b: RD b0 = {Bb,Rb} b1 = {Bb,Cb1} b2 = {Bb,Cb2} b3 = {Bb} Transaction c: RD c0 = {Bc,Rc} c1 = {Bc,Cc1} c2 = {Bc,Cc2} c3 = {Bc} Transaction d: RD d0 = {Bd,Rd} d1 = {Bd,Cd1} a2 = {Bd,Cd2} d3 = {Bd} Transaction e: RD e0 = {Be,Re} e1 = {Be,Ce1} e2 = {Be,Ce2} e3 = {Be}Be = Ba different banks. Ba,Bb,Bc,Bd are Interleaved Page-empty Write Example Interleaved Page-empty Read Example Transaction f: WR e0 = {Bf,Rf} f1 = {Bf,Cf1} f2 = {Bf,Cf2} f3 = {Bf} banks. ACT ACT ACT ACT ACT WR WR WR WR WR WR WR WR tRC tRCD-W WR WR WR WR WR ACT WR WR ACT WR WR WR PRE ACT PRE ACT PRE ACT ACT PRE PRE tCC tWRPtCWD WR WR PRE tRP tRR D(c1) ∆tRC T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 ACT ACT ACT ACT ACT ACT RD RD RD RD RD RD RD RD tRC tRCD-R RD RD RD RD RD ACT RD RD ACT RD RD RD PRE ACT PRE ACT PRE ACT ACT tCC tRDP tCAC RD RD tRP tRR PRE tCYCLE tCYCLE The effective tRC time is increased by 4 tCYCLE DQ15..0 DQN15..0 CFM CFMN RQ11..0 (ACT) RQ11..0 (COL) RQ11..0 (PRE) RQ11..0 (ALL) DQ15..0 DQN15..0 CFM CFMN RQ11..0 (ACT) RQ11..0 (COL) RQ11..0 (PRE) RQ11..0 (ALL) Q(a2) Q(a1) Q(b2) Q(b1) Q(c2) Q(c1) D(d2) D(e1) WR WR D(d1) ACT WR WR PRE PRE PRE PRE D(e1) ∆tWRP

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 31 of 76 The previous section described overlapped r ead transactions and overlapped write transactions in isolation. This section will d escribe the interaction of read and write transactions and the spacing required to avoid channel and core resource conflicts. Figure12 shows a timing diagram (top) for the first case, a writ e transaction followed by a read transaction. Two COL packets with WR commands are presented on cycles T0 and T2. The write data packets are presented a time tCWD later on cycles T4 and T6. The device requires a time t ∆WR after the second COL packet with a WR command bef ore a COL packet with a RD command may be presented. Two COL packets with RD comm ands are presented on cycles T 11 and T 13. The read data packets are returned a time t CAC later on cycles T17 and T 19. The time t ∆WR is required for turning around internal bi-directi onal interconnections (insi de the device). This time must be observed regardless of whether the write and read comm ands are directed to same banks or different banks. A gap t WR- BUB,XDRDRAM will appear on the DQ bus between the end of the D(a2) packet and the beginning of the Q(b1) packet (measured at the appropriate packet reference points). The size of this gap can be evaluated by ca lculating the difference between cycles T 2 and T 17 using the two timing paths : tWR-BUB, XDRDRAM = t∆WR + tCAC - tCWD - tCC In this example, the value of t WR-BUB,XDRDRAM is greater than its minimum value of t WR-BUB,XDRDRAM,MIN. The values of t∆WR and tCAC are equal to their minimum values. In the second case, the timing diagram displayed at the bottom of Figure12 illustrates a read transaction followed by a write transaction. Two COL packets with RD commands are presented on cycles T0 and T2. The read data packets are returned a time tCAC later on cycles T6 and T8. The device requires a time t∆RW after the second COL packet with a RD command before a COL packet with a WR command may be presented. Two COL packets with WR commands are presented on cycles T10 and T12. The write data packets are presented a time tCWD later on cycles T 13 and T 15. The time t ∆RW is required for turning around the external DQ bi-directional interconnections (outside the device). This time must be observed regardless w hether the read and write commands are directed to the same banks or different banks. The time t∆RW depends upon four timing parameters. and may be evaluated by calculating the difference between cycles T2 and T13 using the two timing paths : t∆RW + tCWD = tCAC + tCC + tRW-BUB, XDRDRAM or t∆RW = (tCAC - tCWD) + tCC + tRW-BUB, XDRDRAM In this example, the values of t∆RW, tCAC, tCWD, tCC, and tRW-BUB, XDRDRAM are equal to their minimum values. T0 T1 T2 T3 CFM RQ11..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN Transaction a: WR a1 = {Ba,Ca1} a2 = {Ba,Ca2} Transaction b: RD b1 = {Bb,Cb1} b2 = {Bb,Cb2} RD T0 T1 T2 T3 CFM RQ11..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN WR D(b2) tCWD Q(b2) Q(b1) tCACa1 WR tCAC RD tCWD WR D(b1) t∆RW D(a2) Q(a2) RD D(a1) Q(a1) Write/Read Turnaround Example Read/Write Turnaround Example tCYCLE tCYCLE RD WR t∆WR DQ15..0 DQN15..0 DQ15..0 DQN15..0 tRW-BUB,XDRDRAM tCC tCC tWR-BUB,XDRDRAM tCWD tDR Transaction a: WR a1 = {Ba,Ca1} a2 = {Ba,Ca2} Transaction b: RD b1 = {Bb,Cb1} b2 = {Bb,Cb2} Figure 12 : Write/Read Interaction

8.4 Read/Write Interaction

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 32 of 76 Figure 13 shows two timing diagrams that di splay the system-level timing relations hips between the memory component and the memory controller. The timing diagram at the top of the figur e shows the case of a write-read-write co mmand and data at the memory component. In t his case, the timing will be identical to what has already been shown in the previous sections; i,e. with all timing measured at the pins of the memory component. This timing diagram was produced by merging portions of the top and bottom timing diagrams in Figure12. The example shown is that of a single COL packet with a writ e command, followed by a single COL packet with a read command, followed by a second COL packet with a write command. These accesses all assume a page-hit to an open bank. A timing interval t∆WR is required between the first WR command and the RD command, and a timing interval t∆RW is required between the RD command and the second WR command. There is a write data delay tCWD between each WR command and the associated write data packet D. There is a read data delay t CAC between the RD command and the associated read data packet Q. In this example, all timing parameters have assumed their minimum values except tWR-BUB, XDRDRAM. The lower timing diagram in the figure shows the case where ti ming skew is present between the memory controller and the memory component. This skew is the result of the propagation delay of signal wavefronts on the wire carrying the signals. The example in the lower diagram assumes that there is a propagation delay of t PD-RQ along both the RQ wi res and the CFM/CFMN clock wires between the memory controller and the memory component (the value of t PD-RQ used here is 1*t CYCLE). Note that in an actual system the tPD-RQ value will be different for each memory component connected to the RQ wires. In addition, it is assumed that there is a propagation delay t PD-D along the DQ/DQN wires between the memory controller and the memory component (the direction in which write data travels, and it is assumed that there is the same propagation delay tPD-Q along the DQ/DQN wires between the memory component and the memory controller (the direction in which read data travels). The sum of these two propagation delays is also denoted by the timing parameter tPD,CYC = tPD-D + tPD-Q. As a result of these propagation delays, the position of packets will have timing skews that depend upon whether they are measured at the pins of the memory controller or the pins of memory component. For example, the CFM/CFMN signals at the points of the memor y component are tPD-RQ later than at the pins of the memory controller. This is shown by the cycle numbering of the CFM/CFMN signals at the two locations - in this example cycle T1 at the memory controller aligns with cycle T0 at the memory component. All the request packets on the RQ wires will have a t PD-RQ skew at the memory com ponent relative to the memory controller in this example. Because the tPD-D propagation delay of write data matches the tPD-RQ propagation delay of the write command, the controller may issue the write data packet D(a0) relative to the COL pack et with the first write command “WR(a0)” with normal write data d elay tCWD. If the propagation delays between the memo ry controller and memory component were different for the RQ and DQ buses (not shown in this example), the write data delay at the memory controller would need to be adjusted. A propagation delay is seen by the read command - that is, the read command will be delayed by a tPD-RQ skew at the memory compo- nent relative to the memory controller. The memory componet will return the read data packet Q(b0) relative to this read command with the normal read data delay tCAC (at the pins of the memory componet). The read data packet will be skewed by an additional propagation delay of t PD-Q as it travels from the memory component back to the memory controller. The effective read data delay measured between the read command and the read data at the memory controller will be tCAC + tPD-RQ + tPD-Q. tPD-RQ factor is casued by the propagaion delay of the request packets as they travel from memory controller to memory component. The tPD-Q factor is casued by the propagation delay of the read data packets as they travel from memory componet to memory controller. All timing parameters will be equal to their minimum values except tWR-BUB,XDRDRAM (as in the top diagram), and the timing parameters tRW-BUB,XDRDRAM and t∆RW. These will be larger than their minimum values by the amount (tPD,CYC - tPD,CYC,MIN), where tPD,CYC = tPD- D + tPD-Q. This may be seen by evaluating the two timing paths between cycle T9 at th controller and cycle T21 at the XDR DRAM: t∆RW + tPD-RQ + tCWD = tPD-RQ + tCAC + tCC + tRW-BUB,XDRDRAM or t∆RW = (tCAC - tCWD) + tCC + tRW-BUB,XDRDRAM The following relationship was shown for Figure12. t∆RW, MIN = (tCAC - tCWD) + tCC + tRW-BUB, XDRDRAM, MIN or (t ∆RW - t∆RW, MIN) = (tRW-BUB, XDRDRAM - tRW-BUB, XDRDRAM, MIN) In other words, the two timing parameters tRW-BUB,XDRDRAM and t∆RW will change together. The relationship of this change to the propa- gation delay tPD,CYC (=tPD-D + tPD-Q) can be derived by looking at the two timing paths from T15 to T21 at the XDR DRAM: tPD-Q + tCC + tRW-BUB,XIO + tPD-D = tCC + tRW-BUB,XDRDRAM or tRW-BUB,XDRDRAM = tRW-BUB,XIO + tPD-D + tPD-Q or tRW-BUB,XDRDRAM = tRW- BUB,XIO + tPD,CYC In a system with minimum propagation delays: tRW-BUB,XDRDRAM,MIN = tRW-BUB,XIO + tPD,CYC,MIN and since tRW-BUB,XIO is equal to t RW-BUB,XIO,MIN in the both cases, the following is true: (t PD,CYC - tPD,CYC,MIN) = (tRW-BUB,XDRDRAM - tRW-BUB,XDRDRAM,MIN) = (t∆RW - t∆RW,MIN) In other words, the values of the t RW-BUB,XDRDRAM,MIN and t∆RW,MIN timing parameters correspond to the value of t PD,CYC,MIN for the system (this is equal to one t CYCLE). As tPD,CYC is increased from this minimum value, t RW-BUB,XDRDRAM and t∆RW increase from their minimum values by an equivalent amount.

8.5 Propagation Delay

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 33 of 76 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22T8 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Write-Read-Write at XDR DRAM Write-Read-Write at Controller and XDR DRAM tPD-RQ WR WR tPD-Q tPD-D D(a0) D(a0) WR tCYCLE tCYCLE tCYCLE t∆RWt∆WR b0 RD WR WR tDWR b0 RD tPD-RQ RD tPD-D tCWD tCAC D(a0) Q(b0) tCWD D(c0) tCWD tCAC tCWDc0 WR tPD-RQ Q(b0) Q(b0) D(c0) D(c0) a0 = {Ba,Ca0} c0 = {Bc,Cc0} b0 = {Bb,Cb0} DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 XDR DRAM Controller XDR DRAMT-1 tRW-BUB,XIO tCC tRW-BUB,XDRDRAM tCC tDRW w/ tPD-RQ = tPD-Q = tPD-D = 1*tCYCLE tRW-BUB,XDRDRAM tWR-BUB,XDRDRAM tCC (portions of top and bottom timing diagrams of Figure 12 merged) tCC Figure 13 : Propagation Delay Transaction a: WR Transaction b: RD Transaction c: WR a0 = {Ba,Ca0} c0 = {Bc,Cc0} b0 = {Bb,Cb0} Transaction a: WR Transaction b: RD Transaction c: WR Controller RQ DQ RQ DQ XDR DRAM tPD-RQ tPD-D tPD-Q

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 34 of 76 The serial device read transaction in Figure15 begins with the Start[3:0] field. This consists of bits “1100” on the CMD pin. This indicates that the remaining 28 bits constitute a serial transaction. The next two bits are the SCMD [1:0] field. This field contains the serial command, and the bits “10” in the case of a serial device read transaction. The next eight bits are “00” and the SID [5:0] field. This field contains the serial identification of the device being accessed. The next eight bits are the SADR [7:0] field and contain the serial address of the control register being accessed. A single bit “0” follows next. This bit allows one cycle for the access time to the control register and time to turn on the SDO output driver. The next eight bits on the CMD pin are the sequence “00000000”. At the same time, the eight bits on the SDO pin are the SRD [7:0] field. This is the read data that is accessed from the selected control register. Note the output timing convention here: bit SRD [7] is driven from a time tQ,SI,MAX after edge S26 to a time tQ,SI,MIN after edge S27. The bit is sampled in the controller by the edge S27. A final bit “0” is driven on the CMD pin to finish the serial read transaction. A serial forece read is identical except that the contents of the SID [5:0] fiel d in the transaction is ignored and all devices perform the register read. This is used for device testing. Figure16 shows the response of a DR AM to a serial device read transaction when its internal SID [5:0] register field doesn’t match the SID [5:0] field of the transaction. Instead of driving read data from an internal register for cycle edges S 27 through S34 on the SDO output pin, it passes the input data from the SDI input pin to the SDO output pin during this same period. Table 9: SCMD Field Encoding Summary SCMD[1:0] Command DESCRIPTION

00 SDW Serial device write-one device is written, the one whose SID[5:0] register matches the SID[5:0]

field of the transaction. 01 SBW Serial broadcast write - all devices are written, regardless of the contents of the SID [5:0] register and the SID [5:0] transaction field.

10 SDR Serial device read - one device is read, the one whose SID[5:0] register matches the SID[5:0]

field of the transaction. 11 SFR Serial forced read - all devices are read, regardless of the contents of the SID[5:0] register and the SID[5:0] transaction field

9.0 Register Operations

9.1 Serial Transactions

The serial interface consists of five pins. This includes RST, SCK, CMD, SDI and SDO. SDO uses CMOS signaling levels. The other four pins use RSL signaling levels. RST, CMD, SDI and SDO use a timing window which surrounds the falling edge of SCK. The RST pin i s used for initialization. Figure14 and Figure15 show examples of a serial write transaction and a serial read transaction. Each transaction starts on cycle S4 and requires 32 SCK edges. The next serial transaction can begin on cycle S36. SCK does not need to be asserted if there is no transaction.

9.2 Serial Write Transactions

The serial device write transaction in Figure14 begins with the Start [3:0] field. This consists of bits “1100” on the CMD pin. This indicates to the XDR DRAM that the remaining 28 bits constitute a serial transaction. The next two bits are the SCMD[1:0] field. This field contains the serial command, the bits 00 in the case of a serial device write transac- tion. The next eight bits are “00” and the SID[5:0] field. This field contains the serial identification of the device being accessed. The next eight bits are the SADR[7:0] field. This field contains the serial address of the control register being accessed. A single bit “0” follows next. This bit allows one cycle for the access time to the control register. The next eight bits on the CMD pin is the SWD[7:0] field. this is the write data that is placed into the selected control register. A final bit”0” is driven on the CMD pin to finish the serial write transaction. A serial broadcast write is identical except that the contents of the SID[5:0] field in the transaction is ignored and all devices perform the register write. The SDI and SDO pins are not used during either serial write transaction.

9.3 Serial Read Transactions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 36 of 76 Figure17 through Figure42 show the control register in the memory component. The control registers are responsible for configuring the component’s operating mode, for managing power state transactions, for managing refresh, and for managing calibration operations. A control register may contain up to eight bits. Each figure shows defined bits in white and reserved bits in gray. Reserved bi ts must be written as 0 and must be ignored when read. Write-only fields must be ignored when read . Each figure displays the following register information: 1. Register name 2. Register mnemonic 3. Register address (SADR [7:0] value needed to access it) 4. Read-only, write-only or read-write 5. Initialization state 6. Description of each defined register field Figure17 shows the Serial Identific ation register. The register contains the SID [5:0] (serial identification field). This fiel d contains the serial identification value for the deice. The value is compared to the SID[5:0] field of a serial transaction to determine if the serial trans- action is directed to this device. The serial identification value is set during the initialization sequence. Figure18 shows the Configuration Register. It contains three fields. The first is the WIDTH field. This field allows the number of DQ/DQN pins used for memory read and write accesses to be adjusted. T he SLE field enables data to be written into the memory through t he serial interface using the WDSL register. Figure19 shows the Power Management Register. It contains two fields. The first is the PX field. When this field is written with a “1”, the memory component transactions from powerdown to active state. It is usually unnecessary to write a “0” into this field; this is done auto- matically by the PDN command in a COLX packet. The PST field indicates the current power state of the memory component. Figure20 shows the Write Data Serial Load Register. It permits data to be written into memory via the Serial Interface. Figure23 shows the Refresh Bank Control Regi ster. It contains two fields: BANK and MB R. The BANK field is read-write and contai ns the bank address used by self-refresh during the powerdown state. The MBR field controls how many banks are refreshed during each refresh operation. Figure24, Figure25 and Figure26 show different fields of the Refresh Row Register (high, middle and low). This read- write field contains the row address used by self- and auto-refresh. See”Refresh Transactions” on page 42 for more details. Figure28 and Figure29 show the Current Calibration 0 and 1 registers. They contain the CCVALUE0 and CCVALUE1 fields, respectively. These are read-write fields which control the amount of IOL current dr iven by the DQ and DQN pins during a read transaction. Th e Current Calibration 0 Register controls the even-numbered DQ and DQN pins, and the Current Calibration 1 controls the odd-numbered DQ and DQN pins. Figure30 and Figure31 show the Impedance Calibrati on 0 and 1 registers. They contain the ZCVALUE0 and ZCVALUE1 field, respec- tively. These are read-write fields that control the impedance of the on-chip termi nation components in the DQ and DQN pins. Th e Impedance Calibration 0 Register controls the even-numbered DQ and DQN pins, and t he Impedance Calibration 1 controls the odd- numbered DQ and DQN pins. Figure 36 through Figure 41 and Figure 43 shows t he test registers. This in cludes the TEST, DLL, PLL0, PLL1, IFT, DA and PARTn registers. These are used during device testing. They are not to be read or written during normal operation. Figure42 shows the DLY register. This is used to set the value of t CAC and tCWD used by the component. See “Timing Parameters” on page 61. 7 6 5 4 3 2 1 0 Read-only register SID[7:0] resets to 000000002SID[5:0]reserved SID[5:0] - Serial Identification field. This field contains the serial identification value for the device. The value is compared to the SID[5:0] field of a serial transac- tion to determine if the serial transaction is directed to this device. The serial identification value is set during the initializa- tion sequence. Serial Identification Register SADR[7:0]: 00000001 Figure 17 : Serial Identification (SID) Register

9.4 Register Summary

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 42 of 76 Figure44 contains two timing diagrams showing examples of refresh transactions. The top timing diagram shows a single refresh opera- tion. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is received in a ROWP packet on clock edge T0. The REFA command causes the row address ed by the REFr register (REFH/REFM/REFL) to be opened (sensed) and placed in the sense amp array for the bank. Note that the REFA and REFI commands are similar to the AC T command functionally; both specif y a bank address and delay value, and both cause the selected bank to open (to bec ome sensed.). The difference is that the ACT command is accompanied by a row address in the ROWA packet, while the REFA and REFI commands use a row address in the REFr register (REFH/REFM/REFL). After a time t RAS, a ROWP packet with REFP command to bank Ba is pres ented. This causes the bank to be closed (precharged), leaving the bank in the same state as when the refresh transaction began. Note that the REFP command is equivalent to the PRE command functionally; both specify a bank address and delay value, and both cause the selected bank to close (to become precharged). After a time tRP, another ROWP packet with REFA command to bank Bb is presented (banks Ba and Bb are the same in this example). This starts a second refresh cycle. Each refresh transaction requires a total time t RC = tRAS + tRP, but refresh transactions to different banks may be interleaved like normal read and write transactions. Note that refresh transactions always perform full-page activati on, regardless of the setting in the SP1..0 field of the Config uration register. See "Configuration (CFG) Register" on page 37. Also, see "sub-Row (Sub-Page) Sensing" on page 50. Each row of each bank must be refreshed once in every tREF interval. This is shown with the fourth ROWP packet with a REFA command in the top timing diagram.

10.0 Maintenance Operations

10.1 Refresh Transactions

The lower timing diagram in Figure44 represents one way a memory controller might handle refresh maintenance in a real system. A series of eight ROWP packets with REFA commands (except for the last which is a REFI command) are presented starting at edge T0. The packets are spaced with intervals of tRR. Each REFA or REFI command is addressed to a different bank (Ba through Bh) but uses the same row address from the REFr (REFH/REFM/REFL) register. The eighth REFI command uses this address and then increments it so the next set of eight REFA/REFI commands will refresh the next set of rows in each bank. A series of eight ROWP packets with REFP commands are presented effectively at edge T 10 (a time tRAS after the first ROWP packet with a REFA command). The packets are spaced with intervals of t PP. Like the REFA/REFI commands, each REFP command is addressed to a different bank (Ba through Bh). This burst of eight refresh transactions fully utilizes the memory component. However, other read and write transactions may be inter- leaved with the refresh transactions before and after the burst to prevent any loss of bus efficiency. In other words, a ROWA packet with ACT command for a read or write could have been presented at edge T4 (a time tRR before the first refresh transaction starts at edge T0). Also, a ROWA packet with ACT command for a read or write could have been presented at edge T 36 (a time t RR after the last refresh transaction starts at edge T 32). In both cases, the other request packets for t he interleaved read or write accesses (the precharge commands and the read or write commands) could be slotted in among the request packets for the refresh transaction.

10.2 Interleaved Refresh Transaction

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 43 of 76 Figure 44 : Refresh Transactions T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 Transaction a: REF a0 = {Ba,REFR} a1 = {Ba} tCYCLE T24 T25 T26 T27 T28 T29 T30 T31 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47T32 Refresh Transaction Interleaved Refresh Example REFA tRR REFP REFA Transaction b: REF a0 = {Ba,REFR} b1 = {Bb}Bb = Ba tRC REFA REFA REFA tCYCLE REFP REFP REFP REFP REFA REFA REFI REFP REFP REFP REFP REFA REFA REFA REFA REFA REFA REFA REFA REFA REFA tREF tRPtRAS REFA Transaction c: REF c0 = {Bc,REFR} c1 = {Bc}Bc/Rc = Ba/Ra Transaction a: REF a0 = {Ba,REFR} a1 = {Ba} Transaction b: REF b0 = {Bb,REFR} b1 = {Bb} Transaction c: REF c0 = {Bc,REFR} c1 = {Bc} Transaction d: REF d0 = {Bd,REFR} d1 = {Bd} Transaction e: REF e0 = {Be,REFR} e1 = {Be} Ba,Bb,Bc,Bd, Transaction f: REF f0 = {Bc,REFR} f1 = {Bf} Transaction g: REF g0 = {Bd,REFR} g1 = {Bg} Transaction h: REF h0 = {Be,REFR} h1 = {Bh} different banks. Bh are Be,Bf,Bg and REFA Transaction i: REF i0 = {Ba,REFR+1} i1 = {Bi}Bi = Ba This REFI increments REFR DQ15..0 DQN15..0 CFM CFMN RQ11..0 (ACT) RQ11..0 (PRE) RQ11..0 (ALL) DQ15..0 DQN15..0 CFM CFMN RQ11..0 (ACT) RQ11..0 (PRE) RQ11..0 (ALL) DQ15..0 DQN15..0 CFM CFMN RQ11..0 REFP REFP REFP REFP REFP REFP REFP REFP REFA

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 44 of 76 Figure45 shows the calibration transaction diagrams for the XDR DRAM device. There is one calibration operation supported: calibration of the output current level IOL, each DQi and DQNi pin. The output current calibration sequence is shown in the upper diagram. It begins when a period of t CMD-CALC is observed after the last RQ packet (with command “CMD a” in this example). No request packets should be issued in this period. A COLX packet with a “CALC b” command is then issued to start the current calibration sequence. A period of t CALCE is observed after this packet. No request packets should be issued during this period. A COLX packet with a “CALE c” command is then issued to end the current calibration sequence. A period of tCALE-CMD is observed after this packet. No request packets should be issued during this period. The first request packet may then be issued (with command “CMD d” in this example). A second current calibration sequence must be started within an interval of tCALC. In this example. the next COLX packet with a “CALC e” command starts a subsequent sequence. The dynamic termination calibration sequence is shown in the lower diagram. Note that this memory component does not use this sequence; termination calibraion is perform ed during the manufacturing process. Howe ver, the terminati on sequence shown will be issued by the controller for those memory component which do use a periodic calibration mechanism. It begins when a period of tCMD-CALZC is observed after the packet edge T0(with command CMDa in this example). No request packets should be issued in this period. A COLX packet with a CALZ command is then issued at edge T 3 to start the current calibration sequence. A second period of t CALZE is ovserved after this packet. No request packets should be issued during this period. A COLX packet with a CALE command is then issued at dege T6 to end the current calibration sequence. A third period of tCALE-CMD is observed after this pakets. No request packets should be issued during this period. The first r equest pakcet may be issued at e dge T12(with command CMDd in this example). A second current calibration sequence must be started within an interval of t CALZ. In this example, the nex t COLX pakcet with a CALZ command occurs at edge T20. Note that the labels for the CFM clock edges(of the form Ti) are not to scale, and are used to identify events in the diagrams. Figure 45 : Calibration Transactions T0 T1 T2 T3 CFM RQ11..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN Packet a: Any CMD tCYCLE Current Calibration TransactionPacket b: CALC tCALC Termination Calibration Transaction tCALE-CMD, Packet d: Any CMD c CALE e CALC a CMD d CMD T0 T1 T2 T3 CFM RQ11..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN tCYCLE tCALZ tCALE-CMD, c CALE e CALZ a CMD d CMD DQ15..0 DQN15..0 DQ15..0 DQN15..0 RQ11..0 CFM CFMN CFM CFMN RQ11..0 tCALCE, Packet e: CALC Packet c: CALE tCMD-CALC b CALC tCMD-CALZ b CALZ Packet a: Any CMD Packet b: CALZ Packet d: Any CMD Packet e: CALZ Packet c: CALE tCALZE,

10.3 Calibration Transactions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 45 of 76 Figure46 shows power state transition diagrams for the XDR DRAM device. There are two power states in the XDR DRAM: Powerdown and Active. Powerdown state is to be used in applications in which it is necessary to shut down the CFM/CFMN clock signals. In this state, the contents of the storage cells of the XDR DRAM will be retained by an internal state machine which performs periodic refresh operations using the REFB and REFr control registers. The upper diagram shows the sequence needed for Powerdown entry. Prior to starting the sequence, all banks of XDR DRAM must be precharged so they are left in a closed state. Also, all 23 banks must be refreshed using the current value of the REFr registers, and the REFr registers must not be incremented with the REFI command at the end of this special set of refresh transactions. This ensures that no matter what value has been left in the REFB register, no ro w of any bank will be skipped when aut omatic refresh is first sta rted in Powerdown. There may be some banks at the current row value in the REFr registers that are refreshed twice during the Powerdown entry process. After the last request packet (with the command CMDa in the upper diagram of the figure), an interval of t CMD-PDN is observed. No request packets should be issued during this period. A COLX packet with the PDN command is issued after this interval , causing the XDR DRAM to enter Powerdown state after an interv al of tPDN-ENTRY has elapsed (this is the parameter that should be used for calculating the power dissipation of the XDR DRAM). The CFM/ CFMN clock signals may be removed a time t PDN-CFM after the COLX packet with the PD N command. Also, the termination voltage supply may be removed (set to the ground refe rence) from the Vterm pins a time t PDN-CFM after the COLX pakcet with the PDN command. The voltage on the DQ/DQN pins will follow the voltae on the Vterm pins during Powerdonwn entry. When the XDR DRAM is in Power down, an internal frequency source and state machi ne will automatically generate internal refresh transactions. It will cycle through all 23 state combinations of the REFB register. When the largest value is reached and the REFB value wraps around, the REFr register is increment ed to the next value. The REFB and REFr va lues select which bank and which row are refreshed during the next automatic refresh transaction. The lower diagram shows the sequence needed for Powerdown exit. The sequence is star ted with a serial broadcast write (SBW command) transaction using the serial bus of the XDR DRAM. This transaction wr ites the value “00000001” to the Power Management (PM) register (SADR = “00000011”) of all XDR DRAMs connected to the serial bus. This se ts the PX bit of the PM register, causing the XDR DRAMs to return to Active power state. The CFM/CFMN clock signals must be stable a time t CFM-PDN before the end of the SBW transacti on. Also, the termination voltage supply must be restored to its normal operating point (VTERM,DRSL) on the Vterm pins a time tCFM-PDN before the end of the SWB trans- action. The voltage on the DQ/DQN pins will follow the voltage on the Vterm pins during Powerdown exit. The XDR DRAM will enter Active state after an interval of tPDN-EXIT has elapsed from the end of the SBW transaction (this is the param- eter that should be used for calculating the power dissipation of the XDR DRAM). The first request packet may be issued after an interval of tPDN-CMD has elapsed from the end of the SBW transaction, and must contain a “REFA” command in a ROWP packet. In this example, this packet is denoted with the command “REFA 1”. No other request packets should be issued during this tPDN-CMD interval. All “n” banks (in the example, n=23) must be refreshed using the current value of the REFr registers. The “nth” refresh transaction will use a “REFI” command to inrement the REFr register (instead of a “REFR” command). This ensures that no matter what value has been left in the REFB register, no row of any bank will be skipped when normal refresh is restarted in Active state. There may be some banks at the current row value in the REFr registers that are refreshed twice during the Powerdown exit process. Note that during the Powerdown state an internal time source keeps the device refreshed. However, during the t PDN-CMD interval, no internal refresh operations are performed. As a result, an additi onal burst of refresh transacti ons must be issued after the bu rst of “n” transactions described above. This second burst consists of “m” refresh transactions: m = ceiling[23*212*tPDN-CMD/tREF] Where “212” is the number of rows per bank, and “2 3” is the number of banks. Every ”nth” refresh transaction (where n=23) will use a “REFI” command (to increment the REFr register) instead of a “REFA” command.

10.4 Power State Management

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 46 of 76 Figure 46 : Power State Management Transaction a: Last precharge command tCYCLE Powerdown Entry CMD Transaction b: PDN tCMD-PDN Transaction 1: REFA tCYCLE Powerdown Exit Transaction 2: REFA S0 S2 S4 S6 S8 S10 S12 S14 S18 S20 S22 S24 S26 S28 S30 S32 S34 S16 ‘0’ ‘0’ SCMD Power-up transaction tCYC,SCK a PDN tPDN-ENTRY Powerdown State... tCYCLE 1 REFA n REFP ‘1’ ‘1’ ‘0’ ‘0’ Start tPDN-EXIT tPDN-CMD REFA Transaction n: REFI n-1 REFP tPDN-CFM No signal No signal tCFM-PDN ....Powerdown State RST SCK CMD DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 DQ15..0 DQN15..0 CFM CFMN RQ11..0 a PDN b 2 4 3 5 0 1 ‘0’ ‘0’ 2’h0,SID[5:0] 2 4 3 5 0 1 6 7 SWD[7:0] ‘0’ ‘0’ SDI (input) SDO (output) 2 4 3 5 0 1 6 7 SADR[7:0] n-2 REFP n REFI The final REFA/REFI command increments the REFr register Transaction n-1: REFA tPDN-CMD

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 47 of 76 Figure47 shows the topology of the serial interface signals of a XDR DRAM system. The three si gnals RST, CMD, and SCK are trans- mitted by the controller and are receiv ed by each XDR DRAM device along the bus . The signals are terminated to the V TERM supply through termination components at the end farthes t from the controller. The SDI input of the XDR DRAM device furthest from the controller is also terminated to V TERM. The SDO output of each XDR DR AM device is transmitted to t he SDI input of the next XDR DRAM device (in the direction of the controller). This SDO/SDI daisy chain topology continues to the controller, where it ends at the SRD input of the controller. All the serial interface signals are low-true. All the signals use RSL signaling circuits, except for the SDO output which uses CMOS signaling circuits. Figure48 shows the initialization timing of the serial interface for the XDR DRAM [k] device in the system shown above. Prior to initializa- tion, the RST is held at zero. The CMD input is not used here, and should also be held at zero. Note that the inputs are all sampled by the negative edge of the SCK clock input. The SDI input for the XDR DRAM[0] device is zero, and is unknown for the remaining devices. On negative SCK edge S8 the RST input is sampled one. It is sampled one on the next four edges, and is sampled zero on edge S 12 a time tRST-10 after it was first sampled one. The state of the control registers in the XDR DRAM dev ice are set to their reset values after the first edge (S8) in which RST is sampled one. The SDI inputs will be sampled one within a time tRST-SDO,11 after RST is first sampled one in all the XDR DRAMs except for XDR DRAM [0]. XDR DRAM [0]’s SDI input will always be sampled zero. XDR DRAM [k] will see its RST input sampled zero at S12, and will then see its SDI input sampled zero at S16 (after SDI had previously been sampled one). This interval (measured in t CYC,SCK units) will be equal to the index [k] of the XDR DRAM device along the serial interface bus. In this example, k is equal to 4. This is because each XDR DRAM device will drive its SDO output zero around the SCK edge a time t SDI-SDO,00 after its SDI input is sample zero. In other words, the XDR DRAM [0] device will see RST and SDI both sampled zero on the same edge S12 (tRST-SDI,00 will be 0 *tCYC,SCK units), and will drive its SDO to zero around the subsequent edge (S13). The XDR DRAM [1] device will see SDI sampled zero on edge S 13 (tRST-SDI,00 will be 1*tCYC,SCK units), and will drive its SDO to zero around the subsequent edge (S14). The XDR DRAM [2] device will see SDI sampled zero on edge S 14 (tRST-SDI,00 will be 2* tCYC,SCK units), and will drive its SDO to zero around the subsequent edge (S15). XDR DRAM [j] RST CMD SCK SDO SDI XDR DRAM [0] RST CMD SCK SDO SDI XDR DRAM [63] RST CMD SCK SDO SDI Controller RST CMD SCK VTERMFigure 47 : Serial Interface Systems Topology S0 S2 S4 S6 S8 S10 S12 S14 S18 S20 S22 S24 S26 S28 S30 S32 S34 S36 S38 S40 S42 S44 S46S16 S48 tCYC,SCK RST SDI (input) SCK CMD SDO (output) tRST-SDI,00 tRST-SDO,11 tSDI-SDO,00 tRST-10 = k * tCYC,SCK Figure 48 : Initialization Timing for XDR DRAM [k] Device

10.5 Initialization

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 48 of 76 This continues until the last XDR DRAM device drives the SRD input of the controller. Each XDR DRAM device contains a state machine which measures the interval tRST-SDI,00 between the edges in which RST and SDI are both sampled zero, and uses this value to set the SID [5:0] field of the SID (Serial Identification) register. This value allows directed read and write transactions to be made to the individual XDR DRAM devices. Table 10 summarizes the range of the timing parameters used for initialization by the serial interface bus. Table 10 : Initialization Timing Parameters Symbol Parameter Min Max Unit Figure (s) tRST,10 Number of cycles between RST being sampled one and RST being sampled zero 2-t CYC,SCK - tRST-SDO,11 Number of cycles between RST being sampled one and SDO being driven to one 11t CYC,SCK - tRST,SDI,00 Number of cycles between RST being sampled zero (after being sampled one for tRST,10,MIN or more cycles) and SDI being sampled zero. This will be equal to the index [k] of the XDR DRAM device along the serial interface bus 06 3t CYC,SCK - tSDI-SDO,00 Number of cycles between SDI being sampled one (after RST has been sam- pled one for tRST,10,MIN or more cycles and is then sampled zero) and SDO being driven to zero 11t CYC,SCK - tRST-SCK Asynchronous reset interval. 20 - t CYC,SCK -

10.6 XDR DRAM Initialization Overview

[1] Apply voltage to VDD, VTERM, and VREF pins. VTERM and VREF voltages must be less or equal to VDD voltage at all times. Wait a time interval tCOREINIT. Power-on reset circuit in XDR DRAM places XDR DRAM into low-power state. [2] Assert RST, SCK, SDI and CMD to logical zero, Then: - Pulse SCK to logical one, then to logical zero four times. - Assert RST to logical one. Reset circuit places XDR DRAM into low-power state(identical to power-on reset) - Perform remaining initialization sequence in Figure 48. [3] XDR DRAM has valid Serial ID and all registers have default values that are defined in Figure17 through Figure42. [4] Perform broadcast or directed register writes to adjust registers which need a value different from their default value. [5] Perform Powerdown Exit sequence shown in Figure46. This includes the activity from SCK cycle S 0 through the final REFP command. [6] Perform termination/current calibrati on. The CALZ /CALE sequence shown in Figur e 45 is issued 128 times. After this, each sequence is issued once every tCALZ or tCALC interval. [7] Condition the XDR DRAM banks by performing a REFA/REFI activate and REFP precharge operation to each bank eight times. This can be interleaved to save time. The row address for the activa te operation will step through eight successive values of the RE Fr registers. The sequence between cycles T0 and T32 in the Interleaved Refresh Example in Figure 44 could be performed eight times to satisfy this conditioning requirement. The XDR memory system requires a method of deterministically loading pattern data to XDR DRAMs before beginning Receive Timing Calibration (RX TCAL). The method employed by the XDR DRAMs to achieve this is called Write Data Serial Load (WDSL). A WDSL packet sends one-byte of serial data which is serially shifted into a holding register within the XDR DRAM. Initialization software sends a sequence of WDSL packets, each of which shifts the new byte in and advances the sh ifter by 8 positions. In this way, XDR DRAMs of varying widths can be loaded with a single command type. Each sequence of WDSL packets will load one full column of data to the internal holding register of the target XDR DRAM. Depend ing upon the ratio of native device width to pr ogrammed width, there may be more than one sub-column per column. After loading a fu ll column, a series of WR commands will be issued to sequentially trans fer each sub-column of the colu mn to the XDR DRAM core(s), based upon the SC [3:0] bits.

10.7 XDR DRAM Pattern Load with WDSL Register

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 49 of 76 Table 11 : XDR DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4/x2 XDR DRAM, BL = 16) DQ Pins ‘ Core Word WDSL Core Word Load Order x16 x8 x4 x2 x2 x4 x8 x16 WD[n][15:0] SC[3:2] =xx SC[3:2] = 0x SC[3:2] = 1x SC[3:2] = 00 SC[3:2] = 01 SC[3:2] = 10 SC[3:2] = 11 SC[3:1] = 000 SC[3:1] = 001 SC[3:1] = 010 SC[3:1] = 011 SC[3:1] = 100 SC[3:1] = 101 SC[3:1] = 110 SC[3:1] = 111 LOGICAL VIEW OF XDR DRAM Word Written (1 = Written, 0 = Not Written) DQ0 DQ0 DQ0 DQ0 WD[0][15:0] WDSL Word 8 1 1 01 0 0 01 0 0 0 0 0 0 0 DQ1 DQ1 DQ1 DQ1 WD[1][15:0] WDSL Word 7 1 1 01 0 0 01 0 0 0 0 0 0 0 DQ0 DQ2 DQ2 DQ2 WD[2][15:0] WDSL Word 12 1 1 01 0 0 0 01 0 0 0 0 0 0 DQ1 DQ3 DQ3 DQ3 WD[3][15:0] WDSL Word 3 1 1 01 0 0 0 01 0 0 0 0 0 0 DQ0 DQ0 DQ4 DQ4 WD[4][15:0] WDSL Word 10 1 1 0 01 0 0 0 01 0 0 0 0 0 DQ1 DQ1 DQ5 DQ5 WD[5][15:0] WDSL Word 5 1 1 0 01 0 0 0 01 0 0 0 0 0 DQ0 DQ2 DQ6 DQ6 WD[6][15:0] WDSL Word 14 1 1 0 01 0 0 0 0 01 0 0 0 0 DQ1 DQ3 DQ7 DQ7 WD[7][15:0] WDSL Word 1 1 1 0 01 0 0 0 0 01 0 0 0 0 DQ0 DQ0 DQ0 DQ8 WD[8][15:0] WDSL Word 9 1 01 0 01 0 0 0 0 01 0 0 0 DQ1 DQ1 DQ1 DQ9 WD[9][15:0] WDSL Word 6 1 01 0 01 0 0 0 0 01 0 0 0 DQ0 DQ2 DQ2 DQ10 WD[10][15:0] WDSL Word 13 1 01 0 01 0 0 0 0 0 01 0 0 DQ1 DQ3 DQ3 DQ11 WD[11][15:0] WDSL Word 2 1 01 0 01 0 0 0 0 0 01 0 0 DQ0 DQ0 DQ4 DQ12 WD[12][15:0] WDSL Word 11 1 01 0 0 01 0 0 0 0 0 01 0 DQ1 DQ1 DQ5 DQ13 WD[13][15:0] WDSL Word 4 1 01 0 0 01 0 0 0 0 0 01 0 DQ0 DQ2 DQ6 DQ14 WD[14][15:0] WDSL Word 15 1 01 0 0 01 0 0 0 0 0 0 01 DQ1 DQ3 DQ7 DQ15 WD[15][15:0] WDSL Word 0 1 01 0 0 01 0 0 0 0 0 0 01 PHYSICAL VIEW OF XDR DRAM Word Written (1 = Written, 0 = Not Written) DQ0 DQ2 DQ6 DQ14 WD[14][15:0] WDSL Word 15 1 01 0 0 01 0 0 0 0 0 0 01 DQ6 WD[6][15:0] WDSL Word 14 1 1 0 01 0 0 0 0 01 0 0 0 0 DQ2 DQ10 WD[10][15:0] WDSL Word 13 1 01 0 01 0 0 0 0 0 01 0 0 DQ2 WD[2][15:0] WDSL Word 12 1 1 01 0 0 0 01 0 0 0 0 0 0 DQ0 DQ4 DQ12 WD[12][15:0] WDSL Word 11 1 01 0 0 01 0 0 0 0 0 01 0 DQ4 WD[4][15:0] WDSL Word 10 1 1 0 01 0 0 0 01 0 0 0 0 0 DQ0 DQ8 WD[8][15:0] WDSL Word 9 1 01 0 01 0 0 0 0 01 0 0 0 DQ0 WD[0][15:0] WDSL Word 8 1 1 01 0 0 01 0 0 0 0 0 0 0 DQ1 DQ1 DQ1 DQ1 WD[1][15:0] WDSL Word 7 1 1 01 0 0 01 0 0 0 0 0 0 0 DQ9 WD[9][15:0] WDSL Word 6 1 01 0 01 0 0 0 0 01 0 0 0 DQ5 DQ5 WD[5][15:0] WDSL Word 5 1 1 0 01 0 0 0 01 0 0 0 0 0 DQ13 WD[13][15:0] WDSL Word 4 1 01 0 0 01 0 0 0 0 0 01 0 DQ3 DQ3 DQ3 WD[3][15:0] WDSL Word 3 1 1 01 0 0 0 01 0 0 0 0 0 0 DQ11 WD[11][15:0] WDSL Word 2 1 01 0 01 0 0 0 0 0 01 0 0 DQ7 DQ7 WD[7][15:0] WDSL Word 1 1 1 0 01 0 0 0 0 01 0 0 0 0 DQ15 WD[15][15:0] WDSL Word 0 1 01 0 0 01 0 0 0 0 0 0 01 Table 12 : Core Data Word-to-WDSL Formata a. Applies for first generation x16/x8/x4/x2 XDR DRAM with BL=16 DQ Serialization Order CFM/PCLK Cycle Cycle 0 Cycle 1 Symbol (Bit) Time t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Bit Transmitted on DQ pins D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 WDSL Byte/Bit Transfer Order Core Word Core Word WD[n][15:0] WDSL Byte Order WDSL Byte 0 WDSL Byte 1 S W D F i e l d o f S e r i a l P a c k e t 7654321076543210 Bit Transmitted on CMD pin D15 D11 D7 D3 D14 D10 D6 D2 D13 D9 D5 D1 D12 D8 D4 D0

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 50 of 76 The SP[1:0] field of the CFG register controls what fraction of a row is sensed during a ROWA activate operation. This permits the con- troller to reduce the amount of power consumed by normal transactions if a smaller row size can be tolerated by the application. Note that the REFA and REFI activate operations always sense the full row, the SP[1:0] setting does not affect these operations. Refresh operations during Powerdown are likewise unaffected by the SP[1:0] setting. The permissible values of the SP[1:0] field are affected by the value programmed into the WIDTH[2:0] field of the CFG register. The table in the following figure summarizes the allowed combinations of values. In general the value of WIDTH[2:0] is chosen, and this then limits the possible values of SP[1:0] that can be used, as seen by the table in the figure above. In other words, the combi nations indicated by the gray boxes labeled “NO” may not be used, since this would allow accessing of sense amplifier cells with invalid data. If half-row activation is selected (with SP[1:0] = 01), then the value of SR[1] used in the ROWA packet for activation must be the same as the value of SC[1] used in the COL/COLM packet for a read/write access. XDR DRAM device will operate in half-activation mode, even when programmed for quarter-activation (with SP[1:0] = 10). WIDTH[2:0] SP[1:0] 001 010 010 x16 010 full 00 OK OK OK OK half 01 OK NO NO NO Figure 49 Sub-Row Example Allowed combinations of WIDTH[2:0] SP[1:0] SC[3:0] SR[1:0] 000x 001x 00xx 0xxx xxxx 010x 011x 01xx 100x 101x 10xx 1xxx 110x 111x 11xx allowed SC[3:0] values for each WIDTH combination NOTE - for half-activation, the following relationship must be observed : SR[1]=SC[1] allowed SR[1:0] values for each SP[1:0] combination xx 0x,1x

10.8 Sub-Row (Sub-Page) Sensing

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 51 of 76 Figure 50 shows the logic used by the XDR DRAM device when a write-masked command (WRM) is specified in a COLM packet. This masking logic permits individual byte of a write data packet to be written or not written according to the value of an eight bit write mask M [7:0]. In Figure 50, there are 16 sets of 16 bit signals forming the D1[15:0] [15:0] input bus for the Byte Mask block. These are treated as 2 x 16 8-bit bytes: D1 [15] [15.8] D1 [15] [7:0] ... D1 [1] [15:8] D1 [1] [7:0] D1 [0] [15:8] D1 [0] [7:0] The eight bits of each byte is compared to the value in the byte mask field (M[7:0 ]). If they are not equal (NE), then the corr esponding write enable signal (WE) is asserted and the byte is written into the sense amplif ier. If they are equal, then corresponding wr ite enable signal (WE) is deasserted and the byte is not written into the sense amplifier. In the example of Figure 50, a WRM command performs a masked writ e of a 64 byte data packet to all the memory devices connected to the RQ bus (and receiving the command). It is the job of the memory controller to search the 64 bytes to find an eight bit d ata value that is not used and place it into the M [7:0] field. This will always be possible because there are 256 possible 8-bit values and there are only 64 possible values used in the bytes in the data packet. Figure 50 : Byte Mask Logic Byte Mask (WR) S[0][7:0] D1[0][7:0] M[7:0] Compare NE Width Demux (WR) 16x16 16x16 Width Mux (RD) 16x16 S[15:0][15:0] 16x16 D[15:0][15:0] WIDTH[2:0] SC[3:0] WIDTH[2:0] SC[3:0] 4+3 4+3 Q[15:0][15:0] M[7:0] 8 8 D1[0][7:0] S[0][15:8] D1[0][15:8]

8 Compare

D1[0][15:8] D1[15][7:0] D1[15][15:8] S[15][15:8] WE-MSB [15] S[15][7:0] WE-LSB [15] WE-MSB [0] WE-LSB [0]

11.1 Write Masking

11.0 Special Feature Description

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 53 of 76 Figure 54 shows a block diagram of a XDR DRAM in which the banks are divided into tw o sets (called the even bank set and the od d bank set) according to the least-significant bit of the bank addr ess field. This XDR DRAM suppor ts a feature called “Early Read After Write” (hereafter called “ERAW”) The logic that accepts commands on the RQ 11...0 signals is capable of operating these two bank sets independently. In addition, each bank set connects to its own internal “S” data bus (called S0 and S1). The receive interface is able to drive write data onto either of these internal data buses, and the transmit interface is able to sample read data from either of these internal data buses. These capabilities will permit the delay between a write column operation and a read column operation to be reduced, thereby improving performance. Figure 52 shows the timing previously presented in Figure12, but with the activity on the internal S data bus included. The write-to-read parameter t∆WR ensures that there is adequate turnaround time on the S bus between D (a2) and Q (c1). When ERAW is supported with odd and even bank sets, the t∆WR,MIN parameter must be obeyed when the write and read column oper- ations are to the same bank set, but a second parameter t ∆WR-D permits earlier column operations to the opposite bank set. Figure 53 shows how this is possible because there are two internal data buses S0 and S1. In this example, the four columns read operations are made to the same bank Bb, but they could use different banks as long as they all belonged to the bank set that was different fo rm the bank set containing Ba (for the column write operations). T0 T1 T2 T3 CFM RQ11..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN Transaction a: WR a1 = {Ba,Ca1} a2 = {Ba,Ca2} Transaction c: RD c1 = {Bc,Cc1} c2 = {Bc,Cc2} RD tCWD Q(c2) Q(c1) tCACa1 WR D(a2) D(a1) tCYCLE RD WR t∆WR DQ15..0 DQN15..0 tCC tWR-BUB,XDRDRAM S[15:0] [15:0] tCC D(a1) D(a2) Q(c1) Q(c2) turnaround T0 T1 T2 T3 CFM RQ11..0 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 CFMN Transaction a: WR a1 = {Ba,Ca1} a2 = {Ba,Ca2} Transaction b: RD b1 = {Bb,Cb1} b2 = {Bb,Cb2} b3 = {Bb,Cb3} RD tCWD Q(c1) Q(b4) tCACa1 WR D(a2) D(a1) tCYCLE RD WR t∆WR-D DQ15..0 DQN15..0 tCC S0[15:0] [15:0] tCC D(a1) D(a2) Q(b4) Q(c1) S1[15:0] [15:0] Q(b1) Q(b2) Transaction c: RD c1 = {Bc,Cc1} RD RD RD Q(b2) Q(b1) Q(b3) Q(b3) tWR-BUB,XDRDRAM turnaround Bb is in different bank set than Ba Bc is in same bank set as Ba Bank Restrictions b4 = {Bb,Cb4} Figure 52 : Write/Read Interaction - No ERAW Feature Figure 53 : Write/Read Interaction - ERAW Feature

11.2 Multiple Bank sets and the ERAW Feature

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 54 of 76 Figure 54 : XDR DRAM Block Diagram with Bank Sets 1:2 Demux Reg RQ11..0 1:16 Demux 16:1 Mux 16/tCC Bank 0 ACT ... Bank 0 ...

1 R/W

... Bank Array Sense Amp Array ... Width Demux (WR) DQ15..0 DQN15..0 16 16 16 16 16/tCC 16x16*26 16x16 16x16 16x16 16x16 3 3 36 12 (23-2) Bank (23-2) Sense Amp 16x16*26 16x16*26*212 D[15:0][15:0] S0[15:0][15:0] 16x16 16x16 16x16*26 Q[15:0][15:0] Width Mux (RD) Byte Mask (WR) Bank 0 ... Bank 1 1ACT ACT ROW ... Sense Amp Array 16x16*26 16x1616x16 (23-1) Bank (23-1) Sense Amp 16x16*26 16x16*26*212 S1[15:0][15:0] 16x16*26 Odd Even ACT logic PRE logic COL logic decode decode decode ... ... ... ... ... ... WR evenWR odd RD oddRD even ... ... Bank Array

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 55 of 76 When the XDR DRAM supports multiple bank sets as in Figure 54, another feature may be supported, in addition to ERAW. This feature is simultaneous activation, and the timing of several cases is shown in Figure 55. The tRR parameter specifies the minimum spacing between packets with activation commands in XDR DRAMs with a single bank set, or between packets to the same bank set in a XDR DRAM with multiple bank sets. The tRR-D parameter specifies the minimum spacing between packets with activation commands to different bank sets in a XDR DRAM with multiple bank sets. In Figure 55, Case 4 shows an example when both tRR and tRR-D must be at least 4*tCYCLE. In such a case, activation commands to dif- ferent bank sets satisfy the same constraint as activation commands to the same bank set. In Figure 55, Case 2 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 2*tCYCLE. In such a case, an acti- vation command to one bank set may be inserted between two activation commands to a different bank set. In Figure 55, Case 1 shows an example when tRR must be at least 4*tCYCLE and tRR-D must be at least 1*tCYCLE. As in the previous case, an activation command to one bank set may be inserted between two activation commands to a different bank set. In this case, the middle activation command will not be symmetrically placed relative to the two outer activation commands. In Figure 55, Case 0 shows an example when t RR must be at least 4*t CYCLE and tRR-D must be at least 0*t CYCLE. This means that two activation commands may be issued on the same CFM clock edge. This is only possible by using the delay mechanism in one of the two commands. See “Dynamic Request Scheduling” on page 23. In the example shown, the packet with the REFA command is received one cycle before the command with the ACT command, and the REFA command includes a one cycle delay. Both activation commands will be issued internally to different bank sets on the same CFM clock edge. T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 tCYCLE DQ15..0 DQN15..0 CFM CFMN RQ11..0 tRR-D ACT REFA ACT tRR-D Case 4: tRR-D = 4*tCYCLE REFA & ACT have same tRR tRR ACT REFA ACT Case 2: tRR-D = 2*tCYCLE REFA fits between two ACT tRR-D T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 tCYCLE DQ15..0 DQN15..0 CFM CFMN RQ11..0 Case 1: tRR-D = 1*tCYCLE REFA fits between two ACT tRR ACT REFA ACT Case 0: tRR-D = 0*tCYCLE REFA simultaneous with ACT tRR-D tRR ACT REFA ACT tRR-D (REFA uses delay=1*tCYCLE) set different from two ACT note - REFA is directed to bank set different from two ACT note - REFA is directed to bank set different from ACT at T12 note - REFA is directed to bank Figure 55 : Simultaneous Activation — t RR-D Cases

11.3 Simultaneous Activation

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 56 of 76 When the XDR DRAM supports multiple bank sets as in Figure54, another feature may be supported, in addition to ERAW. This feature is simultaneous precharge, and the timing of several cases is shown in Figure56. The tPP parameter specifies the minimum spacing between packets with precharge commands in XDR DRAMs with a single bank set, or between packets to the same bank set in a XDR DRAM with multiple bank sets. The t PP-D parameter specifies the minimum spacing between packets with precharge commands to different bank sets in a XDR DRAM with multiple bank sets. In Figure56, Case4 shows an example when both t PP and t PP-D must be at least 4*t CYCLE. In such a case, precharge commands to different bank sets satisfy the same constraint as precharge commands to the same bank set. In Figure56, Case2 shows an example when t PP must be at least 4*t CYCLE and t PP-D must be at least 2*t CYCLE. In such a case, a precharge command to one bank set may be inserted between two precharge commands to a different bank set. In Figure56, Case1 shows an example when tPP must be at least 4*tCYCLE and tPP-D must be at least 1*tCYCLE. As in the previous case, a precharge command to one bank set may be inserted between two prec harge commands to a different bank set. In this case, the middle precharge command will not be symmetrically placed relative to the two outer precharge commands. In Figure56, Case0 shows an example when t PP must be at least 4*t CYCLE and t PP-D must be at least 0*t CYCLE. This means that two precharge commands may be issued on the same CFM clock edge. This is only possible by using the delay mechanism in one of the two commnads. See “Dynamic Request Scheduling” on page 23. It is also possibly by taking advantage of the fact that two independent precharge commands may be encoded within a single ROWP packet. In the example shown, the ROWP packet contains both a REFP command and a PRE command. Both precharge commands will be issued internally to different bank sets on the same CFM clock edge. T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 tCYCLE DQ15..0 DQN15..0 CFM CFMN RQ11..0 tPP-D PRE REFP PRE tPP-D Case 4: tPP-D = 4*tCYCLE REFP & PRE have same tRR tPP PRE REFP PRE Case 2: tPP-D = 2*tCYCLE REFP fits between two PRE tPP-D T0 T1 T2 T3 T4 T5 T6 T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23T8 tCYCLE DQ15..0 DQN15..0 CFM CFMN RQ11..0 Case 1: tPP-D = 1*tCYCLE REFP fits between two PRE tPP PRE PRE Case 0: tPP-D = 0*tCYCLE REFP simultaneous with PRE tPP-D tPP PRE REFP PRE tPP-D set different from two PRE note - REFP is directed to bank set different from two PRE note - REFP is directed to bank set different from PRE at T12 note - REFP is directed to bank Figure 56 : Simultaneous Precharge — t PP-D Cases REFP

11.4 Simultaneous Precharge

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 57 of 76 Table13 summarizes all electrical conditions (temperature and vo ltage conditions) that may be applied to the memory component. The first section of parameters is concer ned with absolute voltage, storage and operating temperatures, and the power supply, refer ence, and termination voltages. The second section of parameters determines the input voltage levels for the RSL RQ signals. The high and low voltages must satisfy a symmetry parameter with respect to the VREF, RSL. The third section of parameters determines the input voltage le vels for the RSL SI(serial interface) signals. The high and low voltages must satisfy a symmetry parameter with respect to the VREF, RSL. The fourth section of parameters determines the input voltage levels for the CFM clock signals. The high and low voltages are specified by a common-mode value and a swing value. The fifth section of parameters determines the input voltage levels for the write data signals on the DRSL DQ pins. The high and low volt- ages are specified by a common-mode value and a swing value. Table 13 : Electrical Conditions Symbol Parameter Minimum Maximum Unit VIN,ABS Voltage applied to any pin (except VDD) with respect to GND - 0.3 1.5 V VDD,ABS Voltage on VDD with respect to GND - 0.5 2.3 V TSTORE Storage temperature - 50 100 °C TJ Junction temperature under bias during normal operation - 100 °C TMIN Operating Temperature 0 TJ,MAX °C VDD Supply voltage applied to VDD pins during normal operation 1.8 - 0.09 1.8 + 0.09 V VREF,RSL RSL - Reference voltage applied to VREF pina VTERM,RSL - 0.450 - 0.025 VTERM,RSL - 0.450 + 0.025 V VTERM,DRSL DRSL - Termination voltage applied to VTERM pins 1.2 - 0.06 1.2 + 0.06 V VIL,RQ RSL RQ inputs -low voltage VREF,RSL - 0.45 VREF,RSL - 0.15 V VIH,RQ b RSL RQ inputs -high voltage VREF,RSL + 0.15 VREF,RSL + 0.45 V RA,RQ RSL RQ inputs - data asymmetry: RA,RQ = (VIH,RQ-VREF,RSL)/(VREF,RSL-VIL,RQ) 0.8 1.2 V VIL,SI RSL Serial Interface inputs -low voltage VREF,RSL - 0.45 VREF,RSL - 0.20 V VIH,SI b RSL Serial Interface inputs -high voltage VREF,RSL + 0.20 VREF,RSL + 0.45 V RA,SI RSL Serial Interface inputs - data asymmetry: RA,SI = (VIH,RQ-VREF,RSL)/(VREF,RSL-VIL,RQ) 0.8 1.2 V VICM,CFM CFM/CFMN input - common mode: VICM,CTM = (VIH,CFM b+VIL,CTM)/2 b.VIH is typically equal to VTERM,RSL or VTERM,DRSL (whichever is appropriate) under DC conditions in a system. VTERM,DRSL-0.150 VTERM,DRSL-0.075 V VISW,CFM CFM/CFMN input - high-low swing: VISW,CFM = (VIH,CTM b - VIL,CTM) 0.15 0.30 V VICM,DQ DRSL DQ inputs - common mode: VICM,DQ = (VIH,DQ b+VIL,DQ)/2 VTERM,DRSL-0.150 VTERM,DRSL-0.025 V VISW,DQ DRSL DQ inputs - high-low swing: VISW,DQ = (VIH,DQ b - VIL,DQ) 0.05 0.30 V

12.0 Operating Conditions

12.1 Electrical Conditions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 58 of 76 Table14 summarizes all timing conditions that may be applied to the memory component. The first sect ion of parameters is concer ned with parameters for the clock signals. The second section of parameters is concerned with parameters for the request signals. The third section of parameters is concerned with parameters is concerned with parameters for the write data signals. The fourth section of param- eters is concerned with parameters for the serial interface si gnals. The fifth section is concerned with all other parameters, including those for refresh, calibration, power state transitions, and initialization. Table 14 : Timing Conditions Symbol Parameter and Other Conditions Minimum Maximum Units Figure(s) tCYCLE or tCYC,CTM CFM RSL clock - cycle time -4000 -3200 -2400 2.00 2.50 3.33 3.83 3.83 3.83 ns ns ns Figure 57 tR,CFM, tF,CFM CFM/CFMN input - rise and fall time - use minimum for test. 0.08 0.20 tCYCLE Figure 57 tH,CFM, tL,CFM CFM/CFMN input - high and low times 40% 60% tCYCLE Figure 57 tR,RQ, tF,RQ RSL RQ input - rise/fall times (20% - 80%) - use minimum for test. 0.08 0.26 tCYCLE Figure 58 tS,RQ, tH,RQ RSL RQ input to sample points (set/hold) @ 2.50 ns > tCYCLE ≥ 2.00 ns @ 3.33 ns > tCYCLE ≥ 2.50 ns @ 3.83 ns ≥ tCYCLE ≥ 3.33 ns 0.170 0.200 0.275 ns ns ns Figure 58 tIR,DQ, tIF,DQ DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test. 0.020 0.074 tCYCLE Figure 59 tS,DQ, tH,DQ DRSL DQ input to sample points (set/hold) @ 2.50 ns > tCYCLE ≥ 2.00 ns @ 3.33 ns > tCYCLE ≥ 2.50 ns @ 3.83 ns ≥ tCYCLE ≥ 3.33 ns 0.052 0.065 0.080 ns ns ns Figure 59 tDOFF,DQ DRSL DQ input delay offset (fixed) to sample points -0.08 +0.08 tCYCLE Figure 59 tCYC,SCK Serial Interface SCK input - cycle time 20 - ns Figure 61 tR,SCK, tF,SCK Serial Interface SCK input - rise and fall times - 5.0 ns Figure 61 tH,SCK, tL,SCK Serial Interface SCK input - high and low times 40% 60% tCYC,SCK Figure 61 tIR,SI, tIF,SI Serial Interface CMD,RST,SDI input - rise and fall times - 5.0 ns Figure 61 tS,SI,tH,SI Serial Interface CMD,SDI input to SCK clock edge - set/hold time 5 - ns Figure 61 tDLY,SI-RQ Delay from last SCK clock edge for register write to first CFM edge with RQ packet containing a command which uses the value in the register. Also, delay from first CFM edge with RQ packet containing a command which modifies reg- ister value to the first SCK clock edge for register read to this register. 10 - tCYC,SCK - tREF Refresh interval. Every row of every bank must be accessed at least once in this interval with a ROW-ACT, ROWP-REF or ROWP-REFI command. - 16 ms Figure 44 tREFA-REFA,AVG Average refresh command interval. ROWP-REFA or ROWP-REFI commands must be issued at this average rate. This depends upon t REF and the number of banks and the number of rows: tREFI = tREF/(NB*NR) = tREF/(23*211). tREFA-REFA,AVG = 488 ns - NREFA,BURST Refresh burst limit. The number of ROWP-REFA or ROWP-REFI commands which can be issued consecutively at the minimum command spacing. - 128 commands - tBURST-REFA Refresh burst interval. The interval between a burst of NREFA,BURST,MAX ROWP- REFA or ROWP-REFI commands and the next ROWP-REFA or ROWP-REFI command. 40 - tCYCLE - tCOREINIT Interval needed for core initialialization after power is applied. - 1.5 ms - tCALC Current calibration interval - 100 ms Figure 45 tCMD-CALC, tCMD-CALZ Delay between packet with any command and CALC/CALZ packet w/ PRE or REFP command w/ any other command tCYCLE Figure 45 tCALCE, tCALZE Delay between CALC/CALZ packet and CALE packet 12 - tCYCLE Figure 45 tCALE-CMD Delay between CALE packet and packet with any command 24 - tCYCLE Figure 45 tCMD-PDN Last command before PDN entry 16 - tCYCLE Figure 46 tPDN-CFM RSL CFM/CFMN and VTERM stable after PDN entry 16 - tCYCLE Figure 46 tCFM-PDN RSL CFM/CFMN and VTERM stable before PDN exit 16 - tCYCLE Figure 46 tPDN-CMD First command after PDN exit (includes lock time for CFM/CFMN) 4096 - tCYCLE Figure 46

12.2 Timing Conditions

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 59 of 76 Table15 summarizes all electrical paramete rs (temperature, current and voltage) that characterize this memory component. The on ly exception is the supply current values(IDD) under different operating conditions covered in the Supply Current Profile section. The first section of parameters is concerned with the thermal characteristics of the memory component. Ther second section of parameters is concerned with the current needed by the RQ pins and VREF pin. The third section of parameters is concerned with the current needed by the DQ pins and voltage levels produced by the DQ pins when driving read data. This section is also concerned with the current needed by the V TERM pin, and with the resistance levels produced for the internal termination components that attach to the DQ pins. The fourth section of parameters determines the output voltage levels and the current needed for the serial interface signals. Table 15 : Electrical Characteristics Symbol Parameter Minimum Maximum Units ΘJC Junction-to-case thermal resistance 1.7 °C/Watt II,RSL RSL RQ or Serial Interface input current @ ( VIN= VIH,RQ,MAX) -10 10 uA IREF,RSL VREF,RSL current @ VREF,RSL,MAX flowing into VREF pin -10 10 uA VOSW,DQ DRSL DQ outputs - high-low swing: VOSW,DQ=(VIH,DQ-VIL,DQN) or (VIH,DQN-VIL,DQ) 0.200 0.400 V RTERM,DQ DRSL DQ outputs - termination resistance 40.0 60.0 Ω VOL,SI RSL serial interface SDO output - low voltage 0.0 0.25 V VOH,SI RSL serial interface SDO output - high voltage VTERM,RSL - 0.25 VTERM,RSL V In this section, Table16 summarizes the supply current (IDD) that characterizes this memory component. This parameter is shown under different operating conditions. Table 16 : Supply Current Profile Symbol Power State and Steady State Transaction Rates Maximum @tCYCLE= 2.00 ns Maximum @tCYCLE= 2.50 ns Maximum @tCYCLE= 3.33 ns Units x16 x8 x4 x2 x16 x8 x4 x2 x16 x8 x4 x2 IDD,PDN Device in PDN, self-refresh enabled. a a. IDD current @ VDD,MAX flowing into VDD pins 25 25 25 mA IDD,STBY Device in STBY. This is for a device in STBY with no packets on the Channela 330 270 220 mA IDD,ROW ACT command every tRR, PRE command every tPP .a 720 600 480 mA IDD,WR ACT command every tRR, PRE command every tPP, WR command every tCC. a 1260 1100 990 940 1050 910 830 800 850 740 670 640 mA IDD,RD ACT command every tRR, PRE command every tPP, RD command every tCC. a,b b.This does not include the IOL,DQ sink current. The device dissipates IOL,DQ•VTERM,DQ in each DQ/DQN pair when driving data. 1500 1360 1270 1210 1300 1200 1100 1000 1050 980 900 820 mA ITERM,DRSL,RD RD command every tCC. c c. ITERM,DRSL current @ VTERM,DQ,MAX flowing into VTERM pins 170 90 40 20 170 90 40 20 170 90 40 20 mA ITERM,DRSL,WR WR command every tCC. c 100 50 30 15 100 50 30 15 100 50 30 15 mA

13.0 Operating Characteristics

13.1 Electrical Characteristics

13.2 Supply Current Profile

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 60 of 76 Table 17 summarizes all timing parameters that characterize this memory component. The only exceptions are the core timing parame- ters that are speed-bin dependent. Refer to the Timing Parameters section for more information. The first section of parameters pertains to the timing of the DQ pins when driving read data. The second section of parameters is concerned with the timing for the serial interface signals when driving register read data. The third section of parameters is concerned with the time intervals needed by the interface to transition between power states. Table 17 : Timing Characteristics Symbol Parameter and Other Conditions Minimum Maximum Units Figure(s) tQ,DQ DRSL DQ output delay (variation across 16 Q bits on each DQ pin) from drive points - output delay @ 2.50 ns > t CYCLE ≥ 2.00 ns @ 3.33 ns > tCYCLE ≥ 2.50 ns @ 3.83 ns ≥ tCYCLE ≥ 3.33 ns -0.052 -0.065 -0.080 +0.052 +0.065 +0.080 ns ns ns Figure 60 tQOFF,DQ DRSL DQ output delay offset (a fixed value for all 16 Q bits on each DQ pin) from drive points - output delay 0.00 +0.20 tCYCLE Figure 60 tOR,DQ, tOF,DQ DRSL DQ output - rise and fall times (20%-80%). 0.02 0.04 tCYCLE Figure 60 tQ,SI Serial SCK-to-SDO output delay @ CLOAD,MAX = 15 pF 2 15 ns Figure 62 tP,SI Serial SDI-to-SDO propagation delay @ CLOAD,MAX = 15 pF - 15 ns Figure 62 tOR,SI, tOF,SI Serial SDO output rise/fall (20%-80%) @ CLOAD,MAX = 15 pF - 10 ns Figure 62 tPDN-ENTRY Time for power state to change after PDN entry - 16 tCYCLE Figure 46 tPDN-EXIT Time for power state to change after PDN exit 0 - tCYCLE Figure 46

13.3 Timing Characteristics

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 61 of 76 Table18 summarizes the timing parameters that characterize the core logic of this memory component.. These timing parameters will vary as a function of the component’s speed bin. The four sections deal with the timing intervals between packets with, respectively, row- row commands, row-column commands, column-column commands, and column-row commands. Table 18 : Timing Parameters Symbol Parameter and Other Conditions Min (A) Min (B) Min (C) Units Figure(s) tRC Row-cycle time: interval between successive ROWA- ACT or ROWP-REFA or ROWP-REFI activate com- mands to the same bank. tRC tRC-R, 2tCC = tRCD-R + tCC+ tRDP + tRP a tRC-W, 2tCC, noERAW = tRCD-W + tCC+ tWRP +tRP a tRC-W, 2tCC, ERAW = tRCD-W + tCC+ tWRP + tRP a a. The tRC,MIN parameter is applicable to all transaction types (read, write, refresh, etc.). Read and write transactions may have an additional limitation, depending upon how many column accesses (each requiring tCC) are performed in each row access (tRC). The table lists the special cases (tRC-R, 2tCC, tRC-W, 2tCC, noERAW, tRC-W, 2tCC, ERAW) in which two column accesses are performed in each row access. Note that tRC-W, 2tCC, ERAW uses a relaxed value of tRCD-W that is equal to tRCD-R,MIN. All other parameters are minimum. tCYCLE Figure 4 - Figure 7 tRAS Row-asserted time: interval between a ROWA-ACT or ROWP-REFA or ROWP-REFI activate command and a ROWP-PRE or ROWP-REFP precharge command to the same bank. Note that tRAS,MAX is 64 us for all timing bins. 10 13 17 tCYCLE Figure 4 - Figure 7 tRP Row-precharge time: interval between a ROWP-PRE or ROWP-REFP precharge command and a ROWA- ACT or ROWP-REFA or ROWP-REFI activate command to the same bank. 6 7 7 tCYCLE Figure 4 - Figure 7 tPP Precharge-to-precharge time: interval between suc- cessive ROWP-PRE or ROWP-REFP precharge com- mands to different banks. tPP tPP-D b b. tPP-D is the tPP parameter for precharges to different bank sets. See “Simultaneous Precharge” on page 56. tCYCLE Figure 4 - Figure 7 tRR Row-to-row time: interval between ROWA-ACT or ROWP- REFA or ROWP-REFI activate commands to different banks. tRR tRR-D c c. tRR-D is the tRR parameter for activates to different bank sets. See “Simultaneous Activation” on page 55. tCYCLE Figure 4 - Figure 7 tRCD-R Row-to-column-read delay: interval between a ROWA-ACT activate command and a COL-RD read com- mand to the same bank. 5 7 7 tCYCLE Figure 4 - Figure 7 tRCD-W Row-to-column-write delay: interval between a ROWA-ACT activate command and a COL-WR or COL- WRM write command to the same bank. 1 3 3 tCYCLE Figure 4 - Figure 7 tCAC Column access delay: interval from COL-RD read command to Q read data 6 7 7 tCYCLE Figure 10 tCWD Column write delay: interval from a COL-WR or COLM-WRM write command to D write data. 3 3 3 tCYCLE Figure 9 tCC Column-to-column time: interval between successive COL-RD commands, or between successive COL- WR or COLM-WRM commands. 2 2 2 tCYCLE Figure 4 - Figure 7 tRW-BUB, XDRDRAM Read-to-write bubble time: interval between the end of a Q read data packet and the start of D write data packet (the end of a data packet is the time interval tCC after its start). 3 3 3 tCYCLE Figure 13 tWR-BUB, XDRDRAM Write-to-read bubble time: interval between the end of a D writed data and the start of Q read data packet (the end of a data packet is the time interval t CC after its start). 3 3 3 tCYCLE Figure 13 t∆RW Read-to-write time: interval between a COL-RD read command and a COL-WR or COLM-WRM write com- mand.d d. See “Propagation Delay” on page 32. 8 9 9 tCYCLE Figure 12 t∆WR Write-to-read time: interval between a COL-WR or COLM-WRM write command and a COL-RD read com- mand. t∆WR t∆WR-D e e. t∆WR-D is the t∆WR parameter for write-read accesses to different bank sets. See “Multiple Bank Sets and the ERAW Feature” on page 53. Also, note that the value of 2 tCYCLE Figure 12 tRDP Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE precharge com- mand to the same bank. 3 4 4 tCYCLE Figure 4 - Figure 7 tWRP Write-to-precharge time: interval between a COL-WR or COLM-WRM write command and a ROWP-PRE precharge command to the same bank. 10 12 12 tCYCLE Figure 4 - Figure 7 tDR Write data-to-read time: interval between the start of D write data and a COL-RD read command to the same bank. 6 7 7 tCYCLE Figure 12 tDP Write data-to-precharge time: interval between D write data and ROWP-PRE precharge command to the same bank. 7 9 9 tCYCLE Figure 9 tLRRn-LRRn Interval between ROWP-LRRn command and a subsequent ROWP-LRRn command. f f.ROWP-LRRn includes the commands {ROWP-LRR0,ROWP-LRR1,LOWP-LRR2}, ROWP-REFx includes the commands {ROWP-REFA,ROWP-REFI, LOWP-R EFP}, 16 20 24 tCYCLE Table5 tREFx-LRRn Interval between ROWP-REFx command and a subsequent ROWP-LRRn command. 16 20 24 tCYCLE Table5 tLRRn-REFx Interval between ROWP-LRRn command and a subsequent ROWP-REFx command. 16 20 24 tCYCLE Table5

13.4 Timing Parameters

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 62 of 76 Figure57 shows a timing diagram for the CFM/CFMN clock pins of the memory component. This diagram represents a magnified view of these pins. This diagram shows only one clock cycle. CFM and CFMN are differential signals: one signal is the complement of the other. They are also high-true signals - a low voltage repre- sents a logical zero and a high voltage represents a logical one. There are two crossing points in each clock cycle. The primary crossing point includes the high-voltage-to-low-voltage transition of CFM (indicated with the arrowhead in the diagram). The secondary c rossing point includes the low-voltage-to-high-volt age transition of CFM. All timing events on the RSL signals are referenced to the fi rst set of edges. Timing events are measured to and from the crossing point of the CFM and CFMN signals. In the timing diagram, this is how the c lock- cycle time (tCYCLE or tCYC, CFM), clock-low time (tL, CFM) and clock-high time (tH, CFM) are measured. Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tR, CFM) and fall time (tF, CFM) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VIL, CFM + 0.2*(VIH, CFM - VIL, CFM) 80% = VIL, CFM + 0.8*(VIH, CFM - VIL, CFM) CFM CFMN tCYCLE or tCYC,CFM tR,CFM 80% 20% VIH,CFM VIL,CFM logic 0 logic 1tL,CFM tH,CFM tF,CFM Figure 57 : Clocking Waveforms

14.0 Receive/Transmit Timing

14.1 Clocking

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 63 of 76 Figure58 shows a timing diagram for the RQ11...0 request pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycle (CFM and CFMN are the clo ck signals). Timing events are measured to and from the primary CF M/ CFMN crossing point in which C FM makes its high-voltage-to-low-voltage transition. The RQ11...0 signals are low- true: a high v oltage represents a logical zero and a low voltage represents a logical one. Timing events on the RQ11... 0 pins are measured to and from the point that the signal reaches the level of the reference voltage VREF, RSL. Because timing intervals are measured in this fashion, it is nec essary to constrain the slew rate of the signals. The rise (tR, RQ) and fall time (tF, RQ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VIL, RQ + 0.2*(VIH, RQ - VIL, RQ) 80% = VIL, RQ + 0.8*(VIH, RQ - VIL, RQ) There are two data receiving windows defined for each RQ11...0 signal. The first of these (labeled “0”) and a set time, tS,RQ, and a hold time, tH,RQ, measured around the primary CFM/CFMN crossing point. The second (labeled “1”) has a set time (tS, RQ) and a hold time (tH, RQ) measured around a point 0.5*tCYCLE after the primary CFM/CFMN crossing point. tS,RQ CFM CFMN RQ0 tH,RQ tCYCLE RQ11 ... 80% 20% tR,RQ VIH,RQ VIL,RQ logic1 logic 0 VREF,RSL [1/2]•tCYCLE 0 1 tS,RQ tH,RQ tF,RQ tS,RQ tH,RQ 80% 20% tR,RQ VIH,RQ VIL,RQ logic 1 logic 0 VREF,RSL [1/2]•tCYCLE 0 1 tS,RQ tH,RQ tF,RQ Figure 58 : RSL RQ Receive Waveforms

14.2 RSL RQ Receive Timing

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 64 of 76 Figure59 shows a timing diagram for receiving write data on the DQ/DQN data pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles are shown (CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its high-vo ltage-to-low -voltage transition. The DQ15...0/ DQN15...0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical one. They are also differ- Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (tIR, DQ) and fall time (tIF, DQ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VIL, DQ + 0.2*(VIH, DQ - VIL, DQ) 80% = VIL, DQ + 0.8*(VIH, DQ - VIL, DQ) 0/DQN15... 0 pin pairs). The tDOFF,DQi parameter determines the time between the primary CFM/CFMN crossing point and the offset point for the DQi/DQNi pin pair. The 16 receiving windows are placed at times tDOFF,DQi + (j/8)*tCYCLE (the index “j” may take on the values {0, 1, .. , 15} and refers to each of the receiving windows for the DQi/DQNi pin pair). The offset values tDOFF,DQi for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained to lie inside the range {tDOFF,MIN, tDOFF,MAX}. Furthermore, each offset value t DOFF,DQi is static and will not change duri ng system operation. Its value can be determined at initialization. The 16 receiving windows (j = 0 ... 15) for the first pair DQ0/DQN0 are labeled “0” through “15”. Each window has a set time (tS, DQ) and a hold time (tH, DQ) measured around a point tDOFF,DQ0 + (j/8) *tCYCLE after the primary CFM/CFMN crossing point. The 16 receiving windows (j = 0 ... 15) for the each of the other pairs DQi/DQNi are also labeled “0” through “15”. Each window has a set time (tS, DQ) and a hold time (tH, DQ) measured around a point tDOFF,DQi + (j/8)*tCYCLE after the primary CFM/CFMN crossing point.

14.3 DRSL DQ Receive Timing

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 65 of 76 tS,DQ CFM CFMN [(j)/8]•tCYCLE DQ0 DQN0 tDOFF,DQ0 1 20 5 63 4 j 14 15 tH,DQ tCYCLE DQi DQNi tDOFF,DQi 1 20 5 63 4 j 14 15 DQ15 DQN15 tDOFF,DQ15 1 20 5 63 4 j 14 15 tDOFF,MIN tDOFF,MAX VIH,DQ VIL,DQ logic 0 logic 1 ... tS,DQ [(j)/8]•tCYCLE tH,DQ tS,DQ [(j)/8]•tCYCLE tH,DQ tIF,DQtIR,DQ tIF,DQtIR,DQ 80% 20% tIF,DQtIR,DQ VIH,DQ VIL,DQ logic 0 logic 1 80% 20% VIH,DQ VIL,DQ logic 0 logic 1 80% 20% Figure 59 : DRSL DQ Receive Waveforms

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 66 of 76 diagram represents a magnified view of thes e pins and only a few clock cycles are sh own (CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/CFMN crossing point in whic h CFM makes its high-voltage-to-low-voltage pair crosses. Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (tOR, DQ) and fall time (tOF, DQ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VOL, DQ + 0.2*(VOH, DQ - VOL, DQ) 80% = VOL, DQ + 0.8*(VOH, DQ - VOL, DQ) 0/DQN15...0 pin pairs). The tQOFF,DQi + tQ,DQ,MAX expression determines the time bet ween the primary CFM/CFMN crossing point and the offset point for the DQi/DQNi pin pair. The offset values tQOFF,DQi for each of the 16 DQi/DQNi pin pairs can be different . However, each is constrained to lie inside the range {tQOFF,MIN, tQOFF,MAX}. Furthermore, each offset value tQOFF,DQi is static; its value will not change during system operation. Its value can be determined at initialization time. The 16 transmit windwos (j = 0 ... 15} for the first pair DQ0/ DQN0 are labeled “0” through “15”. Each window begins at the time (tQOFF,DQ0 + tQ,DQ,MAX +((j+0.5)/8)*tCYCLE) and ends at the time (tQOFF,DQ0 + tQ,DQ,MIN +((j+1.5)/8)*tCYCLE) measured after the primary CFM/CFMN crossing point. The 16 transmit windwos (j = 0 ... 15} for the other pair DQi/DQ Ni are also labeled “0” through “15”. Each window begins at the time (tQOFF,DQi + tQ,DQ,MAX +((j+0.5)/8)*tCYCLE) and ends at the time (t QOFF,DQi + tQ,DQ,MIN +((j+1.5)/8)*tCYCLE) measured after the primary CFM/CFMN crossing point. Note that when no read data is to be transmitted on the DQ/DQN pins(and no other component is transmitting on the external DQ/DQN wires), then the voltage level on the DQ/DQN pins will follow the voltage reference value VTERM,DRSL on the VTERM pin. The logical value of each DQ/DQN pin pair in this no-drive state will be “1/1”; when read data is driven, each DQ/DQN pin pair will have either the logical value of “1/0” or “0/1”.

14.4 DRSL DQ Transmit Timing

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 67 of 76 Figure 60 : RSL DQ Transmit Waveforms tQ,DQ,MAX CFM CFMN [(j+0.5)/8]•tCYCLE DQ0 DQN0 tQOFF,DQ0 2 30 1 7 84 6 j 14 15 [(j-0.5)/8]•tCYCLE tQ,DQ,MIN tCYCLE tQ,DQ,MAX [(j+0.5)/8]•tCYCLE DQi DQni tQOFF,DQi 2 30 1 6 74 5 j 14 15 [(j-0.5)/8]•tCYCLE tQ,DQ,MIN tQ,DQ,MAX [(j+0.5)/8]•tCYCLE DQ15 DQN15 tQOFF,DQ15 2 30 1 6 74 5 j 14 15 [(j-0.5)/8]•tCYCLE tQ,DQ,MIN tQOFF,MIN tQOFF,MAX 80% 20% logic “0” logic “1” ... VOH,DQ VOL,DQ tOF,DQtOR,DQ tOF,DQtOR,DQ tOF,DQtOR,DQ 80% 20% logic “0” logic “1” VOH,DQ VOL,DQ 80% 20% logic “0” logic “1” VOH,DQ VOL,DQ

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 68 of 76 Figure61shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the pins only a few clock cycles. The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logic al one. Timing events are measured to and from the V REF,RSL level. Because timing intervals are measur ed in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (tR,SCK and tRI,SI) and fall time (tF,SCK and tIF,SI) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VIL,SI + 0.2 *(VIH,SI - VIL,SI) 50% = VIL,SI + 0.5 *(VIH,SI - VIL,SI) 80% = VIL,SI + 0.8 *(VIH,SI - VIL,SI) There is one receiving window defined for each serial interface signal (RST, CMD and SDI pins). This window has a set time (tS, RQ) and a hold time (tH, RQ) measured around the falling edge of the SCK clock signal. SCK tCYC,SCK 80% 20% tIR,SI VIH,SI VIL,SI logic 1 logic 0 VREF,RSL tS,SI tH,SI tIF,SI 80% 20% VIH,SI VIL,SI logic 1 logic 0 VREF,RSL tL,SCK tH,SCK tF,SCK tR,SCK RST CMD SDI Figure 61 : Serial Interface Receive Waveforms

14.5 Serial Interface Receive Timing

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 69 of 76 Figure62 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles are shown. The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logic al one. Timing events are measured to and from the V REF,RSL level. Because timing intervals are measur ed in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (t OR,SI) and fall time (t OF,SI) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = VOL,SI + 0.2*(VOH,SI - VOL,SI) 50% = VOL,SI + 0.5*(VOH,SI - VOL,SI) 80% = VOL,SI + 0.8*(VOH,SI - VOL,SI) There is one transmit window defined for the serial interface data signal (SDO pins). This window has a maximum delay time (tQ, SI,MAX) from the falling edge of the SCK clock signal and a minimum delay time (tQ,SI,MIN) from the next falling edge of the SCK clock signal. When the memory component is not selected during a serial device read transaction, it will simply pass the information on the SDI input to the SDO output. This combinational propagation delay parameter is t P,SI. The tCYC,SCK will need to be increased during a serial read transaction (relative to the tCYC,SCK value for a serial write transaction) because of the accumulated propagation delay through all of the XDR DRAM devices on the serial interface. During Initialization, when the serial identification is det ermined, the SDI-to-SDO path is registered, so the t CYC,SCK value can be set to the same value as for serial write transactions. See “Initialization” on page 47. Figure 62 : Serial Interface Transmit Waveforms SCK tCYC,SCK 80% 20% VIH,SI VIL,SI logic 1 logic 0 VREF,RSL tL,SCK tH,SCK tF,SCK tR,SCK 80% 20% tOR,SI VOH,SI VOL,SI logic 1 logic 0 VREF,RSL tQ,SI,MAX tQ,SI,MIN tOF,SI 80% 20% VIH,SI VIL,SI logic 1 logic 0 VREF,RSL SDI tP,SI SDO Combinational propagation from SDI to SDO when the device is not selected during a serial device read transaction.

14.6 Serial Interface Transmit Timing

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 70 of 76 Table19 summarizes inductance, capacitance, and resistance values associated with each pin gr oup for the memory component. Most of the parameters have maximum values only, however some have both maximum and minimum values. The first group of parameters are for the CFM/CFMN clock pair pins. They include inductance, capacitance, and resistance values. The second group of parameters are for the RQ request pins. They include inductance, mutual inductance, capacitance, and resistance values. There are also limits on the spread in inductance and capacitance values allowed in any one memory component. The third group of parameters are specific to the DQ data pins and include inductance, mutual inductance, capacitance, and resistance values. There are limits on the spread in inductance and capacitance values allowed in any one memory component. The fourth group of parameters are for the serial interface pins. They include inductance and capacitance values. Table 19 : Package RSL Parasitic Summary a. This is the effective die input capacitance, and does not include package capacitance. b. CFM/RQ/SI should include package capacitance/Impedance, only DQ deos not include pacage capacitance. This value is a combina- tion of the device I/O circuitry and package capacitance&inductance Symbol Parameter and Other Conditions Minimum Maximum Units LVTERM VTERM pin - effective input inductance per four bits - 2.2 nH LI ,CFM CFM/CFMN pins - effective input capacianceb - 5.0 nH CI ,CFM CFM/CFMN pins - effective input capacianceb 1.8 2.4 pF RI ,CFM CFM/CFMN pins - effective input resistance 4 18 Ω LI ,RQ RSL RQ pins - effective input inductanceb - 5.0 nH CI ,RQ RSL RQ pins - effective input capacitanceb 1.8 2.4 pF RI ,RQ RSL RQ pins - effective input resistance 4 18 Ω L12,RQ Mutual inductance between adjacent RSL RQ signals - 0.6 nH ∆LI,RQ Difference in LI,RQ between any RSL RQ pins of a single device - 1.8 nH ∆CI,RQ Difference in CI between CFM/CFMN average and RSL RQ pins of single device -0.12 +0.12 pF ZPKG,DQ DRSL DQ pins - package differential impednce note - package trace length should be less than 10mm long. 70 130 Ω CI ,DQ DRSL DQ pins - effective input capacitancea - 1.8 pF ∆CI,DQ Difference in CI between DQi and DQNi of each DRSL paira - 0.06 pF RI ,DQ DRSL DQ pins - effective input resistance 4 25 Ω LI ,SI Serial Interface effective input inductance - 8.0 nH CI ,SI Serial Interface effective input capacitance RST, SCK, CMD SDI,SDO 1.7 3.0 7.0 pF pF

15.0 Package Description

15.1 Package Parasitic Summary

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 71 of 76 GND Pin SCK,CMD,RST Pin Pad LI,SI CI,SI GND Pin RQ Pin Pad LI,RQ RI,RQ CI,RQ RQ Pin L12,RQ RQ Pin L12,RQ CFM Pin GND Pin GND Pin DQ Pin Pad RI,DQ CI,DQ Pad RI,DQ CI,DQ DQN Pin ZPKG,DQ/2 ZPKG,DQ/2 Pad RI,CFM CI,CFM Pad RI,CFM CI,CFM ZPKG,CFM/2 ZPKG,CFM/2 CFMN Pin SDI,SDO Pin Figure 63 : Equivalent Circuits for Package Parasitic

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 72 of 76 0.80 2.00 12345678910111213141516 12.00 14.00 ± 0.10 12.70 14.50 ± 0.10 A B C D E F G H J K L #A1 INDEX MARK 104- ∅0.45 Solder ball

0.2 M AB

1.27 14.00 ± 0.10 14.50 ± 0.10 #A1 1.03 ± 0.10 0.35 ± 0.05

0.10 MAX

(Datum B) MOLDING AREA (Datum A) ( Post reflow 0.50 + 0.05 ) A B 1.27

15.2 Package Dimensions (104-Ball FBGA) (Unit : mm)

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 73 of 76 Table of Contents

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 75 of 76 List of Figures

Rev. 1.1 August 2006 K4Y50024UC XDRTM DRAM K4Y50044UC K4Y50084UC K4Y50164UC 76 of 76 Copyright © Dec. 2005, Samsung Electronics. All rights reserved. Rambus and Rambus logo are trademarks or registered trademarks of Rambus Inc. XDR is a trademark of Rambus Inc. in the United States and other countries. This document contains advanced information that is subject to change by Samsung Electronics without notice Document Version 1.0ver. Samsung Electronics Co. Ltd. San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do, KOREA Telephone: 82-31-208-6366 Fax: 82-31-208-6799 http://www.intl.samsungsemi.com