K4X1G163PC-L

K4X1G163PC-L SAMSUNG | Alldatasheet

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K4X1G163PC - L(F)E/G - 4 - Mobile DDR SDRAM November 2007 64Mx16 Mobile DDR SDRAM 1. FEATURES

• VDD/VDDQ = 1.8V/1.8V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK
• MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave)
• EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
• Internal Temperature Compensated Self Refresh
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• LMD, UMD for write masking only.
• Auto refresh duty cycle - 7.8us for -25 to 85 °C 2. Operating Frequency NOTE: 1) CAS Latency 3. Address configuration - DM is internally loaded to match DQ and DQS identically. 4. Ordering Information - L(F)E : 60FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C) - L(F)G : 60FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C) - C6/C3 : 166MHz(CL=3) / 133MHz(CL=3) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMS UNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTH- ING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICEN SE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, crit ical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. DDR333 DDR266 Speed @CL21) 83Mhz 83Mhz Speed @CL31) 166Mhz 133Mhz Organization Bank Address Row Address Column Address 64Mx16 BA0,BA1 A0 - A13 A0 - A9 Part No. Max Freq. Interface Package K4X1G163PC-L(F)E/GC6 166MHz(CL=3),83MHz(CL=2) LVCMOS 60FBGA Pb (Pb Free)K4X1G163PC-L(F)E/GC3 133MHz(CL=3),83MHz(CL=2)

K4X1G163PC - L(F)E/G - 5 - Mobile DDR SDRAM November 2007 5. FUNCTIONAL BLOCK DIAGRAM Bank Select Timing Register DM Input Register Address Register Refresh Counter Row Buffer Row DecoderCol. Buffer Data Input Register Serial to parallel 16Mx16 16Mx16 16Mx16 16Mx16 Sense AMP 2-bit prefetch Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Strobe Gen. CK, CK ADD LCKE CK, CK CKE CS RAS CAS WE LCAS LRAS LCBR LWE LWCBR LRAS LCBR CK, CK 32 16 LDM X16 DQi Data Strobe DM LDM LWE

K4X1G163PC - L(F)E/G - 6 - Mobile DDR SDRAM November 2007 6. Package Dimension and Pin Configuration Ball Name Ball Function CK, CK System Differential Clock CS Chip Select CKE Clock Enable A0 ~ A13 Address BA0 ~ BA1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DM Data Input Mask L(U)DQS Data Strobe DQ0 ~ 15 Data Input/Output VDD/VSS Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground < Bottom View*1 > 60Ball(6x10) FBGA 123789 AV SS DQ15 V SSQ VDDQ DQ0 V DD BV DDQ DQ13 DQ14 DQ1 DQ2 V SSQ CV SSQ DQ11 DQ12 DQ3 DQ4 V DDQ DV DDQ D Q 9D Q 1 0D Q 5 D Q 6 V SSQ EV SSQ UDQS DQ8 DQ7 LDQS V DDQ FV SS UDM N.C. A13 LDM V DD GC K E C KC K WE CAS RAS HA 9 A 1 1 A 1 2 C S BA0 BA1 J A 6A 7A 8 A 1 0 / A P A 0A 1 KV SS A4 A5 A2 A3 V DD < Top View*2 > F E D C B J H G A K 63 174 598 2 e D E < Top View*2 > *2: Top View *1: Bottom View Symbol Min Typ Max A- - 1 . 0 A1 0.25 - - E 10.9 11.0 11.1 E1 -6 . 4- D 11.4 11.5 11.6 D1 -7 . 2- e - 0.80 - b 0.45 0.50 0.55 z-- 0 . 1 0 [Unit:mm] z A b #A1 Ball Origin Indicator K4X1G163PC-XXXX SAMSUNG Week

K4X1G163PC - L(F)E/G - 7 - Mobile DDR SDRAM November 2007 7. Input/Output Function Description Symbol Type Description CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the cross- ing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK. CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deacti vates internal clock signals, and device input buff- ers and output drivers. Taking CKE LOW pr ovides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are contrived for low standby power con- sumption. CS Input Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external b ank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs : RAS , CAS and WE (along with CS) define the command being entered. LDM,UDM Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. BA0, BA1 Input Bank Addres Inputs : BA0 and BA1 define to whic h bank an ACTIVE, READ, WRITE or PRECHARGE com- mand is being applied. A [n : 0] Input Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRE- CHARGE bit for READ/WRITE commands, to select one lo cation out of the memory array in the respective bank. A10 sampled during a PRECHARGE command det ermines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code dur ing a MODE REGISTER SET command. BA0 and BA1 determines which mode register( mode register or extended mode register ) is loaded during the MODE REG- ISTER SET command. DQ I/O Data Input/Output : Data bus LDQS,UDQS I/O Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. it is used to fetch write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. NC - No Connect : No internal el ectrical connection is present. VDDQ Supply DQ Power Supply : 1.7V to 1.95V VSSQ Supply DQ Ground. VDD Supply Power Supply : 1.7V to 1.95V VSS Supply Ground.

Figure 1. State diagram

umn address) uses A4 ~ A6, A7 ~ A13 is used for test mode. BA0 and BA1 must be set to low for proper MRS operation. Figure 2. Mode Register Set

0 Sequential

1 Interleave

0 BT Burst Length 0 R F U 1) 0 0 0 CAS Latency

Table 1. Burst address ordering for burst length

must be set to low for proper EMRS operation. Refer to the table for specific codes. Figure 3. Extended Mode Register Set

1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self

refresh cycle automatically according to the two temperature ranges ; 45 °C and 85 °C.

1. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.

1) It has +/- 5 °C tolerance.

1. In order to save power consumption, Mobile DDR SDRAM includes PASR option.
2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array.

Figure 4. EMRS code and TCSR , PASR

K4X1G163PC - L(F)E/G - 13 - Mobile DDR SDRAM November 2007 10. Absolute maximum ratings NOTE : 1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. 2) Functional operation should be restricted to recommend operation condition. 3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 11. DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, Tc = -25°C to 85°C) NOTE : 1) Under all conditions, VDDQ must be less than or equal to VDD. 2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 2.7 V Voltage on VDD supply relative to VSS VDD -0.5 ~ 2.7 V Voltage on VDDQ supply relative to VSS VDDQ -0.5 ~ 2.7 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 1.0 W Short circuit current IOS 50 mA Parameter Symbol Min Max Unit Note Supply voltage(for device with a nominal VDD of 1.8V) VDD 1.7 1.95 V 1 I/O Supply voltage VDDQ 1.7 1.95 V 1 Input logic high voltage VIH(DC) 0.7 x VDDQ VDDQ+0.3 V 2 Input logic low voltage VIL(DC) -0.3 0.3 x VDDQ V 2 Output logic high voltage VOH(DC) 0.9 x VDDQ - V IOH = -0.1mA Output logic low voltage VOL(DC) - 0.1 x VDDQ V IOL = 0.1mA Input leakage current II -2 2 uA Output leakage current IOZ -5 5 uA

K4X1G163PC - L(F)E/G - 14 - Mobile DDR SDRAM November 2007 12. DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C) NOTE : 1) It has +/- 5°C tolerance. 2) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request. Please contact Samsung for more information. 3) IDD specifications are tested after the device is properly intialized. 4) Input slew rate is 1V/ns. 5) Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ ; HIGH is defined as V IN ≥ 0.9 * VDDQ ; STABLE is defined as inputs stable at a HIGH or LOW level ; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. Parameter Symbol Test Condition DDR333 DDR266 Unit Note Operating Current (One Bank Active) IDD0 tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE 100 90 mA Precharge Standby Current in power-down mode IDD2P all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 0.5 mA IDD2PS all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 0.5 Precharge Standby Current in non power-down mode IDD2N all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 15 12 mA IDD2NS all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 8 8 Active Standby Current in power-down mode IDD3P one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE mA IDD3PS one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Active Standby Current in non power-down mode (One Bank Active) IDD3N one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 25 25 mA IDD3NS one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 20 20 Operating Current (Burst Mode) IDD4R one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA address inputs are SWITCHING; 50% data change each burst transfer 150 135 mA IDD4W one bank active; BL = 4; tCK = tCKmin ; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer 130 115 Refresh Current IDD5 tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 200 180 mA Self Refresh Current IDD6 CKE is LOW; t CK = t CKmin ; Extended Mode Register set to all 0’s; address and control inputs are STABLE; data bus inputs are STABLE Parameter 451) 85 °C - E Full Array 600 1200 uA 1/2 Array 500 900 1/4 Array 450 750 - G Full Array 500 1000 1/2 Array 440 800 1/4 Array 400 700 Deep Power Down Current IDD8 Deep Power Down Mode Current 25 uA 2

K4X1G163PC - L(F)E/G - 15 - Mobile DDR SDRAM November 2007 13. AC Operating Conditions & Timming Specification NOTE : 1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2) The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Parameter/Condition Symbol Min Max Unit Note Input High (Logic 1) Voltage, all inputs VIH(AC) 0.8 x VDDQ VDDQ+0.3 V 1 Input Low (Logic 0) Voltage, all inputs VIL(AC) -0.3 0.2 x VDDQ V 1 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.4 x VDDQ 0.6 x VDDQ V 2

K4X1G163PC - L(F)E/G - 16 - Mobile DDR SDRAM November 2007 14. AC Timming Parameters & Specifications Parameter Symbol DDR333 DDR266 Unit Note Min Max Min Max Clock cycle time CL=2 tCK 12.0 12.0 ns CL=3 6 7.5 Row cycle time tRC 60 67.5 ns Row active time tRAS 42 70,000 45 70,000 ns RAS to CAS delay tRCD 18 22.5 ns Row precharge time tRP 18 22.5 ns Row active to Row active delay tRRD 12 15 ns Write recovery time tWR 12 15 ns Last data in to Active delay tDAL 2tCK+tRP 2tCK+tRP - 2 Last data in to Read command tCDLR 1 1 tCK Col. address to Col. address delay tCCD 1 1 tCK Clock high level width tCH 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 tCK DQ Output data access time from CK/CK CL=2 tAC 2 8 2 8 ns 3 CL=3 2 5.5 2 6 DQS Output data access time from CK/CK CL=2 tDQSCK 2 8 2 8 ns CL=3 2 5.5 2 6 Data strobe edge to ouput data edge tDQSQ 0.5 0.6 ns Read Preamble CL=2 tRPRE 0.5 1.1 0.5 1.1 tCK CL=3 0.9 1.1 0.9 1.1 Read Postamble tRPST 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 ns 4 DQS-in hold time tWPREH 0.25 0.25 tCK DQS-in high level width tDQSH 0.4 0.6 0.4 0.6 tCK DQS-in low level width tDQSL 0.4 0.6 0.4 0.6 tCK DQS falling edge to CK setup time tDSS 0.2 0.2 tCK DQS falling edge hold time from CK tDSH 0.2 0.2 tCK DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 tCK Address and Control Input setup time tIS 1.1 1.3 ns 1 Address and Control Input hold time tIH 1.1 1.3 ns 1 Address & Control input pulse width tIPW 2.2 2.6 1 DQ & DM setup time to DQS tDS 0.6 0.8 ns 5,6 DQ & DM hold time to DQS tDH 0.6 0.8 ns 5,6 DQ & DM input pulse width tDIPW 1.2 1.8 ns DQ & DQS low-impedence time from CK/CK tLZ 1.0 1.0 ns DQ & DQS high-impedence time from CK/CK tHZ 5.5 6.0 ns DQS write postamble time tWPST 0.4 0.6 0.4 0.6 tCK DQS write preamble time tWPRE 0.25 0.25 tCK Refresh interval time tREF 64 64 ms Mode register set cycle time tMRD 2 2 tCK Power down exit time tPDEX 1 1 tCK CKE min. pulse width(high and low pulse width) tCKE 2 2 tCK

K4X1G163PC - L(F)E/G - 17 - Mobile DDR SDRAM November 2007 NOTE : 1) Input Setup/Hold Slew Rate Derating This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/ns. 2) Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP . 3) tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C). tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C). tAC is measured in the device with half driver strength and under the AC output load condition (Fig.7 in next Page). 4) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 5) I/O Setup/Hold Slew Rate Derating This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ns. 6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 7) Maximum burst refresh cycle : 8 Parameter Symbol DDR333 DDR266 Unit Note Min Max Min Max Auto refresh cycle time tRFC 72 80 ns 7 Exit self refresh to active command tXSR 120 120 ns Data hold from DQS to earliest DQ edge tQH tHPmin - tQHS tHPmin - tQHS ns Data hold skew factor tQHS 0.65 0.75 ns Clock half period tHP tCLmin or tCHmin tCLmin or tCHmin ns Input Setup/Hold Slew Rate ∆tIS ∆tIH (V/ns) (ps) (ps) 1.0 0 0 0.8 +50 +50 0.6 +100 +100 I/O Setup/Hold Slew Rate ∆tIS ∆tIH (V/ns) (ps) (ps) 1.0 0 0 0.8 +75 +75 0.6 +150 +150 Data Rise/Fall Rate ∆tIS ∆tIH (ns/V) (ps) (ps) 00 0 ±0.25 +50 +50 ±0.5 +100 +100

K4X1G163PC - L(F)E/G - 20 - Mobile DDR SDRAM November 2007 19. Command Truth Table (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) NOTE : 1) OP Code : Operand Code. A0 ~ A13 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2) EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3) Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4) BA0 ~ BA1 : Bank select addresses. 5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6) During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7) Burst stop command is valid at every burst length. 8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM. Command CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A13 ~A11, A9~A0 Note Register Mode Register Set H X L L L L OP CODE 1, 2 Refresh Auto Refresh H H LL LH X Self Refresh Entry L 3 Exit L H LH HH X HX XX 3 Bank Active & Row Addr. H X L L H H V Row Address Read & Column Address Auto Precharge Disable HX L H L H V L Column Address (A0~A9) Auto Precharge Enable H 4 Write & Column Address Auto Precharge Disable HX L H L L V L Column Address (A0~A9) Auto Precharge Enable H 4, 6 Deep Power Down Entry H L L H H L X Exit L H H X X X Burst Stop H X L H H L X 7 Precharge Bank Selection HX L L H L VL X All Banks X H 5 Active Power Down Entry H L HX XX XLV VV Exit L H X X X X Precharge Power Down Entry H L HX XX X LH HH Exit L H HX XX LV VV DM H X X 8 No operation (NOP) : Not defined H X HX XX X LH HH 9

K4X1G163PC - L(F)E/G - 21 - Mobile DDR SDRAM November 2007 20. Functional Truth Table Current State CS RAS CAS WE Address Command Action PRECHARGE STANDBY L H H L X Burst Stop ILLEGAL2) L H L X BA, CA, A10 READ/WRITE ILLEGAL2) L L H H BA, RA Active Bank Active, Latch RA L L H L BA, A10 PRE/PREA ILLEGAL4) LLLH X R e f r e s h AUTO-Refresh5) L L L L Op-Code, Mode-Add MRS Mode Register Set5) ACTIVE STANDBY L H H L X Burst Stop NOP L H L H BA, CA, A10 READ/READA Begin Read, Latch CA, Determine Auto-Precharge L H L L BA, CA, A10 WRITE/WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA Active Bank Active/ILLEGAL2) LLHL BA, A10 PRE/PREA Precharge/Precharge All L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ L H H L X Burst Stop Terminate Burst L H L H BA, CA, A10 READ/READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge3) L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active Bank Active/ILLEGAL2) L L H L BA, A10 PRE/PREA Terminate Burst, Precharge10) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge3) L H L L BA, CA, A10 WRITE/WRITEA Terminate Burst, Latch CA, Begin new Write, Determine Auto- Precharge3) L L H H BA, RA Active Bank Active/ILLEGAL2) L L H L BA, A10 PRE/PREA Terminate Burst With DM=High, Precharge10) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ with AUTO PRECHARGE6) (READA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA 6) L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active 6) LLHL BA, A10 PRE/PREA 6) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

K4X1G163PC - L(F)E/G - 22 - Mobile DDR SDRAM November 2007 Current State CS RAS CAS WE Address Command Action WRITE with AUTO RECHARGE7) (WRITEA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA 7) L H L L BA, CA, A10 WRITE/WRITEA 7) L L H H BA, RA Active 7) L L H L BA, A10 PRE/PREA 7) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL PRECHARGING (DURING tRP) L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL2) L L H H BA, RA Active ILLEGAL2) L L H L BA, A10 PRE/PREA NOP4)(Idle after tRP) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING (FROM ROW ACTIVE TO tRCD) L H H L X Burst Stop ILLEGAL2) L H L X BA, CA, A10 READ/WRITE ILLEGAL2) L L H H BA, RA Active ILLEGAL2) LLHL BA, A10 PRE/PREA ILLEGAL2) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE RECOVERING (DURING tWR OR tCDLR) L H H L X Burst Stop ILLEGAL2) L H L H BA, CA, A10 READ ILLEGAL2) L H L L BA, CA, A10 WRITE WRITE L L H H BA, RA Active ILLEGAL2) L L H L BA, A10 PRE/PREA ILLEGAL2) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL RE- FRESHING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MODE REGISTER SETTING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL LLHL BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

K4X1G163PC - L(F)E/G - 23 - Mobile DDR SDRAM November 2007 (H=High Level, L=Low level, X=Don′t Care) NOTE : 1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2) ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. (ILLEGAL = Device operation and/or data integrity are not guaranteed.) 3) Must satisfy bus contention, bus turn around and write recovery requirements. 4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5) ILLEGAL if any bank is not idle. 6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information. 7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information. 8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9) Power-Down, Self-Refresh and Deep Power Down Mode can be entered only from All Bank Idle state. 10) The Deep Power Down Mode is exited by asserting CKE high and full initialization is required after exiting Deep Power Down Mode. Current State CKE n-1 CKE n CS RAS CAS WE Add Action SELF- REFRESHING8) L H H X X X X Exit Self-Refresh LHLHHHX E x i t S e l f - R e f r e s h LHLHHLX I L L E G A L LHLHLXX I L L E G A L LHLLXXX I L L E G A L L L X X X X X NOP (Maintain Self-Refresh) POWER DOWN L H X X X X X Exit Power Down(Idle after tPDEX) L L X X X X X NOP (Maintain Power Down) DEEP POWER DOWN LHHXXXX Exit Deep Power Down 10) L L X X X X X NOP (Maintain Deep Power Down) ALL BANKS IDLE9) H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X Enter Deep Power Down HLLHHLX I L L E G A L H L L H L X X ILLEGAL HLLLXXX I L L E G A L L X X X X X X Refer to Current State=Power Down