K4T51083QG-HCLD5

K4T51043QG SAMSUNG | Alldatasheet

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Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 1 of 47 K4T51043QG 512Mb G-die DDR2 SDRAM Specification 60FBGA & 84FBGA with Lead-Free and Halogen-Free (RoHS compliant) * Samsung Electronics reserves the right to change products or specification without notice. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 2 of 47 K4T51043QG Table of Contents

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 3 of 47 K4T51043QG

Revision History

Revision Month Year History

1.0 August 2007 - Initial Release

1.1 October 2007 - Added x16 IDD Specification

1.2 January 2008 - Added x4 Specification

1.21 February 2008 - Typo Correction

1.3 July 2008 - Updated AC timing table with the JEDEC update(JESD79-2E)

1.4 December 2008 - Updated AC/DC operating condition with the JEDEC update(JESD79-2E)

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 4 of 47 K4T51043QG Speed DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3 Units CAS Latency 5 6 5 43 tCK tRCD(min) 12.5 15 15 15 15 ns tRP(min) 12.5 15 15 15 15 ns tRC(min) 57.5 60 60 60 55 ns Note : 1. Speed bin is in order of CL-tRCD-tRP 2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products. Org. DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3 Package 128Mx4 K4T51043QG-HC(L)E7 K4T51043QG-HC(L)F7 K4T51043QG-H C(L)E6 K4T51043QG-HC(L)D5 K4T51043QG-HC(L)CC 60 FBGA 64Mx8 K4T51083QG-HC(L)E7 K4T51083QG-HC(L)F7 K4T51083QG-H C(L)E6 K4T51083QG-HC(L)D5 K4T51083QG-HC(L)CC 60 FBGA 32Mx16 K4T51163QG-HC(L)E7 K4T51163QG-HC(L)F7 K4T51163QG-H C(L)E6 K4T51163QG-HC(L)D5 K4T51163QG-HC(L)CC 84 FBGA

• JEDEC standard V DD = 1.8V ± 0.1V Power Supply
• V DDQ = 1.8V ± 0.1V
• 200 MHz f CK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/ pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/ sec/pin
• 4 B a n k s
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4 , 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data- strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support -50ohm ODT -High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T CASE 85°C, 3.9us at 85°C < TCASE < 95 °C
• All of products are Lead-Free, Halogen-Free, and RoHS com- pliant The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4banks or 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks device. This synchronous device achieves high speed double- data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency -1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS / CAS multiplexing style. For example, 512Mb(x8) device receive 14/10/2 addressing. The 512Mb DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V V DDQ. The 512Mb DDR2 device is available in 60ball FBGAs(x8) and in 84ball FBGAs(x16). Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. Note : This data sheet is an abstract of full DDR2 specificati on and does not cover the common features which are described in “Samsung’s DDR2 SDRAM Device Operation & Timing Diagram”

1.0 Ordering Information

2.0 Key Features

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 5 of 47 K4T51043QG 3.1 x4 package pinout (Top View) : 60ball FBGA Package A B C D E F G H J K L VDD NC V SS NC VSSQ DM VDDQ VDDQ VDDQ VSSQ VSSQ DQS DQS NC DQ0VDDQ DQ2 VSSQ NC VSSDL VDDCK RAS CK CAS CS A6 A4 A11 A8 NC A13NCA12 A9A7 VDD A10/AP VSS VDDQ VSSQ DQ1 DQ3NC VDDL BA1 VREF VSS CKE WE BA0 VDD VSS ODT NC 12 3 7 8 9 Note : 1. Pin B3 has identical capacitance as pin B7. 2. VDDL and VSSDL are power and ground for the DLL. Ball Locations (x4) 123456789 A B C D E F G H J K L : Populated Ball + : Depopulated Ball Top View (See the balls through the package)

3.0 Package Pinout/Mechanical Dimension & Addressing

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 6 of 47 K4T51043QG A B C D E F G H J K L VDD NU/ VSS DQ6 V SSQ VDDQ VDDQ VDDQ VSSQ VSSQ DQS DQS DQ7 DQ0VDDQ DQ2 VSSQ DQ5 VSSDL VDDCK RAS CK CAS CS A6 A4 A11 A8 NC A13NCA12 A9A7 VDD A10/AP VSS VDDQ VSSQ DQ1 DQ3DQ4 VDDL BA1 VREF VSS CKE WE BA0 VDD VSS DM/ RDQS RDQS NC ODT Note : 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input masking function is disabled. 3. The function of DM or RDQS/RDQS are enabled by EMRS command. 4. VDDL and VSSDL are power and ground for the DLL. 123456789 A B C D E F G H J K L Ball Locations (x8) : Populated Ball + : Depopulated Ball Top View (See the balls through the package) 12 3 7 8 9 3.2 x8 package pinout (Top View) : 60ball FBGA Package

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 7 of 47 K4T51043QG A B C D E F G H J K L VDD NC V SS DQ6 VSSQ LDM VDDQ VDDQ VDDQ VSSQ VSSQ LDQS LDQS DQ7 DQ0VDDQ DQ2 VSSQ DQ5 VSSDL VDDCK RAS CK CAS CS A6 A4 A11 A8 NC NCNCA12 A9A7 VDD A10/AP VSS VDDQ VSSQ DQ1 DQ3DQ4 VDDL BA1 VREF VSS CKE WE BA0 VDD VSS VDD NC V SS DQ14 V SSQ UDM VDDQ VDDQ VSSQ DQ9 DQ11DQ12 VDDQ VDDQ VSSQ VSSQ UDQS UDQS DQ15 DQ8VDDQ DQ10 VSSQ DQ13 NC ODT M N P R Note : 1. VDDL and VSSDL are power and ground for the DLL. 2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used. 123456789 A B C D E F G H J K L M N P R : Populated Ball + : Depopulated Ball Top View Ball Locations (x16) (See the balls through the package) 1 23 789 3.3 x16 package pinout (Top View) : 84ball FBGA Package

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 8 of 47 K4T51043QG 9.50 ± 0.10 0.80 7.50 ± 0.10 0.80 1.60 (0.95) (1.90) 9.50 ± 0.10 7.50 ± 0.10 0.50 ± 0.05 0.10MAX 0.35±0.05 1.10±0.10 # A1 INDEX MARK #A1 (Datum A) (Datum B) MOLDING AREA A B

3.4 FBGA Package Dimension(x4/x8)

0.80 x 10 = 8.00 B C D E F G H J K L A 0.80 x 8 = 6.40 60-∅0.45 Solder ball

0.2 M AB

(Post reflow 0.50 ± 0.05)

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 9 of 47 K4T51043QG 12.50 ± 0.10 0.80 7.50 ± 0.10 123456789 3.20 0.80 1.60 (0.95) (1.90) 0.50±0.05 0.10MAX 0.35±0.05 1.10±0.10 5.60 # A1 INDEX MARK (Datum A) (Datum B) MOLDING AREA A B

3.5 FBGA Package Dimension(x16)

0.80 x 14 = 11.20 0.80 x 8 = 6.40 12.50 ± 0.10 7.50 ± 0.10 #A1 B C D E F G H K L N A J M P R 84-∅0.45 Solder ball (Post reflow 0.50 ± 0.05)

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 10 of 47 K4T51043QG Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out- put drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. After VREF has become stable during the power on and initialization swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on sys- tems with multiple Ranks. CS is considered part of the command code. ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16 configuration, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register Set(EMRS) is programmed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM (UDM), (LDM) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci- dent with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command. BA0 - BA1 Input Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 - A13 Input Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2. The address inputs also provide the op- code during Mode Register Set commands. DQ Input/Output Data Input/ Output: Bi-directional data bus. DQS, (DQS) (LDQS), (LDQS) (UDQS), (UDQS) (RDQS), (RDQS) Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. A control bit at EMRS(1)[A10] enables or disables all complementary data strobe signals. In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1) x4 DQS/DQS x8 DQS/DQS if EMRS(1)[A11] = 0 x8 DQS/DQS, RDQS/RDQS, if EMRS(1)[A11] = 1 x16 LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1) x4 DQS x8 DQS if EMRS(1) [A11] = 0 x8 DQS, RDQS, if EMRS(1) [A11] = 1 x16 LDQS and UDQS NC No Connect : No internal electrical connection is present. V DD/VDDQ Supply Power Supply : 1.8V +/- 0.1V, DQ Power Supply : 1.8V +/- 0.1V VSS/VSSQ Supply Ground, DQ Ground VDDL Supply DLL Power Supply : 1.8V +/- 0.1V VSSDL Supply DLL Ground VREF Supply Reference voltage

4.0 Input/Output Functional Description

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 11 of 47 K4T51043QG 512Mb * Reference information: The following tables are address mapping information for other densities. 256Mb 1Gb 2Gb 4Gb Configuration 128Mb x4 64Mb x 8 32Mb x16 # of Banks 4 4 4 Bank Address BA0,BA1 BA0,BA1 BA0,BA1 Auto precharge A10/AP A10/AP A10/AP Row Address A0 ~ A13 A0 ~ A13 A0 ~ A12 Column Address A0 ~ A9,A11 A0 ~ A9 A0 ~ A9 Configuration 64Mb x4 32Mb x 8 16Mb x16 # of Banks 4 4 4 Bank Address BA0,BA1 BA0,BA1 BA0,BA1 Auto precharge A10/AP A10/AP A10/AP Row Address A0 ~ A12 A0 ~ A12 A0 ~ A12 Column Address A0 ~ A9,A11 A0 ~ A9 A0 ~ A8 Configuration 256Mb x4 128Mb x 8 64Mb x16 # of Banks 8 8 8 Bank Address BA0 ~ BA2 BA0 ~ BA2 BA0 ~ BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 ~ A13 A0 ~ A13 A0 ~ A12 Column Address A0 ~ A9,A11 A0 ~ A9 A0 ~ A9 Configuration 512Mb x4 256Mb x 8 128Mb x16 # of Banks 8 8 8 Bank Address BA0 ~ BA2 BA0 ~ BA2 BA0 ~ BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 ~ A14 A0 ~ A14 A0 ~ A13 Column Address A0 ~ A9,A11 A0 ~ A9 A0 ~ A9 Configuration 1 Gb x4 512Mb x 8 256Mb x16 # of Banks 8 8 8 Bank Address BA0 ~ BA2 BA0 ~ BA2 BA0 ~ BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 - A15 A0 - A15 A0 - A14 Column Address/page size A0 - A9,A11 A0 - A9 A0 - A9

5.0 DDR2 SDRAM Addressing

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 12 of 47 K4T51043QG Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together. Symbol Parameter Rating Units Notes Min. Typ. Max. VDD Supply Voltage 1.7 1.8 1.9 V VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 4 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 4 VREF Input Reference Voltage 0.49*V DDQ 0.50*VDDQ 0.51*VDDQ mV 1,2 VTT Termination Voltage V REF-0.04 V REF VREF+0.04 V 3 Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ. When VDD and VDDQ and VDDL are less than 500mV, VREF may be equal to or less than 300mV. 4. Voltage on any input or I/O may not exceed voltage on VDDQ. Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to VSS - 1.0 V ~ 2.3 V V 1 VDDQ Voltage on VDDQ pin relative to VSS - 0.5 V ~ 2.3 V V 1 VDDL Voltage on VDDL pin relative to VSS - 0.5 V ~ 2.3 V V 1 VIN, VOUT Voltage on any pin relative to VSS - 0.5 V ~ 2.3 V V 1 TSTG Storage Temperature -55 to +100 °C 1, 2

6.0 Absolute Maximum DC Ratings

7.0 AC & DC Operating Conditions

7.1 Recommended DC Operating Conditions (SSTL - 1.8)

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 13 of 47 K4T51043QG

7.2 Operating Temperature Condition

Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

7.3 Input DC Logic Level

7.4 Input AC Logic Level

Note : 1. For information related to VPEAK value, Refer to overshoot/undershoot specification in device operation and timing datasheet; maximum peak ampli- tude allowed for overshoot and undershoot.

7.5 AC Input Test Conditions

Note : 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from V REF to VIH(AC) min for rising edges and the range from V REF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from V IL(AC) to VIH(AC) on the positive transitions and V IH(AC) to VIL(AC) on the negative transitions. Symbol Parameter Rating Units Notes TOPER Operating Temperature 0 to 95 °C 1, 2 Symbol Parameter Min. Max. Units Notes VIH(DC) DC input logic high VREF + 0.125 V DDQ + 0.3 V VIL(DC) DC input logic low - 0.3 V REF - 0.125 V Symbol Parameter DDR2-400, DDR2-533 DDR2-667, DDR2-800 Units Min. Max. Min. Max. VIH(AC) AC input logic high VREF + 0.250 V DDQ + VPEAK VREF + 0.200 V DDQ + VPEAK V VIL(AC) AC input logic low VSSQ - VPEAK VREF - 0.250 V SSQ - VPEAK VREF - 0.200 V Symbol Condition Value Units Notes VREF Input reference voltage 0.5 * V DDQ V1 VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 VDDQ VIH(AC) min VIH(DC) min VREF VIL(DC) max VIL(AC) max VSS < AC Input Test Signal Waveform > VSWING(MAX) delta TRdelta TF VREF - VIL(AC) max delta TF Falling Slew = Rising Slew = VIH(AC) min - VREF delta TR

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 14 of 47 K4T51043QG VDDQ Crossing point VSSQ VTR VCP VID VIX or VOX < Differential signal levels >

7.6 Differential input AC logic Level

Note : 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to VIH (AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross. 3. For information related to VPEAK value, Refer to overshoot/undershoot specification in device operation and timing datasheet; maximum peak ampli- tude allowed for overshoot and undershoot.

7.7 Differential AC output parameters

Note : 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.

8.0 ODT DC electrical characteristics

Note : 1. Test condition for Rtt measurements Measurement Definition for Rtt(eff) : Apply V IH (AC) and VIL (AC) to test pin separately, then measure current I(VIH (AC)) and I( VIL (AC)) respectively. V IH (AC), VIL (AC), and VDDQ values defined in SSTL_18 Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load. Symbol Parameter Min. Max. Units Notes VID(AC) AC differential input voltage 0.5 V DDQ V1 VIX(AC) AC differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * V DDQ + 0.175 V 2 Symbol Parameter Min. Max. Units Note VOX(AC) AC differential cross point voltage 0.5 * VDDQ - 0.125 0.5 * V DDQ + 0.125 V 1 PARAMETER/CONDITION SYMBOL MIN NOM MAX UNITS NOTES Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt1(eff) 60 75 90 ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt2(eff) 120 150 180 ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Rtt3(eff) 40 50 60 ohm 1 Deviation of VM with respect to V DDQ/2 delta V M - 6 + 6 % 1 Rtt(eff) = VIH(AC) - VIL (AC) I(VIH (AC)) - I(VIL (AC)) delta VM = 2 x VM VDDQ x 100%- 1

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 15 of 47 K4T51043QG 25 ohms VTT Output (VOUT) Reference Point

9.0 OCD default characteristics

Note : 2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for val- ues of VOUT between VDDQ and VDDQ- 280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/ Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from VIL(AC) to VIH(AC). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaran- teed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty. Output slew rate load : 7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin, 667Mb/sec/pin and 800Mb/sec/pin speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification. Description Parameter Min Nom Max Unit Notes Output impedance 18ohm at norminal condition See full strength default driver characteristics on device operation specification ohms 1,2 Output impedance step size for OCD calibration 0 1.5 ohms 6 Pull-up and pull-down mismatch 0 4 ohms 1,2,3 Output slew rate Sout 1.5 5 V/ns 1,4,5,6,7,8

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 16 of 47 K4T51043QG (IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5) Symbol Proposed Conditions Units Notes IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is same as IDD4W mA IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputsare STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 mA Slow PDN Exit MRS(12) = 1 mA IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS- max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH- ING; Data pattern is same as IDD4W mA IDD5B Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid com- mands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal mA Low Power mA IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol- lowing page for detailed timing conditions mA

10.0 IDD Specification Parameters and Test Conditions

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 17 of 47 K4T51043QG Note : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS , RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as V IN ≤ VILAC(max) HIGH is defined as V IN ≥ VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at V REF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. For purposes of IDD testing, the following parameters are utilized Detailed IDD7 The detailed timings are shown below for IDD7. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA Timing Patterns for 4 bank devices x4/ x8/ x16 -DDR2-400 3/3/3 A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D -DDR2-533 4/4/4 A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D -DDR2-667 5/5/5 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D -DDR2-667 4/4/4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D -DDR2-800 6/6/6 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D -DDR2-800 5/5/5 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D DDR2-800 DDR2-800 DDR2-667 DDR2-533 DDR2-400 UnitsParameter 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 CL(IDD) 5 6 5 4 3 tCK tRCD(IDD) 12.5 15 15 15 15 ns tRC(IDD) 57.5 60 60 60 55 ns tRRD(IDD)-x16 10 10 10 10 10 ns tCK(IDD) 2.5 2.5 3 3.75 5 ns tRASmin(IDD) 45 45 45 45 40 ns tRP(IDD) 12.5 15 15 15 15 ns tRFC(IDD) 105 105 105 105 105 ns

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 18 of 47 K4T51043QG Symbol 128Mx4 (K4T51043QG) Unit Notes800@CL=5 800@CL=6 667@CL=5 533@CL=4 400@CL=3 CE7 LE7 CF7 LF7 CE6 LE6 CD5 LD5 CCC LCC IDD0 80 80 75 75 70 mA IDD1 90 90 85 85 85 mA IDD2P 8 5 8 5 8 5 8 4.5 8 4.5 mA I D D 2 Q 3 53 53 53 03 0 m A I D D 2 N 4 04 04 03 53 5 m A I D D 3 P - F 3 03 03 03 03 0 m A I D D 3 P - S 1 21 21 21 21 2 m A I D D 3 N 5 55 55 55 05 0 m A IDD4W 115 115 100 75 75 mA IDD4R 125 125 110 85 85 mA IDD5 115 115 110 105 105 mA I D D 6 8484848484 m A IDD7 210 210 175 175 175 mA Symbol 64Mx8 (K4T51083QG) Unit Notes800@CL=5 800@CL=6 667@CL=5 533@CL=4 400@CL=3 CE7 LE7 CF7 LF7 CE6 LE6 CD5 LD5 CCC LCC IDD0 85 85 75 75 70 mA IDD1 95 95 90 85 85 mA I D D 2 P 8585858 4 . 5 8 4 . 5m A I D D 2 Q 3 53 53 53 03 0 m A I D D 2 N 4 04 04 03 53 5 m A I D D 3 P - F 3 03 03 03 03 0 m A I D D 3 P - S 1 21 21 21 21 2 m A I D D 3 N 6 06 05 55 05 0 m A IDD4W 110 110 100 85 80 mA IDD4R 140 140 130 105 95 mA IDD5 110 110 105 105 100 mA I D D 6 8484848484 m A IDD7 210 210 175 175 175 mA Symbol 32Mx16 (K4T51163QG) Unit Notes800@CL=5 800@CL=6 667@CL=5 533@CL=4 400@CL=3 CE7 LE7 CF7 LF7 CE6 LE6 CD5 LD5 CCC LCC IDD0 95 95 90 90 90 mA IDD1 115 115 110 105 105 mA IDD2P 8 5 8 5 8 5 8 4.5 8 4.5 mA I D D 2 Q 3 53 53 53 03 0 m A I D D 2 N 4 04 04 03 53 5 m A I D D 3 P - F 3 03 03 03 03 0 m A I D D 3 P - S 1 21 21 21 21 2 m A I D D 3 N 6 06 05 55 05 0 m A IDD4W 130 130 115 100 95 mA IDD4R 185 185 165 135 130 mA IDD5 110 110 105 105 105 mA I D D 6 8484848484 m A IDD7 275 275 235 235 210 mA

11.0 DDR2 SDRAM IDD Spec

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 19 of 47 K4T51043QG Speed DDR2-800(E7) DDR2-800(F7) DDR2-667(E6) DDR2-533(D5) DDR2-400(CC) UnitsBin (CL - tRCD - tRP) 5-5-5 6-6-6 5 - 5 - 5 4 - 4 - 4 3 - 3 - 3 Parameter min max min max min max min max min max tCK, CL=3 5 8 - - 5 8 5 8 5 8 ns tCK, CL=4 3.75 8 3.75 8 3.75 8 3.75 8 5 8 ns tCK, CL=5 2.5 8 3 8 3 8 3.75 8 - - ns tRCD 12.5 - 15 - 15 - 15 - 15 - ns tRP 12.5 - 15 - 15 - 15 - 15 - ns tRC 57.5 - 60 - 60 - 60 - 55 - ns tRAS 45 70000 45 70000 45 70000 45 70000 40 70000 ns Parameter Symbol DDR2-400 DDR2-533 DDR2-667 DDR2-800 Units Min Max Min Max Min Max Input capacitance delta, CK and CK CDCK x 0.25 x 0.25 x 0.25 pF Input capacitance delta, all other input-only pins CDI x 0.25 x 0.25 x 0.25 pF Input/output capacitance delta, DQ, DM, DQS, DQS CDIO x 0.5 x 0.5 x 0.5 pF

13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400

(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)

13.1 Refresh Parameters by Device Density

Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active/Refresh command time tRFC 75 105 127.5 195 327.5 ns Average periodic refresh interval tREFI

13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

12.0 Input/Output capacitance

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 20 of 47 K4T51043QG (For information related to the entries in this table, refer to both the general notes and the specific notes following this table.) Parameter Symbol DDR2-800 DDR2-667 Units Notes min max min max DQ output access time from CK/CK tAC -400 400 -450 450 ps 40 DQS output access time from CK/CK tDQSCK -350 350 -400 400 ps 40 Average clock HIGH pulse width tCH(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36 Average clock LOW pulse width tCL(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36 CK half pulse period tHP Min(tCL(abs), tCH(abs)) x Min(tCL(abs), tCH(abs)) x ps 37 Average clock period tCK(avg) 2500 8000 3000 8000 ps 35,36 DQ and DM input hold time tDH(base) 125 x 175 x ps 6,7,8,21,28,31 DQ and DM input setup time tDS(base) 50 x 100 x ps 6,7,8,20,28,31 Control & Address input pulse width for each input tIPW 0.6 x 0.6 x tCK(avg) DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x tCK(avg) Data-out high-impedance time from CK/CK tHZ x tAC(max) x tAC(max) ps 18,40 DQS/DQS low-impedance time from CK/CK tLZ(DQS) tAC(min) tAC(max) tAC(min) tAC(max) ps 18,40 DQ low-impedance time from CK/CK tLZ(DQ) 2* tAC(min) tAC(max) 2* tAC(min) tAC(max) ps 18,40 DQS-DQ skew for DQS and associated DQ signals tDQSQ x 200 x 240 ps 13 DQ hold skew factor tQHS x 300 x 340 ps 38 DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x ps 39 DQS latching rising transitions to associated clock edges tDQSS - 0.25 0.25 -0.25 0.25 tCK(avg) 30 DQS input HIGH pulse width tDQSH 0.35 x 0.35 x tCK(avg) DQS input LOW pulse width tDQSL 0.35 x 0.35 x tCK(avg) DQS falling edge to CK setup time tDSS 0.2 x 0.2 x tCK(avg) 30 DQS falling edge hold time from CK tDSH 0.2 x 0.2 x tCK(avg) 30 Mode register set command cycle time tMRD 2 x 2 x nCK MRS command to ODT update delay tMOD 0 12 0 12 ns 32 Write postamble tWPST 0.4 0.6 0.4 0.6 tCK(avg) 10 Write preamble tWPRE 0.35 x 0.35 x tCK(avg) Address and control input hold time tIH(base) 250 x 275 x ps 5,7,9,23,29 Address and control input setup time tIS(base) 175 x 200 x ps 5,7,9,22,29 Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK(avg) 19,41 Read postamble tRPST 0.4 0.6 0.4 0.6 tCK(avg) 19,42 Activate to activate command period for 1KB page size products tRRD 7.5 x 7.5 x ns 4,32 Activate to activate command period for 2KB page size products tRRD 10 x 10 x ns 4,32

13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 21 of 47 K4T51043QG Parameter Symbol DDR2-800 DDR2-667 Units Notes min max min max Four Activate Window for 1KB page size products tFAW 35 x 37.5 x ns 32 Four Activate Window for 2KB page size products tFAW 45 x 50 x ns 32 CAS to CAS command delay tCCD 2 x 2 x nCK Write recovery time tWR 15 x 15 x ns 32 Auto precharge write recovery + precharge time tDAL WR + tnRP x WR + tnRP x nCK 33 Internal write to read command delay tWTR 7.5 x7 . 5 x ns 24,32 Internal read to precharge command delay tRTP 7.5 x7 . 5 x ns 3,32 Exit self refresh to a non-read command tXSNR tRFC + 10 x tRFC + 10 x ns 32 Exit self refresh to a read command tXSRD 200 x 200 x nCK Exit precharge power down to any command tXP 2 x 2 x nCK Exit active power down to read command tXARD 2 x 2 x nCK 1 Exit active power down to read command (slow exit, lower power) tXARDS 8 - AL x 7 - AL x nCK 1,2 CKE minimum pulse width (HIGH and LOW pulse width) tCKE 3 x 3 x nCK 27 O D T t u r n - o n d e l a y t A O N D 2222 nCK 16 ODT turn-on tAON tAC(min) tAC(max)+0.7 tAC(min) tAC(max)+0.7 ns 6,16,40 ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2*tCK(avg) +tAC(max)+1 tAC(min)+2 2*tCK(avg) +tAC(max)+1 ns ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 nCK 17,45 ODT turn-off tAOF tAC(min) tAC(max)+0.6 tAC(min) tAC(max)+0.6 ns 17,43,45 ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5*tCK(avg) +tAC(max)+1 tAC(min)+2 2.5*tCK(avg) +tAC(max)+1 ns ODT to power down entry latency tANPD 3 x3 x nCK ODT power down exit latency tAXPD 8 x8 x nCK OCD drive mode output delay tOIT 0 12 0 12 ns 32 Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay tIS+tCK(avg) +tIH x tIS+tCK(avg) +tIH xn s 1 5

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 22 of 47 K4T51043QG (For information related to the entries in this table, refer to both the general notes and the specific notes following this table.) Parameter Symbol DDR2-533 DDR2-400 Units Notes min max min max DQ output access time from CK/CK tAC -500 500 -600 600 ps DQS output access time from CK/CK tDQSCK -450 450 -500 500 ps CK HIGH pulse width tCH 0.45 0.55 0.45 0.55 tCK CK LOW pulse width tCL 0.45 0.55 0.45 0.55 tCK CK half pulse period tHP Min(tCL, tCH) x Min(tCL, tCH) x ps 11,12 Clock cycle time, CL=x tCK 3750 8000 5000 8000 ps 15 DQ and DM input hold time (differential strobe) tDH(base) 225 x 275 x ps 6,7,8,21,28 DQ and DM input setup time (differential strobe) tDS(base) 100 x 150 x ps 6,7,8,20,28 DQ and DM input hold time (single-ended strobe) tDH1(base) -25 x 25 x ps 6,7,8,26 DQ and DM input setup time (single-ended strobe) tDS1(base) -25 x 25 x ps 6,7,8,25 Control & Address input pulse width for each input tIPW 0.6 x 0.6 x tCK DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x tCK Data-out high-impedance time from CK/CK tHZ x tAC(max) x14 tAC(max) ps 18 DQS(/DQS) low-impedance time from CK/CK tLZ(DQS) tAC(min) tAC(max) tAC(min) tAC(max) ps 18 DQ low-impedance time from CK/CK tLZ(DQ) 2* tAC(min) tAC(max) 2* tAC(min) tAC(max) ps 18 DQS-DQ skew for DQS and associated DQ signals tDQSQ x 300 x 350 ps 13 DQ hold skew factor tQHS x 400 x 450 ps 12 DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x ps DQS latching rising transitions to associated clock edges tDQSS -0.25 0.25 -0.25 0.25 tCK DQS input HIGH pulse width tDQSH 0.35 x 0.35 x tCK DQS input LOW pulse width tDQSL 0.35 x 0.35 x tCK DQS falling edge to CK setup time tDSS 0.2 x 0.2 x tCK DQS falling edge hold time from CK tDSH 0.2 x 0.2 x tCK Mode register set command cycle time tMRD 2x 2x tCK MRS command to ODT update delay tMOD 0 12 0 12 ns Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 10 Write preamble tWPRE 0.35 x 0.35 x tCK Address and control input hold time tIH(base) 375 x 475 x ps 5,7,9,23 Address and control input setup time tIS(base) 250 x 350 x ps 5,7,9,22 Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 19 Read postamble tRPST 0.4 0.6 0.4 0.6 tCK 19 Active to active command period for 1KB page size products tRRD 7.5 x 7.5 x ns 4 Active to active command period for 2KB page size products tRRD 10 x 10 x ns 4

13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 23 of 47 K4T51043QG Parameter Symbol DDR2-533 DDR2-400 Units Notes min max min max Four Activate Window for 1KB page size products tFAW 37.5 x 37.5 x ns Four Activate Window for 2KB page size products tFAW 50 x 50 x ns CAS to CAS command delay tCCD 2 x 2 x tCK Write recovery time tWR 15 x 15 x ns Auto precharge write recovery + precharge time tDAL WR+tRP x WR+tRP x tCK 14 Internal write to read command delay tWTR 7.5 x1 0 x ns 24 Internal read to precharge command delay tRTP 7.5 x7 . 5 x ns 3 Exit self refresh to a non-read command tXSNR tRFC + 10 x tRFC + 10 x ns Exit self refresh to a read command tXSRD 200 x2 0 0 x tCK Exit precharge power down to any non-read command tXP 2 x 2 x tCK Exit active power down to read command tXARD 2 x 2 x tCK 1 Exit active power down to read command (slow exit, lower power) tXARDS 6 - AL x 6 - AL x tCK 1,2 CKE minimum pulse width (HIGH and LOW pulse width) tCKE 3 x3 xt C K 2 7 ODT turn-on delay tAOND 2 2 2 2 tCK 16 ODT turn-on tAON tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns 16 ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2tCK+ tAC(max)+1 tAC(min)+2 2tCK+ tAC(max)+1 ns ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK 17,44 ODT turn-off tAOF tAC(min) tAC(max) + 0.6 tAC(min) tAC(max) + 0.6 ns 17,44 ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+ tAC(max)+1 tAC(min)+2 2.5tCK+ tAC(max)+1 ns ODT to power down entry latency tANPD 3 x3 xt C K ODT power down exit latency tAXPD 8 x8 xt C K OCD drive mode output delay tOIT 0 12 0 12 ns 32 Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay tIS+tCK+tIH x tIS+tCK+tIH xn s 1 5

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 24 of 47 K4T51043QG

14.0 General notes, which may apply for all AC parameters

1. DDR2 SDRAM AC timing reference load Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended t o be either a precise repre sentation of the typical system environment or a depiction of t he actual load presented by a pr oduction tester. System designer s will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential 2. Slew Rate Measurement Levels a) Output slew rate for falling and rising edges is measured between V TT - 250 mV and V TT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS ) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b) Input slew rate for single ended signals is measured from V REF(DC) to V IH(AC),min for rising edges and from V REF(DC) to V IL(AC),max for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = + 500 mV (+ 250 mV to - 500 mV for falling edges). c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in Figure 2. VDDQ DUT DQ DQS DQS Output VTT = VDDQ/2 25Ω Timing reference point Figure 1 - AC Timing Reference Load RDQS RDQS VDDQ DUT DQ DQS, DQS RDQS, RDQS Output VTT = VDDQ/2 25ΩTest point Figure 2 - Slew Rate Test Load

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 26 of 47 K4T51043QG

15.0 Specific Notes for dedicated AC parameters

1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. 2. AL = Additive Latency. 3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min) have been satisfied. 4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency. 5. Timings are specified with command/address input slew rate of 1.0 V/ns. 6. Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns. 7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1.0 V/ns in single ended mode. 8. Data setup and hold time derating. Table 1 - DDR2-400/533 tDS/tDH derating with differential data strobe Table 2 - DDR2-667/800 tDS/tDH derating with differential data strobe ∆tDS, ∆tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, the note applies to entire Table) DQS,DQS Differential Slew Rate DQ Siew rate V/ns 1 . 5 8 32 18 32 18 32 19 53 3 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - ∆tDS, ∆tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, the note applies to entire Table) DQS,DQS Differential Slew Rate DQ Slew rate V/ns 0 . 8 ---- - 1 3 - 3 1 - 1 - 1 9 1 1 - 7 2 3 5 3 5 1 7 ----

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 27 of 47 K4T51043QG Table 3 - DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the ∆tDS and ∆tDH derating value respectively. Example: tDS (total setup time) =tDS(base) +∆tDS. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V REF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier t han the nominal slew rate line between shaded ’V REF(DC) to ac region’, use nominal slew rate for derating value (See Figure 5 for differential data strobe and Figure 6 for single -ended data strobe.) If the actual signal is later than the n ominal slew rate line anywhere between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the act ual signal from the ac level to dc level is used for derating val ue (see Figure 7 for differential data strobe and Figure 8 for single-ended data strobe) Hold (tDH) nominal slew rate for a rising signal is defi ned as the slew rate between the last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to V REF(DC) region’, use nominal slew rate for derating value (see Figure 9 for differential data strobe and Figure 10 for single-ended data strobe) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 11 for differential data strobe and Figure 12 for single-ended data strobe) Although for slow slew rates the total setup time might be nega tive (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in Tables 1, 2 and 3, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. ∆tDS1, ∆tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table) DQS Single-ended Slew Rate ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH DQ Slew rate V/ns

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 28 of 47 K4T51043QG VSS tDS tDH Setup Slew RateSetup Slew Rate Rising SignalFalling Signal ∆TF ∆TR VREF(DC) - VIL(AC)max ∆TF= VIH(AC)min - VREF(DC) ∆TR= VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max nominal slew rate nominal slew rate VREF to ac region VREF to ac region tDS tDH tVAC DQS DQS Figure 5 - IIIustration of nominal slew rate for tDS (differential DQS,DQS)

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 29 of 47 K4T51043QG VSS tDS tDH Setup Slew RateSetup Slew Rate Rising SignalFalling Signal ∆TF ∆TR VREF(DC) - VIL(AC)max ∆TF= VIH(AC)min - VREF(DC) ∆TR= VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max nominal slew rate nominal slew rate VREF to ac region VREF to ac region DQS Figure 6 - IIIustration of nominal slew rate for tDS (single-ended DQS) VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max VSS tDHtDS Note1 Note : DQS signal must be monotonic between VIL(AC)max and VIH(AC)min.

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 30 of 47 K4T51043QG VSS Setup Slew Rate Setup Slew Rate Rising Signal Falling Signal ∆TF ∆TR tangent line[VREF(DC) - VIL(AC)max] ∆TF= tangent line[VIH(AC)min - VREF(DC)] ∆TR= VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max tangent tangent VREF to ac region VREF to ac region line line nominal line nominal line tDS tDH tDS tDH DQS DQS Figure 7 - IIIustration of tangent line for tDS (differential DQS, DQS)

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 31 of 47 K4T51043QG VSS Setup Slew Rate Setup Slew Rate Rising Signal Falling Signal ∆TF ∆TR tangent line[VREF(DC) - VIL(AC)max] ∆TF= tangent line[VIH(AC)min - VREF(DC)] ∆TR= VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max tangent tangent VREF to ac region VREF to ac region line line nominal line nominal line Figure 8 - IIIustration of tangent line for tDS (single-ended DQS) tDS tDH DQS VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max VSS tDHtDS Note1 Note : DQS signal must be monotonic between VIL(DC)max and VIH(DC)min.

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 32 of 47 K4T51043QG VSS Hold Slew RateHold Slew Rate Falling SignalRising Signal ∆TR ∆TF VREF(DC) - VIL(DC)max ∆TR= VIH(DC)min - VREF(DC) ∆TF= VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max nominal slew rate nominal slew rate dc to VREF region dc to VREF region tDS tDH tDS tDH DQS DQS Figure 9 - IIIustration of nominal slew rate for tDH (differential DQS, DQS)

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 33 of 47 K4T51043QG VSS Hold Slew RateHold Slew Rate Falling SignalRising Signal ∆TR ∆TF VREF(DC) - VIL(DC)max ∆TR= VIH(DC)min - VREF(DC) ∆TF= VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max nominal slew rate nominal slew rate dc to VREF region dc to VREF region Figure 10 - IIIustration of nominal slew rate for tDH (single-ended DQS) tDS tDH DQS VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max VSS tDHtDS Note1 Note : DQS signal must be monotonic between VIL(DC)max and VIH(DC)min.

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 34 of 47 K4T51043QG Hold Slew Rate ∆TF∆TR tangent line [ VIH(DC)min - VREF(DC) ] ∆TF= tangent tangent dc to VREF region dc to VREF region line line nominal line nominal line Falling Signal Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ] ∆TR= Rising Signal tDS tDH tDS tDH DQS DQS Figure 11 - IIIustration of tangent line for tDH (differential DQS, DQS) VSS VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 35 of 47 K4T51043QG Hold Slew Rate ∆TF∆TR tangent line [ VIH(DC)min - VREF(DC) ] ∆TF= tangent tangent dc to VREF region dc to VREF region line line nominal line nominal line Falling Signal Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ] ∆TR= Rising Signal Figure 12 - IIIustration of tangent line for tDH (single-ended DQS) Note : DQS signal must be monotonic between VIL(DC)max and VIH(DC)min. tDS tDH DQS VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max VSS tDHtDS Note1 VSS VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 36 of 47 K4T51043QG 9. tIS and tIH (input setup and hold) derating Table 4 - Derating values for DDR2-400, DDR2-533 ∆tIS, ∆tIH Derating Values for DDR2-400, DDR2-533 CK, CK Differential Slew Rate 2.0 V/ns 1.5 V/ns 1.0 V/ns Units Notes Command/ Address Slew rate(V/ns) 4.0 +187 +94 +217 +124 +247 +154 ps 1 3.5 +179 +89 +209 +119 +239 +149 ps 1 3.0 +167 +83 +197 +113 +227 +143 ps 1 2.5 +150 +75 +180 +105 +210 +135 ps 1 2.0 +125 +45 +155 +75 +185 +105 ps 1 1.5 +83 +21 +113 +51 +143 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 -11 -14 +19 +16 +49 +46 ps 1 0.8 -25 -31 +5 -1 +35 +29 ps 1 0.7 -43 -54 -13 -24 +17 +6 ps 1 0.6 -67 -83 -37 -53 -7 -23 ps 1 0.5 -110 -125 -80 -95 -50 -65 ps 1 0.4 -175 -188 -145 -158 -115 -128 ps 1 0.3 -285 -292 -255 -262 -225 -232 ps 1 0.25 -350 -375 -320 -345 -290 -315 ps 1 0.2 -525 -500 -495 -470 -465 -440 ps 1 0.15 -800 -708 -770 -678 -740 -648 ps 1 0.1 -1450 -1125 -1420 -1095 -1390 -1065 ps 1

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 37 of 47 K4T51043QG Table 5 - Derating values for DDR2-667, DDR2-800 For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ∆tIS and ∆tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value (see Figure 13). If the actual signal is later than the nominal slew rate line anywhere between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 14). Hold (tIH) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and the first crossing of V REF(DC). If the actual signal is always later than the nominal slewrate line between shaded ’dc to VREF(DC) region’, use nominal slew rate for derating value (see Fig- ure 15). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 16). Although for slow slew rates the total setup time might be nega tive (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in Tables 4 and 5, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. ∆tIS and ∆tIH Derating Values for DDR2-667, DDR2-800 CK, CK Differential Slew Rate 2.0 V/ns 1.5 V/ns 1.0 V/ns Units Notes Command/ Address Slew rate(V/ns) 4.0 +150 +94 +180 +124 +210 +154 ps 1 3.5 +143 +89 +173 +119 +203 +149 ps 1 3.0 +133 +83 +163 +113 +193 +143 ps 1 2.5 +120 +75 +150 +105 +180 +135 ps 1 2.0 +100 +45 +130 +75 +160 +105 ps 1 1.5 +67 +21 +97 +51 +127 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 -5 -14 +25 +16 +55 +46 ps 1 0.8 -13 -31 +17 -1 +47 +29 ps 1 0.7 -22 -54 +8 -24 +38 +6 ps 1 0.6 -34 -83 -4 -53 +26 -23 ps 1 0.5 -60 -125 -30 -95 0 -65 ps 1 0.4 -100 -188 -70 -158 -40 -128 ps 1 0.3 -168 -292 -138 -262 -108 -232 ps 1 0.25 -200 -375 -170 -345 -140 -315 ps 1 0.2 -325 -500 -295 -470 -265 -440 ps 1 0.15 -517 -708 -487 -678 -457 -648 ps 1 0.1 -1000 -1125 -970 -1095 -940 -1065 ps 1

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 38 of 47 K4T51043QG VSS Setup Slew RateSetup Slew Rate Rising SignalFalling Signal ∆TF ∆TR VREF(DC) - VIL(AC)max ∆TF= VIH(AC)min - VREF(DC) ∆TR= VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max nominal slew rate nominal slew rate VREF to ac region VREF to ac region Figure 13 - IIIustration of nominal slew rate for tIS CK CK tIS tIH tIS tIH

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 39 of 47 K4T51043QG VSS Setup Slew Rate Setup Slew Rate Rising Signal Falling Signal ∆TF ∆TR tangent line[VREF(DC) - VIL(AC)max] ∆TF= tangent line[VIH(AC)min - VREF(DC)] ∆TR= tangent tangent VREF to ac region VREF to ac region line line nominal line nominal line Figure 14 - IIIustration of tangent line for tIS CK CK tIS tIH tIS tIH VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 40 of 47 K4T51043QG Hold Slew RateHold Slew Rate Falling SignalRising Signal ∆TR ∆TF VREF(DC) - VIL(DC)max ∆TR= VIH(DC)min - VREF(DC) ∆TF= nominal slew rate nominal slew rate dc to VREF region dc to VREF region Figure 15 - IIIustration of nominal slew rate for tIH CK CK tIS tIH tIS tIH VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max VSS

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 41 of 47 K4T51043QG Hold Slew Rate ∆TF∆TR tangent line [ VIH(DC)min - VREF(DC)] ∆TF= tangent tangent dc to VREF region dc to VREF region line line nominal line nominal line Falling Signal Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ] ∆TR= Rising Signal Figure 16 - IIIustration of tangent line for tIH CK CK tIS tIH tIS tIH VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max VSS

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 42 of 47 K4T51043QG 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, b ut system performance (bus turnaround) will degrade accordingly. 11. MIN ( tCL, tCH) refers to the smaller of the actual clock LO W time and the actual clock HIGH time as provided to the device (i .e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces. 12. tQH = tHP - tQHS, where : tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle. 14. tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 15. The clock frequency is allowed to change during self refresh mode or precharge power-down mode. 16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resis- tance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are mea- sured from tAOFD, which is interpreted differently per speed bi n. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the c lock edge that regis- tered a first ODT LOW if tCK = 5 ns. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges. 18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thes e parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . Figure 17 shows a method to calculate the point when device is no longer driving (tHZ), or beginsdriving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQ) refers to tLZ of the DQS and tLZ(DQS) refers to tLZ of the (U/L/R)DQS and (U/L/R)DQS each treated as single-ended signal. 19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 17 shows a method to calculat e these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. Figure 17 - Method for calculating transitions and endpoints tHZ tRPST end point VOH + x mV VOH + 2x mV VOL + 2x mV VOL + x mV tLZ tRPRE begin point VTT + 2x mV VTT + x mV VTT - x mV VTT - 2x mV tLZ,tRPRE begin point = 2*T1-T2tHZ,tRPST end point = 2*T1-T2

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 44 of 47 K4T51043QG 24. tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency. 25. Input waveform timing with single-ended data strobe enabled MR[b it10] = 1, is referenced from the input signal crossing at the VIH(AC) level to the single-ended data strobe crossing V IH/L(DC) at the start of its transition for a rising signal, and from the input signal crossing at the V IL(AC) level to the single-ended data strobe crossing VIH/L(DC) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between VIL(DC)max and VIH(DC)min. 26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(DC) level to the single-ended data strobe crossing VIH/L(AC) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(DC) level to the single-ended data strobe crossing VIH/L(AC) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between VIL(DC)max and VIH(DC)min. 27. tCKEmin of 3 clocks means CKE must be registered on three cons ecutive positive clock edges. CKE mu st remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 29. These parameters are measured from a command/address signal (CKE, CS , RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respec- tive clock signal (CK/CK) crossing. The spec values are not affected by the amount of cl ock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the set up and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective clock signal (CK/CK) crossing. The spec val- ues are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 31. These parameters are measured from a data signal ((L/U)DM, (L/U )DQ0, (L/U)DQ1, etc.) transition edge to its respective data str obe signal ((L/U/ R)DQS/DQS) crossing. 32. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will supp ort tnRP = RU{tRP / tCK(avg)}, which is in cloc k cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter. 33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set. 34. New units, ’tCK(avg)’ and ’nCK’, are introduced in DDR2-667 and DDR2-800. Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, ’tCK’ is used for both concepts. ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm+2 - T m) is 2 x tCK(avg) + tERR(2per),min. 35. Input clock jitter spec parameter. These parameters and the ones in the table below are referre d to as 'input clock jitter spe c parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. Parameter Symbol DDR2-667 DDR2-800 units Notes Min Max Min Max Clock period jitter tJIT(per) -125 125 -100 100 ps 35 Clock period jitter during DLL locking period tJIT(per,lck) -100 100 -80 80 ps 35 Cycle to cycle clock period jitter tJIT(cc) -250 250 -200 200 ps 35 Cycle to cycle clock period jitter during DLL locking period tJIT(cc,lck) -200 200 -160 160 ps 35 Cumulative error across 2 cycles tERR(2per) -175 175 -150 150 ps 35 Cumulative error across 3 cycles tERR(3per) -225 225 -175 175 ps 35 Cumulative error across 4 cycles tERR(4per) -250 250 -200 200 ps 35 Cumulative error across 5 cycles tERR(5per) -250 250 -200 200 ps 35 Cumulative error across n cycles, n = 6 ... 10, inclusive tERR(6- 10per) -350 350 -300 300 ps 35 Cumulative error across n cycles, n = 11 ... 50, inclusive tERR(11-50per) -450 450 -450 450 ps 35 Duty cycle jitter tJIT(duty) -125 125 -100 100 ps 35

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 45 of 47 K4T51043QG Definitions : - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses. - tJIT(duty) tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the larg- est deviation of any single tCL from tCL(avg). tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} where, tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200} tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200} - tJIT(per), tJIT(per,lck) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing. - tJIT(cc), tJIT(cc,lck) tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles : tJIT(cc) = Max of |tCK i+1 - tCKi| tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing. - tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per) tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg). tERR(nper) = where n = 2 i + n - 1 tCKj j = 1 - n x tCK(avg)∑ for tERR(2per) n = 3 for tERR(3per) n = 4 for tERR(4per) n = 5 for tERR(5per) 6 ≤ n ≤ 10 for tERR(6-10per) 11 ≤ n ≤ 50 for tERR(11-50per) tCK(avg) = where N = 200 N tCKj j = 1 /N∑ tCH(avg) = where N = 200 N tCHj j = 1 /(N x tCK(avg))∑ tCL(avg) = where N = 200 N tCLj j = 1 /(N x tCK(avg))∑

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 46 of 47 K4T51043QG 36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps 37. tHP is the minimum of the absolute half period of the actual in put clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = Min ( tCH(abs), tCL(abs) ), where, tCH(abs) is the minimum of the ac tual instantaneous clock HIGH time; tCL(abs) is the minimum of the actual instantaneous clock LOW time; 38. tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers 39. tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 40. When the device is operated with input clock jitter, this pa rameter needs to be derated by the actual tERR(6-10per) of the inpu t clock. (output derat- ings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps and tERR(6-10per),max = + 293 ps, th en tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 ps - 293 ps = - 693 ps and tDQSCK,max(derated) = tDQSCK,max - tERR (6- 10per),min = 400 ps + 272 ps = + 672 ps. Similarly, tLZ(DQ) for DD R2-667 derates to tLZ(DQ),min(derated) = - 900 ps - 293 ps = - 1193 ps and tLZ(DQ),max(derated) = 450 ps + 272 ps = + 722 ps. 41. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = + 93 ps, then tRPRE,m in(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 ps = + 2178 ps and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 ps = + 2843 ps. 42. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJ IT(duty),min = - 72 ps and tJIT(duty),max = + 93 ps, then tRPST ,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 ps = + 928 ps and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 ps = + 1592 ps. 43. When the device is operated with input cl ock jitter, this parameter needs to be derat ed by { - tJIT(duty),max - tERR(6-10per), max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM ha s tERR(6-10per),min = - 272 ps, tERR(6- 10per),max = + 293 ps, tJIT (duty),min = - 106 ps and tJIT(duty),max = + 94 ps, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max - tERR(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and tAOF,max(derated) = tAOF,max + { - tJIT(duty),min - tERR(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps. Parameter Symbol Min Max Units Absolute clock Period tCK(abs) tCK(avg),min + tJ IT(per),min tCK(avg),max + tJIT(per),max ps Absolute clock HIGH pulse width tCH(abs) tCH(avg),min x tCK(avg),min + tJIT(duty),min tCH(avg),max x tCK(avg),max + tJIT(duty),max ps Absolute clock LOW pulse width tCL(abs) tCL(avg),min x tCK(avg),min + tJIT(duty),min tCL(avg),max x tCK(avg),max + tJIT(duty),max ps

Rev. 1.4 December 2008 DDR2 SDRAM K4T51083QG K4T51163QG 47 of 47 K4T51043QG 44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tC K assumes a tCH, input clock HIGH pulse width of 0.5 relative t o tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH of 0.45, the tAOF,min should be derated by subtracting 0.05 x tCK from it, whereas if an input clock has a worst case tCH of 0.55, the tAOF,max should be derated by adding 0.05 x tCK to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH,min)] x tCK tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH,max) - 0.5] x tCK or tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH,min] x tCK) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH,max - 0.5] x tCK) where tCH,min and tCH,max are the minimum and maximum of tCH actually measured at the DRAM input balls. 45. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nC K assumes a tCH(avg), average input clock HIGH pulse width of 0 .5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH(avg) offset present at th e DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg) tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg) tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg)) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg)) where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls. Note : that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per). However tAC values used in the equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are; tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max } tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min }