K4S643232E-

K4S643232E- SAMSUNG | Alldatasheet

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Technical content

K4S643232E-TE/N CMOS SDRAM - 1 - Rev. 1.4 (Dec. 2001) 2M x 32 SDRAM Revision 1.4 December 2001 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V) Samsung Electronics reserves the right to change products or specification without notice. Extended Temperature 86-TSOP

K4S643232E-TE/N CMOS SDRAM - 2 - Rev. 1.4 (Dec. 2001) Revision 1.4 (December 4, 2001)

• Not supported 90-Ball FBGA Revision 1.3 (October 24, 2001)
• Removed CAS Latency 1 from the spec. Revision 1.2 (August 7, 2001) - Target
• Added CAS Latency 1 Revision 1.1 (July 6, 2001)
• Added K4S643232E-T/S(E/N)50 Revision 1.0 (April 6, 2001) Revision 0.0 (March 21, 2001)
• Initial draft
• Extended temperature (-25 °c ~ 85 °c )
• 3.3V Power supply (VDD &VDDQ)
• Supported 90-ball FBGA as well as 86 - TSOP

Revision History

K4S643232E-TE/N CMOS SDRAM - 3 - Rev. 1.4 (Dec. 2001) The K4S643232E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG ′s high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

• 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle(4K/64ms)
• Extended Temperature range : -25 o C to +85 o C GENERAL DESCRIPTIONFEATURES 512K x 32Bit x 4 Banks Synchronous DRAM

ORDERING INFORMATION

• - E/N : Extended temperature (-25 o C - 85 o C) Part NO. Max Freq. Interface Package K4S643232E-TE/N50 200MHz LVTTL 86 TSOP(II)K4S643232E-TE/N60 166MHz K4S643232E-TE/N70 143MHz FUNCTIONAL BLOCK DIAGRAM Samsung Electronics reserves the right to change products or specification without notice. Bank Select Data Input Register 512K x 32 512K x 32 Sense AMP Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Address Register Row Buffer Refresh Counter Row DecoderCol. Buffer LRAS LCBR LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE DQM LWE LDQM DQi CLK ADD LCAS LWCBR 512K x 32 512K x 32 Timing Register

K4S643232E-TE/N CMOS SDRAM - 4 - Rev. 1.4 (Dec. 2001) PIN CONFIGURATION (Top view) V DD DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 N.C V DD DQM0 WE CAS RAS CS N.C BA0 BA1 A10/AP DQM2 V DD N.C DQ16 V SSQ DQ17 DQ18 V DDQ DQ19 DQ20 V SSQ DQ21 DQ22 V DDQ DQ23 V DD V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 N.C V SS DQM1 N.C N.C CLK CKE DQM3 V SS N.C DQ31 V DDQ DQ30 DQ29 V SSQ DQ28 DQ27 V DDQ DQ26 DQ25 V SSQ DQ24 V SS 86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch) 86 - TSOP

K4S643232E-TE/N CMOS SDRAM - 5 - Rev. 1.4 (Dec. 2001) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down mode. A 0 ~ A 10 Address Row/column addresses are multiplexed on the same pins. Row address : RA 0 ~ RA 10 , Column address : CA 0 ~ CA 7 BA0,1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS , WE active. DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. DQ 0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins. V DD /V SS Power supply/ground Power and ground for the input buffers and the core logic. V DDQ /V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. NC No Connection This pin is recommended to be left No connection on the device.

K4S643232E-TE/N CMOS SDRAM - 6 - Rev. 1.4 (Dec. 2001) DC OPERATING CONDITIONS

• Recommended operating conditions (Voltage referenced to V SS = 0V, T A = -25 o C to +85 o C) Parameter Symbol Min Typ Max Unit Note Supply voltage V DD , V DDQ 3.0 3.3 3.6 V Input logic high voltage V IH 2.0 3.0 V DDQ +0.3 V 1 Input logic low voltage V IL -0.3 0 0.8 V 2 Output logic high voltage V OH 2.4 - - V IOH = -2mA Output logic low voltage V OL - - 0.4 V IOL = 2mA Input leakage current ILI -10 - 10 uA 3 1. V IH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ V IN ≤ V DDQ , Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The V DD condition of K4S643232E-60 is 3.135V ~ 3.6V Notes : ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN , V OUT -1.0 ~ 4.6 V Voltage on V DD supply relative to Vss V DD , V DDQ -1.0 ~ 4.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1 W Short circuit current IOS 50 mA Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : CAPACITANCE (V DD = 3.3V, T A = 23 °C, f = 1MHz, V REF = 1.4V ± 200 mV) Pin Symbol Min Max Unit Clock C CLK - 4 pF RAS , CAS , WE , CS , CKE, DQM C IN - 4.5 pF Address C ADD - 4.5 pF DQ 0 ~ DQ 31 C OUT - 6.5 pF

K4S643232E-TE/N CMOS SDRAM - 7 - Rev. 1.4 (Dec. 2001) (Recommended operating condition unless otherwise noted, T A = -25 o C to +85 o C, V IH(min) /V IL(max) =2.0V/0.8V) Parameter Symbol Test Condition CAS Latency Speed Unit Note -50 -60 -70 Operating Current (One Bank Active) ICC1 Burst Length =1 tRC ≥ tRC (min), t CC ≥ tCC (min), I o = 0mA 3 175 170 155 mA 2 2 150 150 150 Precharge Standby Current in power-down mode ICC2 P CKE ≤ V IL (max), t CC = 15ns 3 mA ICC2 PS CKE & CLK ≤ V IL (max), t CC = ∞ 2 Precharge Standby Current in non power-down mode ICC2 N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 15ns Input signals are changed one time during 30ns 20 mA ICC2 NS CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞ Input signals are stable 10 Active Standby Current in power-down mode ICC3 P CKE ≤ V IL (max), t CC = 15ns 7 mA ICC3 PS CKE ≤ V IL (max), t CC = ∞ 5 Active Standby Current in non power-down mode (One Bank Active) ICC3 N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 15ns Input signals are changed one time during 30ns 55 mA ICC3 NS CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞ Input signals are stable 40 Operating Current (Burst Mode) ICC4 Io = 0 mA, Page Burst All bank Activated, t CCD = t CCD (min) 3 190 180 170 mA 2 2 150 150 150 Refresh Current ICC5 tRC ≥ tRC (min) 3 190 185 165 mA 3 2 160 160 160 Self Refresh Current ICC6 CKE ≤ 0.2V 3 mA 4 450 uA 5 DC CHARACTERISTICS 1. Unless otherwise notes, Input level is CMOS(V IH /V IL =V DDQ /V SSQ ) in LVTTL. 2. Measured with outputs open. 3. Refresh period is 64ms. 4. K4S643232E-E 5. K4S643232E-N Notes :

K4S643232E-TE/N CMOS SDRAM - 8 - Rev. 1.4 (Dec. 2001) AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V , T A = -25 o C to +85 o C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 3.3V 1200 Ω 870 Ω Output 30pF V OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mA Vtt = 1.4V 50 Ω Output 30pF Z0 = 50 Ω (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following ns-unit based AC table. Note : OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note-50 -60 -70 CAS Latency CL 3 2 3 2 3 2 CLK CLK cycle time tCC(min) 5 10 6 10 7 10 ns Row active to row active delay tRRD(min) 2 CLK 1 RAS to CAS delay tRCD(min) 3 2 3 2 3 2 CLK 1 Row precharge time tRP(min) 3 2 3 2 3 2 CLK 1 Row active time tRAS(min) 8 5 7 5 7 5 CLK 1 tRAS(max) 100 us Row cycle time tRC ( min ) 11 7 10 7 10 7 CLK 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to new col.address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 Mode Register Set cycle time tMRS(min) 2 CLK Number of valid output data CAS Latency=3 2 ea 4CAS Latency=2 1 1. The V DD condition of K4S643232E-60 is 3.135V ~ 3.6VNotes :

K4S643232E-TE/N CMOS SDRAM - 9 - Rev. 1.4 (Dec. 2001) 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Note : Parameter Symbol Version Unit -50 -60 -70 Row active to row active delay tRRD(min) 10 12 14 ns RAS to CAS delay tRCD(min) 15 18 20 ns Row precharge time tRP(min) 15 18 20 ns Row active time tRAS(min) 40 42 49 ns tRAS(max) 100 us Row cycle time tRC ( min ) 55 60 70 ns 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol -50 -60 -70 Unit Note Min Max Min Max Min Max CLK cycle time CAS Latency=3 tCC 1000 1000 1000 ns 1 CAS Latency=2 10 10 10 CLK to valid output delay CAS Latency=3 tSAC - 4.5 - 5.5 - 5.5 ns 1, 2 CAS Latency=2 - 6 - 6 - 6 Output data hold time tOH 2 - 2 - 2 - ns 2 CLK high pulse width CAS Latency=3 tCH 2 - 2.5 - 3 - ns 3 CAS Latency=2 3 - 3 - 3 - CLK low pulse width CAS Latency=3 tCL 2 - 2.5 - 3 - ns 3 CAS Latency=2 3 - 3 - 3 - Input setup time CAS Latency=3 tSS 1.5 - 1.5 - 1.75 - ns 3 CAS Latency=2 2.5 - 2.5 - 2.5 - Input hold time tSH 1 - 1 - 1 - ns 3 CLK to output in Low-Z tSLZ 1 - 1 - 1 - ns 2 CLK to output in Hi-Z CAS Latency=3 tSHZ - 4.5 - 5.5 - 5.5 ns - CAS Latency=2 - 6 - 6 - 6

K4S643232E-TE/N CMOS SDRAM - 10 Rev. 1.4 (Dec. 2001) SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn CS RAS CAS WE DQM BA 0,1 A 10 /AP , A 9 ~ A 0 Note Register Mode register set H X L L L L X OP code 1,2 Refresh Auto refresh H H L L L H X X Self refresh Entry L 3 Exit L H L H H H X X H X X X 3 Bank active & row addr. H X L L H H X V Row address Read & column address Auto precharge disable H X L H L H X V L Column address (A 0 ~ A 7 ) Auto precharge enable H 4,5 Write & column address Auto precharge disable H X L H L L X V L Column address (A 0 ~ A 7 ) Auto precharge enable H 4,5 Burst Stop H X L H H L X X 6 Precharge Bank selection H X L L H L X V L X All banks X H Clock suspend or active power down Entry H L H X X X X XL V V V Exit L H X X X X X Precharge power down mode Entry H L H X X X X X L H H H Exit L H H X X X X L V V V DQM H V X 7 No operation command H X H X X X X X L H H H 1. OP Code : Operand code A 0 ~ A 10 & BA 0 ~ BA 1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA 1 : Bank select addresses. If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10 /AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Notes : X

K4S643232E-TE/N CMOS SDRAM - 11 Rev. 1.4 (Dec. 2001) MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address Function A 10 /AP RFU A 9 W.B.L A 8 A 7 TM A 6 A 5 A 4 A 3 A 2 A 1 A 0 CAS Latency BT Burst Length A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 BT = 0 Test Mode Type Mode Register Set Reserved Reserved Reserved Write Burst Length A 9 Length Burst Single Bit Latency Reserved Reserved Reserved Reserved Reserved Reserved CAS Latency Burst Type BT = 1 Burst Length Type Sequential Interleave Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Note : 1. If A 9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle. Full Page Length : x32 (256) BA 0 ~ BA 1 RFU

K4S643232E-TE/N CMOS SDRAM - 12 Rev. 1.4 (Dec. 2001) BURST SEQUENCE (BURST LENGTH = 4) Initial Address Sequential Interleave A 1 A 0 BURST SEQUENCE (BURST LENGTH = 8) Initial Address Sequential Interleave A 1 A 0A 2