K4S641632E-TL1H

K4S641632E SAMSUNG | Alldatasheet

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Rev.0.2 Sept. 2001 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL * Samsung Electronics reserves the right to change products or specification without notice. Revision 0.2 Sept. 2001

Rev.0.2 Sept. 2001 The K4S641632E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG ′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programma- ble burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications.

• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle) GENERAL DESCRIPTIONFEATURES FUNCTIONAL BLOCK DIAGRAM 1M x 16Bit x 4 Banks Synchronous DRAM Samsung Electronics reserves the right to change products or specification without notice. * Bank Select Data Input Register 1M x 16 1M x 16 Sense AMP Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Address Register Row Buffer Refresh Counter Row DecoderCol. Buffer LRAS LCBR LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE L(U)DQM LWE LDQM DQi CLK ADD LCAS LWCBR 1M x 16 1M x 16 Timing Register

ORDERING INFORMATION

Part No. Max Freq. Interface Package K4S641632E-TC50/TL50 200MHz(CL=3) LVTTL 54 TSOP(II) K4S641632E-TC55/TL55 183MHz(CL=3) K4S641632E-TC60/TL60 166MHz(CL=3) K4S641632E-TC70/TL70 143MHz(CL=3) K4S641632E-TC75/TL75 133MHz(CL=3) K4S641632E-TC1H/TL1H 100MHz(CL=2) K4S641632E-TC1L/TL1L 100MHz(CL=3)

Rev.0.2 Sept. 2001 V DD DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 V DD LDQM WE CAS RAS CS BA0 BA1 A10/AP V DD PIN CONFIGURATION (Top view) V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 V SS N.C/RFU UDQM CLK CKE N.C A11 V SS 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A 0 ~ A 11 Address Row/column addresses are multiplexed on the same pins. Row address : RA 0 ~ RA 11 , Column address : CA 0 ~ CA 7 BA 0 ~ BA 1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS , WE active. L(U)DQM Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ 0 ~ 15 Data input/output Data inputs/outputs are multiplexed on the same pins. V DD /V SS Power supply/ground Power and ground for the input buffers and the core logic. V DDQ /V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No connection /reserved for future use This pin is recommended to be left No Connection on the device.

Rev.0.2 Sept. 2001 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN , V OUT -1.0 ~ 4.6 V Voltage on V DD supply relative to Vss V DD , V DDQ -1.0 ~ 4.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1 W Short circuit current IOS 50 mA Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70 °C) Parameter Symbol Min Typ Max Unit Note Supply voltage V DD , V DDQ 3.0 3.3 3.6 V Input logic high voltage V IH 2.0 3.0 V DD +0.3 V 1 Input logic low voltage V IL -0.3 0 0.8 V 2 Output logic high voltage V OH 2.4 - - V IOH = -2mA Output logic low voltage V OL - - 0.4 V IOL = 2mA Input leakage current ILI -10 - 10 uA 3 1. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ V IN ≤ V DDQ . Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The VDD condition of K4S641632E-55/60 is 3.135V~3.6V. Notes : CAPACITANCE (V DD = 3.3V, T A = 23 °C, f = 1MHz, V REF =1.4V ± 200 mV) Pin Symbol Min Max Unit Note Clock C CLK 2.5 4.0 pF 1 RAS , CAS , WE , CS , CKE, DQM C IN 2.5 5.0 pF 2 Address C ADD 2.5 5.0 pF 2 DQ 0 ~ DQ 15 C OUT 4.0 6.5 pF 3 1. -75 only specify a maximum value of 3.5pF 2. -75 only specify a maximum value of 3.8pF 3. -75 only specify a maximum value of 6.0pF Notes :

Rev.0.2 Sept. 2001 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S641632E-TC 4. K4S641632E-TL 5. Unless otherwise noted, input swing IeveI is CMOS(V IH /V IL =V DDQ /V SSQ) Notes : DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T A = 0 to 70 °C) Parameter Symbol Test Condition Version Unit Note - 50 - 55 -60 - 70 - 75 -1H -1L Operating current (One bank active) ICC1 Burst length = 1 t RC ≥ tRC (min) I O = 0 mA 160 150 140 115 110 100 100 mA 1 Precharge standby current in power-down mode ICC2 P CKE ≤ V IL (max), t CC = 10ns 1 mA ICC2 PS CKE & CLK ≤ V IL (max), t CC = ∞ 1 Precharge standby current in non power-down mode ICC2 N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10ns Input signals are changed one time during 20ns 15 mA ICC2 NS CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞ Input signals are stable 6 Active standby current in power-down mode ICC3 P CKE ≤ V IL (max), t CC = 10ns 3 mA ICC3 PS CKE & CLK ≤ V IL (max), t CC = ∞ 3 Active standby current in non power-down mode (One bank active) ICC3 N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10ns Input signals are changed one time during 20ns 25 mA ICC3 NS CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞ Input signals are stable 15 Operating current (Burst mode) ICC4 I O = 0 mA Page burst 4Banks Activated t CCD = 2CLKs 180 170 160 140 135 110 110 mA 1 Refresh current ICC5 tRC ≥ tRC (min) 180 170 160 140 135 125 125 mA 2 Self refresh current ICC6 CKE ≤ 0.2V C 1 mA 3 L 400 uA 4

Rev.0.2 Sept. 2001 AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V , T A = 0 to 70 °C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 3.3V 1200 Ω 870 Ω Output 50pF V OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mA Vtt = 1.4V 50 Ω Output 50pF Z0 = 50 Ω (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit OPERATING AC PARAMETER Notes : (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note Row active to row active delay tRRD (min) 10 11 12 14 15 20 20 ns 1 RAS to CAS delay tRCD (min) 15 16.5 18 20 20 20 20 ns 1 Row precharge time tRP (min) 15 16.5 18 20 20 20 20 ns 1 Row active time tRAS (min) 38.5 38.5 42 49 45 50 50 ns 1 tRAS (max) 100 us Row cycle time tRC (min) 55 55 60 68 65 70 70 ns 1 Last data in to row precharge tRDL (min) 2 CLK 2,5 Last data in to active delay tDAL (min) 2CLK +15ns 2CLK +16.5ns 2CLK +18ns 2CLK +20ns 2CLK +20ns 2CLK +20ns 2CLK +20ns - 5 Last data in to new col. address Delay tCDL (min) 1 CLK 2 Last data in to burst stop tBDL (min) 1 CLK 2 Col. address to col. address delay tCCD (min) 1 CLK 3 Number of valid output data CAS latency=3 2 ea 4 CAS latency=2 - 1 1. The DC/AC Test Output Load of K4S641632E-50/55/60 is 30pF. 2. The VDD condition of K4S641632E-50/55/60 is 3.135V~3.6V. Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev.0.2 Sept. 2001 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Notes : DQ BUFFER OUTPUT DRIVE CHARACTERISTICS Parameter Symbol Condition Min Typ Max Unit Notes Output rise time trh Measure in linear region : 1.2V ~ 1.8V 1.37 4.37 Volts/ns 3 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8 Volts/ns 3 Output rise time trh Measure in linear Output fall time tfh Measure in linear 1. Rise time specification based on 0pF + 50 Ω to V SS , use these values to design to. 2. Fall time specification based on 0pF + 50 Ω to V DD , use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to V SS . Notes : AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol - 50 - 55 - 60 - 70 - 75 - 1H - 1L Unit Note Min Max Min Max Min Max Min Max Min Max Min Max Min Max CLK cycle time CAS latency=3 tCC 1000 5.5 1000 1000 1000 7.5 1000 1000 1000 ns 1 CAS latency=2 - - - - 10 10 12 CLK to valid output delay CAS latency=3 tSAC - 4.5 - 5 5 6 5.4 6 6 ns 1,2 CAS latency=2 - - - - - - 6 6 7 Output data hold time CAS latency=3 tOH 2 2 2.5 3 3 3 3 ns 2 CAS latency=2 - - - - 3 3 3 CLK high pulse width tCH 2 2 2.5 3 2.5 3 3 ns 3 CLK low pulse width tCL 2 2 2.5 3 2.5 3 3 ns 3 Input setup time tSS 1.5 1.5 1.5 2 1.5 2 2 ns 3 Input hold time tSH 1 1 1 1 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 tSHZ 4.5 5 5 6 5.4 6 6 ns CAS latency=2 - - - - 6 6 7

Rev.0.2 Sept. 2001 IOH Characteristics (Pull-up) Voltage 100MHz 133MHz Min 100MHz 133MHz Max 66MHz Min (V) I (mA) I (mA) I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 -0.7 IBIS SPECIFICATION IOL Characteristics (Pull-down) Voltage 100MHz 133MHz Min 100MHz 133MHz Max 66MHz Min (V) I (mA) I (mA) I (mA) 0.0 0.0 0.0 0.0 0.4 27.5 70.2 17.7 0.65 41.8 107.5 26.9 0.85 51.6 133.8 33.3 1.0 58.0 151.2 37.6 1.4 70.7 187.7 46.6 1.5 72.9 194.4 48.0 1.65 75.4 202.5 49.5 1.8 77.0 208.6 50.7 1.95 77.6 212.0 51.5 3.0 80.3 219.6 54.2 3.45 81.4 222.6 54.9 -100 -200 -300 -400 -500 -600 0 30.5 1 1.5 2 2.5 3.5 Voltage m A 250 200 150 100 0 30.5 1 1.5 2 2.5 3.5 Voltage m A 66MHz and 100MHz/133MHz Pull-up 66MHz and 100MHz/133MHz Pull-down IOH Min (100MHz/133MHz) IOH Max (66 and 100MHz/133MHz) IOH Min (66MHz) IOL Min (100MHz/133MHz) IOL Max (100MHz/133MHz) IOL Min (66MHz)

Rev.0.2 Sept. 2001 V DD Clamp @ CLK, CKE, CS , DQM & DQ V DD (V) I (mA) 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 V SS Clamp @ CLK, CKE, CS , DQM & DQ V SS (V) I (mA) -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 0 31 2 Voltage m A I (mA) Voltage m A I (mA) Minimum V DD clamp current (Referenced to V DD ) Minimum V SS clamp current -10 -20 -30 -40 -3 0-2 -1 -50 -60

Rev.0.2 Sept. 2001 SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn CS RAS CAS WE DQM BA 0,1 A 10 /AP A 11, A 9 ~ A 0 Note Register Mode register set H X L L L L X OP code 1,2 Refresh Auto refresh H H L L L H X X Self refresh Entry L 3 Exit L H L H H H X X H X X X 3 Bank active & row addr. H X L L H H X V Row address Read & column address Auto precharge disable H X L H L H X V L Column address (A 0 ~ A 7 ) Auto precharge enable H 4,5 Write & column address Auto precharge disable H X L H L L X V L Column address (A 0 ~ A 7 ) Auto precharge enable H 4,5 Burst stop H X L H H L X X 6 Precharge Bank selection H X L L H L X V L X All banks X H Clock suspend or active power down Entry H L H X X X X XL V V V Exit L H X X X X X Precharge power down mode Entry H L H X X X X X L H H H Exit L H H X X X X L V V V DQM H V X 7 No operation command H X H X X X X X L H H H 1. OP Code : Operand code A 0 ~ A 11 & BA 0 ~ BA 1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA 1 : Bank select addresses. If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10 /AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Notes : X