K4S640432H-TL75

K4S640432H-TC SAMSUNG | Alldatasheet

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SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 * Samsung Electronics reserves the right to change products or specification without notice. Revision 1.8 August 2004 64Mb H-die SDRAM Specification

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004

Revision History

Revision 0.0 (May, 2003) - Target spec release Revision 0.1 (July, 2003) - Preliminary spec release Revision 0.2 (August, 2003) - Modified IBIS characteristic. Revision 1.0 (September, 2003) - Finalized. Revision 1.1 (September, 2003) - Corrected IBIS Specification. Revision 1.2 (October, 2003) - Deleted speed 7C at x4/x8. Revision 1.3 (October, 2003) - Deleted AC parameter notes 5. Revision 1.4 (November, 2003) - Modified Pin Function description. Revision 1.5 (February, 2004) - Corrected typo. Revision 1.6 (March, 2004) - Modified Pin Description. Revision 1.7 (May, 2004) - Added Note 5. sentense of tRDL parameter. Revision 1.8 (August, 2004) - Modified CLK cycle time(tcc) parameter in AC Characteristics. ( If you want use of CL=2 not CL=3, the maximum operating frequency is 100MHz regardless of its speed bin.)

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 Part No. Orgainization Max Freq. Interface Package K4S640432H-TC(L)75 16Mb x 4 133MHz(CL=3) LVTTL 54pin TSOP(II) K4S640832H-TC(L)75 8Mb x 8 133MHz(CL=3) K4S641632H-TC(L)60 4Mb x 16 166MHz(CL=3) K4S641632H-TC(L)70 143MHz(CL=3) K4S641632H-TC(L)75 133MHz(CL=3) The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG ′s high perfor- mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O tr ansactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K cycle) GENERAL DESCRIPTION

FEATURES

Ordering Information

4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks SDRAM Row & Column address configuration Organization Row Address Column Address 16Mx4 A0~A11 A0-A9 8Mx8 A0~A11 A0-A8 4Mx16 A0~A11 A0-A7

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 11.76±0.20 0.463±0.008 0.002

0.05 MIN

0.008 0.21 ± 0.002 ± 0.05 0.020 0.50( ) 0.005 -0.001 +0.003 0.125 -0.035 +0.075 0.400 10.16 0.45~0.75 0.018~0.030 0.010

0.25 TYP

0~8°C #54 #28 #1 #27 0.004

0.10 MAX

0.028 0.71( ) 0.012 0.30 0.0315 0.80 0.047 1.20 MAX0.039 1.00 ± 0.004 ± 0.10 0.891

22.62 MAX

0.875 22.22 ± 0.004 ± 0.10 +0.10 -0.05 +0.004 -0.002 54Pin TSOP(II) Package Dimension Package Physical Dimension

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 FUNCTIONAL BLOCK DIAGRAM Bank Select Data Input Register 4M x 4 / 2M x 8 / 1M x 16 4M x 4 / 2M x 8 / 1M x 16 Sense AMP Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Address Register Row Buffer Refresh Counter Row Decoder Col. Buffer LRAS LCBR LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE L(U)DQM LWE LDQM DQi CLK ADD LCAS LWCBR 4M x 4 / 2M x 8 / 1M x 16 4M x 4 / 2M x 8 / 1M x 16 Timing Register Samsung Electronics reserves the right to change products or specification without notice. *

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 PIN CONFIGURATION (Top view) 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x4 : CA0 ~ CA9, x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7) BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ N Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No connection /reserved for future use This pin is recommended to be left No Connection on the device. x16 x8 x4 x16x8x4 VDD DQ0 VDDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP VDD VSS DQ15 VSSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 V SS N.C/RFU UDQM CLK CKE N.C A11 V SS VDD N.C VDDQ N.C DQ0 VSSQ N.C N.C V DDQ N.C DQ1 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP VDD VSS N.C VSSQ N.C DQ3 V DDQ N.C N.C V SSQ N.C DQ2 V DDQ N.C V SS N.C/RFU DQM CLK CKE N.C A11 V SS VDD DQ0 VDDQ N.C DQ1 VSSQ N.C DQ2 VDDQ N.C DQ3 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP VDD VSS DQ7 VSSQ N.C DQ6 V DDQ N.C DQ5 V SSQ N.C DQ4 V DDQ N.C V SS N.C/RFU DQM CLK CKE N.C A11 V SS

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1W Short circuit current I OS 50 mA Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Note Supply voltage V DD, VDDQ 3.0 3.3 3.6 V Input logic high voltage V IH 2.0 3.0 V DD+0.3 V 1 Input logic low voltage V IL -0.3 0 0.8 V 2 Output logic high voltage V OH 2.4 - - V I OH = -2mA Output logic low voltage V OL -- 0 . 4 V I OL = 2mA Input leakage current I LI -10 - 10 uA 3 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. Notes : CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol Min Max Unit Note Clock C CLK 2.5 4.0 pF 1 RAS, CAS, WE, CS, CKE, DQM C IN 2.5 5.0 pF 2 Address C ADD 2.5 5.0 pF 2 (x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~DQ15) C OUT 4.0 6.5 pF 3

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S6404(08)32H-TC 4. K4S6404(08)32H-TL 5. Unless otherwise noted, input swing IeveI is CMOS(V IH /VIL=VDDQ/VSSQ) Notes : (Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x4, x8) Parameter Symbol Test Condition Version Unit Note Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 75 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 1 mA ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 1 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 15 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 6 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 3 mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 3 Active standby current in non power-down mode (One bank active) I CC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 25 Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks Activated t CCD = 2CLKs 115 mA 1 Refresh current I CC5 tRC ≥ tRC(min) 135 mA 2 Self refresh current I CC6 CKE ≤ 0.2V C1 m A 3 L 400 uA 4 DC CHARACTERISTICS (x4, x8)

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S641632H-TC 4. K4S641632H-TL 5. Unless otherwise noted, input swing IeveI is CMOS(V IH /VIL=VDDQ/VSSQ) Notes : DC CHARACTERISTICS (x16) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x16 only) Parameter Symbol Test Condition Version Unit Note 60 70 75 Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 140 115 110 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 1 mA ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 1 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 15 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 6 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 3 mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 3 Active standby current in non power-down mode (One bank active) I CC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 25 Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks Activated t CCD = 2CLKs 160 140 135 mA 1 Refresh current I CC5 tRC ≥ tRC(min) 160 140 135 mA 2 Self refresh current I CC6 CKE ≤ 0.2V C1 m A 3 L4 0 0 u A 4

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 3.3V 1200Ω 870Ω Output 30pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Vtt = 1.4V 50Ω Output 30pF Z0 = 50Ω (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP . OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note 60 70 75 Row active to row active delay t RRD(min) 12 14 15 ns 1 RAS to CAS delay t RCD(min) 18 20 20 ns 1 Row precharge time t RP(min) 18 20 20 ns 1 Row active time tRAS(min) 42 49 45 ns 1 tRAS(max) 100 us Row cycle time t RC(min) 60 68 65 ns 1 Last data in to row precharge t RDL(min) 2 CLK 2,5 Last data in to Active delay t DAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay t CDL(min) 1 CLK 2 Last data in to burst stop t BDL(min) 1 CLK 2 Col. address to col. address delay t CCD(min) 1 CLK 3 Number of valid output data CAS latency = 3 2 ea 4 CAS latency = 2 1

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Notes :DQ BUFFER OUTPUT DRIVE CHARACTERISTICS Parameter Symbol Condition Min Typ Max Unit Notes Output rise time trh Measure in linear region : 1.2V ~ 1.8V 1.37 4.37 Volts/ns 3 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8 Volts/ns 3 Output rise time trh Measure in linear Output fall time tfh Measure in linear 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS. Notes : AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol 60 70 75 Unit Note Min Max Min Max Min Max CLK cycle time CAS latency=3 tCC 1000 1000 7.5 1000 ns 1 C A S l a t e n c y = 2 1 01 01 0 CLK to valid output delay CAS latency=3 tSAC -5-6- 5 . 4 ns 1,2 C A S l a t e n c y = 2 -6-6-6 Output data hold time CAS latency=3 tOH 2 . 5 -3-3- ns 2 C A S l a t e n c y = 2 3-3-3- CLK high pulse width t CH 2.5 - 3 - 2.5 - ns 3 CLK low pulse width t CL 2.5 - 3 - 2.5 - ns 3 Input setup time t SS 1.5 - 2 - 1.5 - ns 3 Input hold time t SH 1-1- 0 . 8 - n s 3 CLK to output in Low-Z t SLZ 1-1-1- n s 2 CLK to output in Hi-Z CAS latency=3 tSHZ -5-6- 5 . 4 ns C A S l a t e n c y = 2 -6-6-6

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 IOH Characteristics (Pull-up) Voltage 133MHz Min 133MHz Max (V) I (mA) I (mA) 3.45 - -1.68 3.30 - -19.11 3.00 -0.35 -51.87 2.70 -3.75 -90.44 2.50 -6.65 -107.31 1.95 -13.75 -137.9 1.65 -20.55 -173.6 1.40 -26.2 -199.01 0.20 -46.5 -351.68 IBIS SPECIFICATION IOL Characteristics (Pull-down) Voltage 133MHz Min 133MHz Max (V) I (mA) I (mA) 3.45 43.92 155.82 3.30 - - 3.00 43.36 153.72 1.95 41.20 148.40 1.80 40.56 146.02 1.65 39.60 141.75 1.50 38.40 136.08 1.40 37.28 131.39 1.00 30.08 105.84 0.85 26.64 93.66 0.65 21.52 75.25 0.40 14.16 49.14 -100 -200 -300 -400 -500 -600 03 0.5 1 1.5 2 2.5 3.5 Voltage mA 250 200 150 100 03 0.5 1 1.5 2 2.5 3.5 Voltage mA 133MHz Pull-up 133MHz Pull-down IOH Min (133MHz) IOH Max (133MHz) IOL Min (133MHz) IOL Max (133MHz)

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 VDD Clamp @ CLK, CKE, CS, DQM & DQ VDD (V) I (mA) 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 VSS Clamp @ CLK, CKE, CS, DQM & DQ VSS (V) I (mA) -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 03 12 Voltage mA I (mA) Voltage mA I (mA) Minimum VDD clamp current (Referenced to VDD) Minimum VSS clamp current -10 -20 -30 -40 -3 0 -2 -1 -50 -60

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM Rev. 1.8 August 2004 SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11, A9 ~ A0 Note Register Mode register set H X L L L L X OP code 1,2 Refresh Auto refresh H H LL LHX X Self refresh Entry L 3 Exit L H LH HH XX HX XX 3 Bank active & row addr. H X L L H H X V Row address Read & column address Auto precharge disable HX L H L H X V L Column address Auto precharge enable H 4,5 Write & column address Auto precharge disable HX L H L L X V L Column address Auto precharge enable H 4,5 Burst stop H X L H H L X X 6 Precharge Bank selection HX L L H L X VL X All banks XH Clock suspend or active power down Entry H L HX XX X XLV VV Exit L H X X X X X Precharge power down mode Entry H L HX XX X X LH HH Exit L H HX XX X LV VV DQM H X V X 7 No operation command H X HX XX XX LH HH 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Notes :