K4S280432F-UC

K4S280432F-UC SAMSUNG | Alldatasheet

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SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 * Samsung Electronics reserves the right to change products or specification without notice. 128Mb F-die SDRAM Specification Revision 1.2 August 2004

54 TSOP-II with Pb-Free

(RoHS compliant)

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004

Revision History

Revision 1.0 (January, 2004) - First release. Revision 1.1 (May, 2004)

• Added Note 5. sentense of tRDL parameter. Revision 1.2 (August, 2004)
• Corrected typo.

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 Part No. Orgainization Max Freq. Interface Package K4S280432F-UC(L)75 32M x 4 133MHz LVTTL 54pin TSOP(II) K4S280832F-UC(L)75 16M x 8 133MHz LVTTL 54pin TSOP(II) K4S281632F-UC(L)60/75 8M x 16 166MHz LVTTL 54pin TSOP(II) The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG ′s high perfor- mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O tr ansactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
• 54 TSOP(II) Pb-free Package
• RoHS compliant GENERAL DESCRIPTION

FEATURES

8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM

Ordering Information

Row & Column address configuration Organization Row Address Column Address 32Mx4 A0~A11 A0-A9, A11 16Mx8 A0~A11 A0-A9 8Mx16 A0~A11 A0-A8

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 11.76±0.20 0.463±0.008 0.002

0.05 MIN

0.008 0.21 ± 0.002 ± 0.05 0.020 0.50( ) 0.005 -0.001 +0.003 0.125 -0.035 +0.075 0.400 10.16 0.45~0.75 0.018~0.030 0.010

0.25 TYP

0~8°C #54 #28 #1 #27 0.004

0.10 MAX

0.028 0.71( ) 0.012 0.30 0.0315 0.80 0.047 1.20 MAX0.039 1.00 ± 0.004 ± 0.10 0.891

22.62 MAX

0.875 22.22 ± 0.004 ± 0.10 +0.10 -0.05 +0.004 -0.002 54Pin TSOP Package Dimension Package Physical Dimension

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 Bank Select Data Input Register 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 Sense AMP Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Address Register Row Buffer Refresh Counter Row Decoder Col. Buffer LRAS LCBR LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE L(U)DQM LWE LDQM DQi CLK ADD LCAS LWCBR 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 Timing Register * Samsung Electronics reserves the right to change products or specification without notice. FUNCTIONAL BLOCK DIAGRAM

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 VDD N.C VDDQ N.C DQ0 VSSQ N.C N.C V DDQ N.C DQ1 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP V DD PIN CONFIGURATION (Top view) VSS N.C VSSQ N.C DQ3 V DDQ N.C N.C V SSQ N.C DQ2 V DDQ N.C V SS N.C/RFU DQM CLK CKE N.C A11 V SS PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A 0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8) BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ N Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No connection /reserved for future use This pin is recommended to be left No Connection on the device. VDD DQ0 VDDQ N.C DQ1 VSSQ N.C DQ2 VDDQ N.C DQ3 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP V DD VSS DQ7 VSSQ N.C DQ6 V DDQ N.C DQ5 V SSQ N.C DQ4 V DDQ N.C V SS N.C/RFU DQM CLK CKE N.C A11 V SS VDD DQ0 VDDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP V DD VSS DQ15 VSSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 V SS N.C/RFU UDQM CLK CKE N.C A11 V SS x16 x8 x4 x16x8x4 54Pin TSOP (400mil x 875mil) (0.8 mm Pin pitch)

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss V DD, VDDQ -1.0 ~ 4.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1W Short circuit current I OS 50 mA Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Note Supply voltage V DD, VDDQ 3.0 3.3 3.6 V Input logic high voltage V IH 2.0 3.0 V DD+0.3 V 1 Input logic low voltage V IL -0.3 0 0.8 V 2 Output logic high voltage V OH 2.4 - - V I OH = -2mA Output logic low voltage V OL -- 0 . 4 V I OL = 2mA Input leakage current I LI -10 - 10 uA 3 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. Notes : CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol Min Max Unit Note Clock C CLK 2.5 3.5 pF RAS, CAS, WE, CS, CKE, DQM C IN 2.5 3.8 pF Address C ADD 2.5 3.8 pF (x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15) C OUT 4.0 6.0 pF

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 DC CHARACTERISTICS (x4, x8) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Test Condition Version Unit Note -75 Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 90 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 2 mA ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 20 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 5 mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 5 Active standby current in non power-down mode (One bank active) I CC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 25 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 110 mA 1 Refresh current I CC5 tRC ≥ tRC(min) 200 mA 2 Self refresh current I CC6 CKE ≤ 0.2V C2 m A 3 L 800 uA 4 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S2804(08)32F-UC 4. K4S2804(08)32F-UL 5. Unless otherwise noted, input swing IeveI is CMOS(V IH /VIL=VDDQ/VSSQ) Notes :

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 DC CHARACTERISTICS (x16) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Test Condition Version Unit Note -60 -75 Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 130 100 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 2 mA ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 20 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 5 mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 5 Active standby current in non power-down mode (One bank active) I CC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 25 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 150 140 mA 1 Refresh current I CC5 tRC ≥ tRC(min) 220 200 mA 2 Self refresh current I CC6 CKE ≤ 0.2V C2 m A 3 L 800 uA 4 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S281632F-UC 4. K4S281632F-UL 5. Unless otherwise noted, input swing IeveI is CMOS(V IH /VIL=VDDQ/VSSQ) Notes :

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Value Unit Input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 3.3V 1200Ω 870Ω Output 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Vtt = 1.4V 50Ω Output 50pF Z0 = 50Ω (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit OPERATING AC PARAMETER Notes : (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note - 60 (x16 only) - 75 Row active to row active delay t RRD(min) 12 15 ns 1 RAS to CAS delay t RCD(min) 18 20 ns 1 Row precharge time t RP(min) 18 20 ns 1 Row active time tRAS(min) 42 45 ns 1 tRAS(max) 100 us Row cycle time t RC(min) 60 65 ns 1 Last data in to row precharge t RDL(min) 2 CLK 2,5 Last data in to Active delay t DAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay t CDL(min) 1 CLK 2 Last data in to burst stop t BDL(min) 1 CLK 2 Col. address to col. address delay t CCD(min) 1 CLK 3 Number of valid output data CAS latency=3 2 ea 4 CAS latency=2 - 1 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP .

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS Parameter Symbol Condition Min Typ Max Unit Notes Output rise time trh Measure in linear region : 1.2V ~ 1.8V 1.37 4.37 Volts/ns 3 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8 Volts/ns 3 Output rise time trh Measure in linear Output fall time tfh Measure in linear 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS. Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Notes : AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol - 60 (x16 only) - 75 Unit Note Min Max Min Max CLK cycle time CAS latency=3 tCC 1000 7.5 1000 ns 1 CAS latency=2 - 10 CLK to valid output delay CAS latency=3 tSAC 55 . 4 ns 1,2 CAS latency=2 - 6 Output data hold time CAS latency=3 tOH 2.5 3 ns 2 CAS latency=2 - 3 CLK high pulse width t CH 2.5 2.5 ns 3 CLK low pulse width t CL 2.5 2.5 ns 3 Input setup time t SS 1.5 1.5 ns 3 Input hold time t SH 10 . 8 n s 3 CLK to output in Low-Z t SLZ 11 n s 2 CLK to output in Hi-Z CAS latency=3 tSHZ 55 . 4 ns CAS latency=2 - 6

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 IOH Characteristics (Pull-up) Voltage 100MHz 133MHz Min 100MHz 133MHz Max 66MHz Min (V) I (mA) I (mA) I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 -0.7 IBIS SPECIFICATION IOL Characteristics (Pull-down) Voltage 100MHz 133MHz Min 100MHz 133MHz Max 66MHz Min (V) I (mA) I (mA) I (mA) 0.0 0.0 0.0 0.0 0.4 27.5 70.2 17.7 0.65 41.8 107.5 26.9 0.85 51.6 133.8 33.3 1.0 58.0 151.2 37.6 1.4 70.7 187.7 46.6 1.5 72.9 194.4 48.0 1.65 75.4 202.5 49.5 1.8 77.0 208.6 50.7 1.95 77.6 212.0 51.5 3.0 80.3 219.6 54.2 3.45 81.4 222.6 54.9 -100 -200 -300 -400 -500 -600 03 0.5 1 1.5 2 2.5 3.5 Voltage mA 250 200 150 100 03 0.5 1 1.5 2 2.5 3.5 Voltage mA 66MHz and 100MHz/133MHz Pull-up 66MHz and 100MHz/133MHz Pull-down IOH Min (100MHz/133MHz) IOH Max (66 and 100MHz/133MHz) IOH Min (66MHz) IOL Min (100MHz/133MHz) IOL Max (100MHz/133MHz) IOL Min (66MHz)

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 VDD Clamp @ CLK, CKE, CS, DQM & DQ VDD (V) I (mA) 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 VSS Clamp @ CLK, CKE, CS, DQM & DQ VSS (V) I (mA) -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 03 12 Voltage mA I (mA) mA I (mA) Minimum VDD clamp current (Referenced to VDD) Minimum VSS clamp current -10 -20 -30 -40 -3 0 -2 -1 -50 -60 Voltage

SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Rev. 1.2 August 2004 SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A0 ~ A9, A11, Note Register Mode register set H X L L L L X OP code 1,2 Refresh Auto refresh H H LL LHX X Self refresh Entry L 3 Exit L H LH HH XX HX XX 3 Bank active & row addr. H X L L H H X V Row address Read & column address Auto precharge disable HX L H L H X V L Column address Auto precharge enable H 4,5 Write & column address Auto precharge disable HX L H L L X V L Column address Auto precharge enable H 4,5 Burst stop H X L H H L X X 6 Precharge Bank selection HX L L H L X VL X All banks XH Clock suspend or active power down Entry H L HX XX X XLV VV Exit L H X X X X X Precharge power down mode Entry H L HX XX X X LH HH Exit L H HX XX X LV VV DQM H X V X 7 No operation command H X HX XX XX LH HH 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Notes :