K4R271669A

K4R271669A SAMSUNG | Alldatasheet

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K4R271669A/K4R441869A Direct RDRAM ™ Rev. 1.02 Jan. 2000 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAM TM Revision 1.02 January 2000

K4R271669A/K4R441869A Direct RDRAM ™ Rev. 1.02 Jan. 2000

Revision History

Version 1.0 (July 1999) - Preliminary - Based on the Rambus Datasheet 1.0 ver. Version 1.01 (October 1999) On page 1 - Delete the part numbers of low power On page 32 - Add the data of CNFGA Register @ Figure 28 On page 33 - Add the data of CNFGB Register @ Figure 29 and correct the CORG4..0 field of CNFGB register On page 44 - Add the Tj value from TBD to Max. 100 °C @ Table 18 On page 46 - Add the Θ JC value from TBD to 0.2 °C/Watt @ Table 20 On page 55 - Add the current values for 356MHz and 300MHz RDRAM device Version 1.02 (January 2000) * Change the part number of RDRAM Component according to New Code System since ’00.Jan.1st On page 45 - Reduce swing of V IH,CMOS & V IL,CMOS from “ 0.5V CMOS ±0.6V “ to “ 0.5V CMOS ±0.4V “ - Relax tS1 from 1.0ns to “ 1.25ns “ ( But, Keep tH1 as 1.0ns)

K4R271669A/K4R441869A Direct RDRAM ™ Rev. 1.02 Jan. 2000 Overview The Rambus Direct RDRAM ™ is a general purpose high- performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 128/144Mbit Direct Rambus DRAMs (RDRAM  ) are extremely high-speed CMOS DRAMs organized as 8M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz to 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes). The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's thirty-two b anks support up to four simultaneous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking, and x18 organization. The two data bits in the x18 organiza- tion are general and can be used for additional storage and bandwidth or for error correction.

Features

♦ Highest sustained bandwidth per DRAM device - 1.6GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simul- taneously at full bandwidth data rates ♦ Low latency features - Write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - Interleaved transactions ♦ Advanced power management: - Direct RDRAM operates from a 2.5 volt supply - Multiple low power states allows flexibility in power consumption versus time to transition to active state - Power-down self-refresh ♦ Organization: 1Kbyte pages and 32 banks, x 16/18 - x18 organization allows ECC configurations or increased storage/bandwidth - x16 organization for low cost applications ♦ Uses Rambus Signaling Level (RSL) for up to 800MHz operation The 128/144Mbit Direct RDRAMs are offered in a CSP h orizontal package suitable for desktop as well as low- profile add-in card and mobile applications. Key Timing Parameters/Part Numbers a.The “ 32s " designation indicates that this RDRAM core is composed of 32 banks which use a "split" bank architecture. b.The “ N “ designator indicates the normal package and the “ M “ indicates the mirrored package. c.The “ C “ designator indicates that this RDRAM core uses Normal Power Self Refresh. Figure 1: Direct RDRAM CSP Package Organization Speed Part Number Bin I/O Freq. MHz tRAC (Row Access Time) ns 256Kx16x32s a -CG6 600 53.3 K4R271669A-N b (M)C c G6 -CK7 711 45 K4R271669A-N(M)CK7 -CK8 800 45 K4R271669A-N(M)CK8 256Kx18x32s -CG6 600 53.3 K4R441869A-N(M)CG6 -CK7 711 45 K4R441869A-N(M)CK7 -CK8 800 45 K4R441869A-N(M)CK8 a. Normal Package b. Mirrored Package K4R xxxx 69A- N xxx SAMSUNG 001 M K4R xxxx 69A- M xxx SAMSUNG 001

K4R271669A/K4R441869A Direct RDRAM ™ Rev. 1.02 Jan. 2000 Pinouts and Definitions Normal Package This table shows the pin assignments of the normal RDRAM package. Mirrored Package This table shows the pin assignments of the mirrored RDRAM package. Table 1 : a. Center-Bonded Device (Top View For Normal Package)

12 GND VDD VDD GND

10 DQA7 DQA4 CFM CFMN RQ5 RQ3 DQB0 DQB4 DQB7

9 GND VDD GND GNDa VDD GND VDD VDD GND

8 CMD DQA5 DQA2 VDDa RQ6 RQ2 DQB1 DQB5 SIO1

5 SCK DQA6 DQA1 VREF RQ7 RQ1 DQB2 DQB6 SIO0

4 VCMOS GND VDD GND GND VDD GND GND VCMOS

3 DQA8 * DQA3 DQA0 CTMN CTM RQ4 RQ0 DQB3 DQB8 *

1 GND VDD VDD GND

Table 2: a.Center-Bonded Device (Top View For Mirrored Package)

10 DQA8 * DQA3 DQA0 CTMN CTM RQ4 RQ0 DQB3 DQB8 *

9 VCMOS GND VDD GND GND VDD GND GND VCMOS

8 SCK DQA6 DQA1 VREF RQ7 RQ1 DQB2 DQB6 SIO0

5 CMD DQA5 DQA2 VDDa RQ6 RQ2 DQB1 DQB5 SIO1

4 GND VDD GND GNDa VDD GND VDD VDD GND

3 DQA7 DQA4 CFM CFMN RQ5 RQ3 DQB0 DQB4 DQB7

For mirrored package, pin #1(ROW 1, COL A) is located at the A1 postion on the top side and the A1 position is marked by the alphabet “ M “ . Chip Top View * DQA8/DQB8 are ju st used for 144Mb RDRAM. These two pins are NC(No Connection) in 128Mb RDRAM. b. Top marking example of normal package b. Top marking example of mirrored package COL ROW COL ROW For normal package, pin #1(ROW 1, COL A) is located at the A1 position on the top side and the A1 position is marked by the marker “ “ . K4R xxxx 69A- N xxx SAMSUNG 001 M K4R xxxx 69A- M xxx SAMSUNG 001

K4R271669A/K4R441869A Direct RDRAM ™ Rev. 1.02 Jan. 2000 Table 3: Pin Description Signal I/O Type # of Pins Description SIO1,SIO0 I/O CMOS a 2 Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power man- agement. CMD I CMOS a 1 Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management . SCK I CMOS a 1 Serial clock input. Clock source used for reading from and writing to the control registers V DD 10 Supply voltage for the RDRAM core and interface logic. V DDa 1 Supply voltage for the RDRAM analog circuitry. V CMOS 2 Supply voltage for CMOS input/output pins . GND 13 Ground reference for RDRAM core and interface. GNDa 1 Ground reference for RDRAM analog circuitry. DQA8..DQA0 I/O RSL b 9 Data byte A. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. DQA8 is not used by RDRAMs with a x16 organization. CFM I RSL b 1 Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. CFMN I RSL b 1 Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity V REF 1 Logic threshold reference voltage for RSL signals CTMN I RSL b 1 Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. CTM I RSL b 1 Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. RQ7..RQ5 or ROW2..ROW0 I RSL b 3 Row access control. Three pins containing control and address information for row accesses. RQ4..RQ0 or COL4..COL0 I RSL b 5 Column access control. Five pins containing control and address information for column accesses. DQB8.. DQB0 I/O RSL b 9 Data byte B. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. DQB8 is not used by RDRAMs with a x16 organization. Total pin count per package 62 a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero. b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.

K4R271669A/K4R441869A Direct RDRAM ™ Rev. 1.02 Jan. 2000 Figure 2: 128/144 M bit Direct RDRAM Block Diagram Bank 31 DQA8 .. DQA0 1 : 8 D e m u x8 : 1 M u x W r it e B u f f e r 1:8 Demux Write Buffer 8:1 Mux Bank 30 Bank 29 Bank 1 8 Bank 1 7 Bank 16 Bank 15 Bank 14 Bank 13 Bank 1 Bank 0 SAmp DQB8 ..D QB0 1:8 Demux 1:8 Demux Packet Decode 953 ROW2 .. ROW0 COL4 .. COL0CTM CTMN CFM CFMN SCK,CMD RCLKTCLK Control Registers DCCOP CBC MAMBDXXOP BXD R RROP B R 88655555695511 AV M S Write Buffer MatchMatch Mux Match DEVID 512x64x144 Internal DQB Data Path Column Decode & Mask DM REFR Row Decode Mux ACT RD, WR Power Modes DRAM Core Mux XOP Decode PRE X PRE C 9 99 9 9 PRE R COLX COLC COLM S IO0,SIO1 Sense Amp Internal DQA Data Path Packet Decode ROWA ROWR RC LK RC LK R C L KT C L K RCLKTCLK RQ7. .RQ5 or RQ4..RQ0 or SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp SAmp 32x 72 S A m p S A m p S A m p S A m p 1 4 /1 5 S A m p 1 5 S A m p 1 3 /1 4 S A m p 1 6 /1 7 S A m p 1 7 /1 8 S A m p 1 6 S A m p 2 9 /3 0 S A m p 3 0 /3 1 S A m p 3 1 32x 72 32x 72 Bank 2

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Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 General Description Figure2 is a block diagram of the 128/144 Mbit Direct RDRAM. It consists of two major blocks: a “ core “ block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to 1.6GB/s. Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of Figure2. They are used to write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last refreshed row. Most importantly, the five bit DEVID speci- fies the device address of the RDRAM on the Channel. Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-From- Master) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins. DQA,DQB Pins: These 18 pins carry read (Q) and write (D) data across the Channel. They are multiplexed/de-multi- plexed from/to two 72-bit data paths (running at one-eighth the data frequency) inside the RDRAM. Banks: The 16Mbyte core of the RDRAM is divided into 32 0.5Mbyte banks, each organized as 512 rows, with each row containing 64 dualocts, and each dualoct containing 16 bytes. A dualoct is the smallest unit of data that can be addressed. Sense Amps: The RDRAM contains 34 sense amps. Each sense amp consists of 512 bytes of fast storage (256 for DQA and 256 for DQB) and can hold one-half of one row of one bank of the RDRAM. The sense amp may hold any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM (except for numbers 0, 15, 30, and 31). This intro- duces the restriction that adjacent banks may not be simulta- neously accessed. RQ Pins: These pins carry control and address informa- tion. They are broken into two groups. RQ7..RQ5 are also called ROW2..ROW0, and are used primarily for controlling are used primarily for controlling column accesses. ROW Pins: The principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the RDRAM. These pins are de-multiplexed into a 24-bit ROWA (row-activate) or ROWR (row-operation) packet. COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multi- plexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet. ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 256 byte sense amps for DQA and two for DQB). PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be acti- vated. RD Command: The RD (read) command causes one of the 64 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel. WR Command: The WR (write) command causes a dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 64 dualocts of one of the sense amps during a subse- quent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turn- around. PREC Precharge: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR, except that a precharge operation is performed at the end of the column operation. These commands provide a second mechanism for performing precharge. PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge.

Direct RDRAM ™ Rev. 1.02 Jan. 2000 K4R271669A/K4R441869A Packet Format Figure3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table4 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM. The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and ROWR packet provide a five bit device address and a five bit bank address. An ROWA packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field. Note the use of the “ RsvX ” notation to reserve bits for future address field extension. Figure3 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table5 describes the fields which comprise these packets. The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and is also framed by the S bit. The 23 bit COLC packet has a five bit device address, a five bit bank address, a six bit column address, and a four bit opcode. The COLC packet specifies a read or write command, as well as some power management commands. The remaining 17 bits are interpreted as a COLM (M=1) or COLX (M=0) packet. A COLM packet is used for a COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from a time t RTR earlier. An COLX packet may be used to specify an indepen- dent precharge command. It contains a five bit device address, a five bit bank address, and a five bit opcode. The COLX packet may also be used to specify some house- keeping and power management commands. The COLX packet is framed within a COLC packet but is not otherwise associated with any other packet. Table 4: Field Description for ROWA Packet and ROWR Packet Field Description DR4T,DR4F Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit. DR3..DR0 Device address for ROWA or ROWR packet. BR4..BR0 Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM. AV Selects between ROWA packet (AV=1) and ROWR packet (AV=0). R8..R0 Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM. ROP10..ROP0 Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions. Table 5: Field Description for COLC Packet, COLM Packet, and COLX Packet Field Description S Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets. DC4..DC0 Device address for COLC packet. BC4..BC0 Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0’s). C5..C0 Column address for COLC packet. RsvC denotes bits ignored by the RDRAM. COP3..COP0 Opcode field for COLC packet. Specifies read, write, precharge, and power management functions. M Selects between COLM packet (M=1) and COLX packet (M=0). DX4..DX0 Device address for COLX packet. BX4..BX0 Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’s). XOP4..XOP0 Opcode field for COLX packet. Specifies precharge, I OL control, and power management functions.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Figure 3: Packet Formats CTM/CFM COL4 COL3 COL2 COL1 COL0 T 8 T 9 T 10 T 11 T 12 T 13 T 14 T 15 T 8 T 9 T 10 T 11 T 0 T 1 T 2 T 3 T 0 T 1 T 2 T 3 S=1 a MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2 CTM/CFM ROW2 DR4T DR2 BR0 BR3 RsvR R8 R5 ROW1 DR4F DR1 BR1 BR4 RsvR R7 R4 R1 ROW0 DR3 DR0 BR2 RsvB AV=1 R6 R3 R0 ACT a0 PREX d0MSK (b1) PRER c0 WR b1 CTM/CFM COL4 DC4 S=1 RsvC COL3 DC3 C5 C3 COL2 DC2 COP1 RsvB BC2 C2 DC1 COP0 BC4 BC1 C1 DC0 COP2 COP3 BC3 BC0 C0 COL1 COL0 CTM/CFM ROW2 ROW1 ROW0 CTM/CFM COL4 COL3 COL2 COL1 COL0 ROP2DR4T DR2 BR0 BR3 ROP10 ROP8 ROP5 DR4F DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1 DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0 S=1 b DX4 XOP4 RsvB BX1 M=0 DX3 XOP3 BX4 BX0 DX2 XOP2 BX3 DX1 XOP1 BX2 DX0 XOP0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 ROWA Packet COLM Packet COLC Packet COLX Packet ROWR Packet CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 t PACKET a The COLM is associated with a previous COLC, and is aligned with the present COLC, indicated by the Start bit (S=1) position. b The COLX is aligned with the present COLC, indicated by the Start bit (S=1) position.

Direct RDRAM ™ Rev. 1.02 Jan. 2000 K4R271669A/K4R441869A Field Encoding Summary Table6 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed. Table7 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps. An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-acti- vate) command is similar to the ACT command, except the row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-precharge) command is identical to a PRER command. The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM and are described in more detail in “ Power state manage- ment “ on page 38. The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in “ Current and Temperature Control “ on page 43. Table 6: Device Field Encodings for ROWA Packet and ROWR Packet DR4T DR4F Device Selection Device Match signal (DM) 1 1 All devices (broadcast) DM is set to 1 0 1 One device selected DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0 1 0 One device selected DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0 0 0 No packet present DM is set to 0 Table 7: ROWA Packet and ROWR Packet Field Encodings DM a AV ROP10..ROP0 Field Name Command Description 10 9 8 7 6 5 4 3 2:0 0 - - - - - - - - - --- - No operation. 1 0 1 1 0 0 0 x c x x 000 PRER Precharge bank BR4..BR0 of this device. Increment REFR if BR4..BR0 = 1111 (see Figure50). 1 0 1 0 1 0 1 0 0 x 000 REFP Precharge bank BR4..BR0 of this device after REFA (see Figure50). 1 0 x x 0 0 0 0 1 x 000 PDNR Move this device into the powerdown (PDN) power state (see Figure47). 1 0 x x 0 0 0 1 0 x 000 NAPR Move this device into the nap (NAP) power state (see Figure47). 1 0 x x 0 0 0 1 1 x 000 NAPRC Move this device into the nap (NAP) power state conditionally 1 0 x x x x x x x 0 000 ATTN b Move this device into the attention (ATTN) power state (see Figure45). 1 0 x x x x x x x 1 000 RLXR Move this device into the standby (STBY) power state (see Figure46). 1 0 0 0 0 0 0 0 0 x 001 TCAL Temperature calibrate this device (see Figure52). 1 0 0 0 0 0 0 0 0 x 010 TCEN Temperature calibrate/enable this device (see Figure52). 1 0 0 0 0 0 0 0 0 0 000 NOROP No operation. b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1). c. An “ x “ entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP va lue (011000111000).

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Table8 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure17 for a more detailed description. The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to combining RD/WR with a PREC. RLXC (relax) performs a power mode transi- tion. See “ Power State Management “ on page 38. Table9 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be specified without consuming control bandwidth on the ROW pins. It is also used for the CAL(calibrate) and SAM (sample) current control commands (see “ Current and Temperature Control “ on page 43), and for the RLXX power mode command (see “ Power State Management “ on page 38). Table 8: COLC Packet Field Encodings S DC4.. DC0 (select device) a COP3..0 Name Command Description 0 ---- ----- - No operation. 1 /= (DEVID4 ..0) ----- - Retire write buffer of this device. 1 == (DEVID4 ..0) x000 b NOCOP Retire write buffer of this device. 1 == (DEVID4 ..0) x010 RSRV Reserved, no operation. 1 == (DEVID4 ..0) x110 RSRV Reserved, no operation. 1 == (DEVID4 ..0) 1xxx RLXC Move this device into the standby (STBY) power state (see Figure46). a. “ /= “ means not equal, “ == “ means equal. b. An “ x “ entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value(1001). Table 9: COLM Packet and COLX Packet Field Encodings M DX4 .. DX0 (selects device) XOP4..0 Name Command Description 1 ---- - MSK MB/MA bytemasks used by WR/WRA. 0 /= (DEVID4 ..0) - - No operation. 0 == (DEVID4 ..0) 00000 NOXOP No operation. 0 == (DEVID4 ..0) x10x0 CAL Calibrate (drive) I OL current for this device (see Figure51). 0 == (DEVID4 ..0) x11x0 CAL/SAM Calibrate (drive) and Sample ( update) I OL current for this device (see Figure51). 0 == (DEVID4 ..0) xxx10 RLXX Move this device into the standby (STBY) power state (see Figure46). 0 == (DEVID4 ..0) xxxx1 RSRV Reserved, no operation. a. An “ x “ entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (100 10).

Direct RDRAM ™ Rev. 1.02 Jan. 2000 K4R271669A/K4R441869A DQ Packet Timing Figure4 shows the timing relationship of COLC packets with D and Q data packets. This document uses a specific convention for measuring time intervals between packets: all packets on the ROW and COL pins (ROWA, ROWR, COLC, COLM, COLX) use the trailing edge of the packet as a reference point, and all packets on the DQA/DQB pins (D and Q) use the leading edge of the packet as a reference point. An RD or RDA command will transmit a dualoct of read data Q a time t CAC later. This time includes one to five cycles of round-trip propagation delay on the Channel. The tCAC parameter may be programmed to a one of a range of values ( 8, 9, 10, 11, or 12 t CYCLE ). The value chosen depends upon the number of RDRAM devices on the Channel and the RDRAM timing bin. See Figure39 for more information. A WR or WRA command will receive a dualoct of write data D a time t CWD later. This time does not need to include the round-trip propagation time of the Channel since the COLC and D packets are traveling in the same direction. When a Q packet follows a D packet (shown in the left half of the figure), a gap (t CAC -t CWD ) will automatically appear between them because the t CWD value is always less than the tCAC value. There will be no gap between the two COLC packets with the WR and RD commands which schedule the D and Q packets. When a D packet follows a Q packet (shown in the right half of the figure), no gap is needed between them because the tCWD value is less than the t CAC value. However, , a gap of tCAC -t CWD or greater must be inserted between the COLC packets with the RD WR commands by the controller so the Q and D packets do not overlap. COLM Packet to D Packet Mapping Figure5 shows a write operation initiated by a WR command in a COLC packet. If a subset of the 16 bytes of write data are to be written, then a COLM packet is trans- mitted on the COL pins a time t RTR after the COLC packet containing the WR command. The M bit of the COLM packet is set to indicate that it contains the MA and MB mask fields. Note that this COLM packet is aligned with the COLC packet which causes the write buffer to be retired. See Figure17 for more details. If all 16 bytes of the D data packet are to be written, then no further control information is required. The packet slot that would have been used by the COLM packet (t RTR after the COLC packet) is available to be used as an COLX packet. This could be used for a PREX precharge command or for a housekeeping command (this case is not shown). The M bit is not asserted in an COLX packet and causes all 16 bytes of the previous WR to be written unconditionally. Note that a RD command will never need a COLM packet, and will always be able to use the COLX packet option (a read opera- tion has no need for the byte-write-enable control bits). Figure5 also shows the mapping between the MA and MB fields of the COLM packet and bytes of the D packet on the DQA and DQB pins. Each mask bit controls whether a byte of data is written (=1) or not written (=0). Figure 4: Read (Q) and Write (D) Data Packet - Timing for t CAC = 8, 9, 10, 11, or 12 t CYCLE CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 RD b1 Q (a1) WR a1 D (a1) t CWD RD c1 Q (a1) t CAC -t CWD This gap on the DQA/DQB pins appears automatically This gap on the COL pins must be inserted by the controller t CAC t CAC WR d1 D (d1)D (d1) t CAC -t CWD t CWDWR d1 Q (c1)

• • •
• • • WR d1 WR d1• • • D (d1)Q (c1) D (d1)Q (c1)
• • •
• • • Q (a1) Q (a1)Q (b1)Q (b1) WR d1 D (d1)Q (c1)

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Figure 5: Mapping Between COLM Packet and D Packet for WR Command CTM/CFM COL4 COL3 COL2 COL1 COL0 T 17 T 18 T 19 T 20 MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2 CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 MSK (a1) retire (a1)WR a1 D (a1) ACT b0ACT a0 Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a3 = {Da,Ba} t RTR T 19 T 20 T 21 T 22 CTM/CFM DQB8 DQB7 DQB1 DQB0 DB71DB8 DB17 DB26 DB35 DB45 DB53 DB62 DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70 DB1 DB10 DB19 DB28 DB37 DB46 DB55 DB64 DB0 DB9 DB18 DB27 DB36 DB45 DB54 DB63 COLM Packet PRER a2 DQA8 DQA7

• • • DQA1 DQA0 D Packet MB0 DA71DA8 DA17 DA26 DA35 DA45 DA53 DA62 DA7 DA16 DA25 DA34 DA44 DA52 DA61 DA70 DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64 DA0 DA9 DA18 DA27 DA36 DA45 DA54 DA63 MA0 MB1 MA1 MB2 MA2 MB3 MA3 MB4 MA4 MB5 MA5 MB6 MA6 MB7 MA7
• • • t CWD Each bit of the MB7..MB0 field controls writing (=1) or no writing (=0) of the indicated DB bits when the M bit of the COLM packet is one. Each bit of the MA7..MA0 field controls writing (=1) or no writing (=0) of the indicated DA bits when the M bit of the COLM packet is one. When M=1, the MA and MB fields control writing of individual data bytes. When M=0, all data bytes are written unconditionally.

Direct RDRAM ™ Rev. 1.02 Jan. 2000 K4R271669A/K4R441869A ROW-to-ROW Packet Interaction Figure6 shows two packets on the ROW pins separated by an interval t RRDELAY which depends upon the packet contents. No other ROW packets are sent to banks {Ba,Ba+1,Ba-1} between packet “ a ” and packet “ b ” unless noted otherwise. Table10 summarizes the t RRDELAY values for all possible cases. Cases RR1 through RR4 show two successive ACT commands. In case RR1, there is no restriction since the ACT commands are to different devices. In case RR2, the tRR restriction applies to the same device with non-adjacent banks. Cases RR3 and RR4 are illegal (as shown) since bank Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1 is inserted, t RRDELAY is t RC (t RAS to the PRER command, and t RP to the next ACT). Cases RR5 through RR8 show an ACT command followed by a PRER command. In cases RR5 and RR6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. In cases RR7 and RR8, the t RAS restriction means the activated bank must wait before it can be precharged. Cases RR9 through RR12 show a PRER command followed by an ACT command. In cases RR9 and RR10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. RR10a and RR10b depend upon whether a bracketed bank (Ba ±1) is precharged or activated. In cases RR11 and RR12, the same and adjacent banks must all wait t RP for the sense amp and bank to precharge before being activated. Figure 6: ROW-to-ROW Packet Interaction- Timing CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 TT 17 T 18 T 19 Transaction a: ROPa Transaction b: ROPb a0 = {Da,Ba,Ra} b0= {Db,Bb,Rb} t RRDELAY ROPa a0 ROPb b0 Table 10: ROW-to-ROW Packet Interaction - Rules Case # ROPa Da Ba Ra ROPb Db Bb Rb t RRDELAY Example RR1 ACT Da Ba Ra ACT /= Da xxxx x..x tPACKET Figure11 RR2 ACT Da Ba Ra ACT == Da /= {Ba,Ba+1,Ba-1} x..x tRR Figure11 RR3 ACT Da Ba Ra ACT == Da == {Ba+1,Ba-1} x..x tRC - illegal unless PRER to Ba/Ba+1/Ba-1 Figure10 RR4 ACT Da Ba Ra ACT == Da == {Ba} x..x tRC - illegal unless PRER to Ba/Ba+1/Ba-1 Figure10 RR5 ACT Da Ba Ra PRER /= Da xxxx x..x tPACKET Figure11 RR6 ACT Da Ba Ra PRER == Da /= {Ba,Ba+1,Ba-1} x..x tPACKET Figure11 RR7 ACT Da Ba Ra PRER == Da == { Ba+1,Ba-1} x..x tRAS Figure10 RR8 ACT Da Ba Ra PRER == Da == {Ba} x..x tRAS Figure15 RR9 PRER Da Ba Ra ACT /= Da xxxx x..x tPACKET Figure12 RR10 PRER Da Ba Ra ACT == Da /= {Ba,Ba ±1,Ba ±2} x..x tPACKET Figure12 RR10a PRER Da Ba Ra ACT == Da == {Ba+2} x..x tPACKET /t RP if Ba+1 is precharged/activated. RR10b PRER Da Ba Ra ACT == Da == {Ba-2} x..x tPACKET /t RP if Ba-1 is precharged/activated. RR11 PRER Da Ba Ra ACT == Da == {Ba+1,Ba-1} x..x tRP Figure10 RR12 PRER Da Ba Ra ACT == Da == {Ba} x..x tRP Figure10 RR13 PRER Da Ba Ra PRER /= Da xxxx x..x tPACKET Figure12 RR14 PRER Da Ba Ra PRER == Da /= {Ba,Ba+1,Ba-1} x..x tPP Figure12 RR15 PRER Da Ba Ra PRER == Da == {Ba+1,Ba-1} x..x tPP Figure12 RR16 PRER Da Ba Ra PRER == Da == Ba x..x tPP Figure12

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 ROW-to-ROW Interaction - contin- ued Cases RR13 through RR16 summarize the combinations of two successive PRER commands. In case RR13 there is no restriction since two devices are addressed. In RR14, t PP applies, since the same device is addressed. In RR15 and RR16, the same bank or an adjacent bank may be given repeated PRER commands with only the t PP restriction. Two adjacent banks can’t be activate simultaneously. A precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). If bank Ba is activate and a PRER is directed to Ba, then bank Ba will be precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If bank Ba+1 is activate and a PRER is directed to Ba, then bank Ba+1 will be precharged along with sense amps Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a PRER is directed to Ba, then bank Ba-1 will be precharged along with sense amps Ba/Ba-1 and Ba-1/Ba-2. A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The inter- action rules of the NAPR, NAPRC, PDNR, RLXR, ATTN, TCAL, and TCEN commands are discussed in later sections (see Table7 for cross-ref). ROW-to-COL Packet Interaction Figure7 shows two packets on the ROW and COL pins. They must be separated by an interval t RCDELAY which depends upon the packet contents. Table11 summarizes the tRCDELAY values for all possible cases. Note that if the COL packet is earlier than the ROW packet, it is considered a COL-to-ROW packet interaction. Cases RC1 through RC5 summarize the rules when the ROW packet has an ACT command. Figure15 and Figure16 show examples of RC5 - an activation followed by a read or write. RC4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). In cases RC1, RC2, and RC3, there is no inter- action of the ROW and COL packets. Cases RC6 through RC8 summarize the rules when the ROW packet has a PRER command. There is either no inter- action (RC6 through RC9) or an illegal situation with a read or write of a precharged bank (RC9). The COL pins can also schedule a precharge operation with a RDA, WRA, or PREC command in a COLC packet or a PREX command in a COLX packet. The constraints of these precharge operations may be converted to equivalent PRER command constraints using the rules summarized in Figure14. Figure 7: ROW-to-COL Packet Interaction- Timing CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 TT 17 T 18 T 19 Transaction a: ROPa Transaction b: COPb a0 = {Da,Ba,Ra} b1= {Db,Bb,Cb1} t RCDELAY ROPa a0 COPb b1 Table 11: ROW-to-COL Packet Interaction - Rules Case # ROPa Da Ba Ra COPb Db Bb Cb1 t RCDELAY Example RC1 ACT Da Ba Ra NOCOP,RD,retire /= Da xxxx x..x 0 RC2 ACT Da Ba Ra NOCOP == Da xxxx x..x 0 RC3 ACT Da Ba Ra RD,retire == Da /= {Ba,Ba+1,Ba-1} x..x 0 RC4 ACT Da Ba Ra RD,retire == Da == {Ba+1,Ba-1} x..x Illegal RC5 ACT Da Ba Ra RD,retire == Da == Ba x..x tRCD Figure15 RC6 PRER Da Ba Ra NOCOP,RD,retire /= Da xxxx x..x 0 RC7 PRER Da Ba Ra NOCOP == Da xxxx x..x 0 RC8 PRER Da Ba Ra RD,retire == Da /= {Ba,Ba+1,Ba-1} x..x 0 RC9 PRER Da Ba Ra RD,retire == Da == {Ba+1,Ba-1} x..x Illegal

Direct RDRAM ™ Rev. 1.02 Jan. 2000 K4R271669A/K4R441869A COL-to-COL Packet Interaction Figure8 shows three arbitrary packets on the COL pins. Packets “ b ” and “ c ” must be separated by an interval tCCDELAY which depends upon the command and address values in all three packets. Table12 summarizes the tCCDELAY values for all possible cases. Cases CC1 through CC5 summarize the rules for every situ- ation other than the case when COPb is a WR command and COPc is a RD command. In CC3, when a RD command is followed by a WR command, a gap of t CAC -t CWD must be inserted between the two COL packets. See Figure4 for more explanation of why this gap is needed. For cases CC1, CC2, CC4, and CC5, there is no restriction (t CCDELAY is tCC ). In cases CC6 through CC10, COPb is a WR command and COPc is a RD command. The t CCDELAY value needed between these two packets depends upon the command and address in the packet with COPa. In particular, in case CC6 when there is WR-WR-RD command sequence directed to the same device, a gap will be needed between the packets with COPb and COPc. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Figure18 (right) provides a more detailed explanation of this case. In case CC10, there is a RD-WR-RD sequence directed to the same device. If a prior write to the same device is unre- tired when COPa is issued, then a gap will be needed between the packets with COPb and COPc as in case CC6. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Cases CC7, CC8, and CC9 have no restriction (t CCDELAY is tCC ). For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation PREC to take place. This precharge may be converted to an equiva- lent PRER command on the ROW pins using the rules summarized in Figure14. Figure 8: COL-to-COL Packet Interaction- Timing CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 TT 17 T 18 T 19 COPa a1 Transaction a: COPa COPc c1 Transaction b: COPb Transaction c: COPc a1 = {Da,Ba,Ca1} b1 = {Db,Bb,Cb1} c1 = {Dc,Bc,Cc1} t CCDELAY COPb b1 Table 12: COL-to-COL Packet Interaction - Rules Case # COPa Da Ba Ca1 COPb Db Bb Cb1 COPc D c Bc Cc1 t CCDELAY Example

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 COL-to-ROW Packet Interaction Figure9 shows arbitrary packets on the COL and ROW pins. They must be separated by an interval t CRDELAY which depends upon the command and address values in the packets. Table13 summarizes the t CRDELAY value for all possible cases. Cases CR1, CR2, CR3, and CR9 show no interaction between the COL and ROW packets, either because one of the commands is a NOP or because the packets are directed to different devices or to non-adjacent banks. Case CR4 is illegal because an already-activated bank is to be re-activated without being precharged Case CR5 is illegal because an adjacent bank can’t be activated or precharged until bank Ba is precharged first. In case CR6, the COLC packet contains a RD command, and the ROW packet contains a PRER command for the same bank. The t RDP parameter specifies the required spacing. Likewise, in case CR7, the COLC packet causes an auto- matic retire to take place, and the ROW packet contains a PRER command for the same bank. The t RTP parameter specifies the required spacing. Case CR8 is labeled “ Hazardous ” because a WR command should always be followed by an automatic retire before a precharge is scheduled. Figure19 shows an example of what can happen when the retire is not able to happen before the precharge. For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation to take place. This precharge may converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure14. A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The inter- action rules of the NAPR, PDNR, and RLXR commands are discussed in a later section. Figure 9: COL-to-ROW Packet Interaction- Timing CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 TT 17 T 18 T 19 Transaction a: COPa Transaction b: ROPb a1= {Da,Ba,Ca1} b0= {Db,Bb,Rb} t CRDELAY ROPb b0 COPa a1 Table 13: COL-to-ROW Packet Interaction - Rules Case # COPa Da Ba Ca1 ROPb Db Bb Rb t CRDELAY Example CR1 NOCOP Da Ba Ca1 x..x xxxxx xxxx x..x 0 CR2 RD/WR Da Ba Ca1 x..x /= Da xxxx x..x 0 CR3 RD/WR Da Ba Ca1 x..x == Da /= {Ba,Ba+1,Ba-1} x..x 0 CR4 RD/WR Da Ba Ca1 ACT == Da == {Ba} x..x Illegal CR5 RD/WR Da Ba Ca1 ACT == Da == {Ba+1,Ba-1} x..x Illegal CR6 RD Da Ba Ca1 PRER == Da == {Ba,Ba+1,Ba-1} x..x tRDP Figure15 CR7 retire a Da Ba Ca1 PRER == Da == {Ba,Ba+1,Ba-1} x..x tRTP Figure16 CR8 WR b Da Ba Ca1 PRER == Da == {Ba,Ba+1,Ba-1} x..x 0 Figure19 CR9 xxxx Da Ba Ca1 NOROP xxxxx xxxx x..x 0 a. This is any command which permits the write buffer of device Da to retire (see Table8). “ Ba ” is the bank address in the write buffer. b. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure19.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Figure12 shows examples of the PRER-to-PRER (RR13, RR14) and PRER-to-ACT (RR9, RR10) command spacings from Table10. The RR15 and RR16 cases (PRER-to-PRER to same or adjacent banks) are not shown, but are similar to RR14. In general, the commands in ROW packets may be spaced an interval t PACKET apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device. Row and Column Cycle Description Activate: A row cycle begins with the activate (ACT) opera- tion. The activation process is destructive; the act of sensing the value of a bit in a bank’s storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value. Restore: Because the activation process is destructive, a hidden operation called restore is automatically performed. The restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank. Read/Write: While the restore operation takes place, the sense amp may be read (RD) and written (WR) using column operations. If new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical. Precharge: When both the restore operation and the column operations are completed, the sense amp and bank are precharged (PRE). This leaves them in the proper state to begin another activate operation. Intervals: The activate operation requires the interval tRCD,MIN to complete. The hidden restore operation requires the interval t RAS,MIN - t RCD,MIN to complete. Column read and write operations are also performed during the t RAS,MIN - t RCD,MIN interval (if more than about four column opera- tions are performed, this interval must be increased). The precharge operation requires the interval t RP,MIN to complete. Adjacent Banks: An RDRAM with an “ s ” designation (256Kx32sx16/18) indicates it contains “ split banks ” . This means the sense amps are shared between two adjacent banks. The only exception is that sense amp 0, 15, 30, and 31are not shared. When a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. These two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations. For example (referring to the block diagram of Figure2), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 512 bytes loaded into each sense amp from the 1Kbyte row - 256 bytes to the DQA side and 256 bytes to the DQB side). While this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing. Figure 12: Row Packet Examples CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 PRER a0 ACT b0 t PACKET PRER c0 a0 = {Da,Ba,Ra} b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc} Different Device Any Bank Same Device Non-adjacent Bank RR13 RR14 PRER a0PRER a0PRER b0 ACT c0 b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc} Different Device Any Bank Same Device Non-adjacent Bank RR9 RR10 PRER a0 c0 = {Da,Ba+1Rc}Same Device Same Bank RR16 c0 = {Da,Ba,Rc}Same Device Adjacent Bank RR15 t PP t PACKET t PACKET

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Precharge Mechanisms Figure13 shows an example of precharge with the ROWR packet mechanism. The PRER command must occur a time tRAS after the ACT command, and a time t RP before the next ACT command. This timing will serve as a baseline against which the other precharge mechanisms can be compared. Figure14 (top) shows an example of precharge with a RDA command. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these commands is a RDA, which causes the bank to auto- matically precharge when the final read has finished. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time t OFFP from the COLC packet with the RDA command. The RDA command should be treated as a RD command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Figure14 (middle) shows an example of precharge with a WRA command. As in the RDA example, a bank is acti- vated with an ROWA packet on the ROW pins. Then, two dualocts are written with WR commands in COLC packets on the COL pins. The second of these commands is a WRA, which causes the bank to automatically precharge when the final write has been retired. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time t OFFP from the COLC packet that causes the automatic retire. The WRA command should be treated as a WR command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Note that the automatic retire is triggered by a COLC packet a time t RTR after the COLC packet with the WR command unless the second COLC contains a RD command to the same device. This is described in more detail in Figure17. Figure14 (bottom) shows an example of precharge with a PREX command in an COLX packet. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these COLC packets includes an COLX packet with a PREX command. This causes the bank to precharge with timing equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time t OFFP from the COLX packet with the PREX command. Figure 13: Precharge via PRER Command in ROWR Packet CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 ACT a0 PRER a5 t RAS t RC a0 = {Da,Ba,Ra} a5 = {Da,Ba} b0 = {Da,Ba,Rb} t RP ACT b0

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Figure 14: Offsets for Alternate Precharge Mechanisms CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 RD a1 ACT a0 RD a2 Q (a2)Q (a1) ACT b0 MSK (a2)MSK (a1) retire (a1) t OFFP WR a1 D (a2)D (a1) ACT b0ACT a0 Transaction a: RD a0 = {Da,Ba,Ra} a5 = {Da,Ba} COLC Packet: RDA Precharge Offset COLC Packet: WDA Precharge Offset Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a5 = {Da,Ba} COLX Packet: PREX Precharge Offset RD a3 Q (a4)Q (a3) RDA a4 PRER a5 The RDA precharge is equivalent to a PRER command here t OFFP PRER a5 The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here WRA a2 retire (a2) t RTR a3 = {Da,Ba,Ca3} a4 = {Da,Ba,Ca4} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} RD a1 ACT a0 RD a2 Q (a2)Q (a1) ACT b0 t OFFP Transaction a: RD a0 = {Da,Ba,Ra} a5 = {Da,Ba} RD a3 Q (a4)Q (a3) PRER a5 The PREX precharge command is equivalent to a PRER command here a3 = {Da,Ba,Ca3} a4 = {Da,Ba,Ca4} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} RD a4 PREX a5

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Read Transaction - Example Figure15 shows an example of a read transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time t RCD later a RD a1 command is issued in a COLC packet. Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the RD command includes device, bank, and column address (abbreviated as a1). A time t CAC after the RD command the read data dualoct Q(a1) is returned by the device. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time t CC after the first COLC packet on the COL pins a second is issued. It contains a RD a2 command. The a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time t CAC after the second RD command a second read data dualoct Q(a2) is returned by the device. Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time t RAS or more after the original ACT command (the activation operation in any DRAM is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the t RAS interval). The PRER command must also occur a time t RDP or more after the last RD command. Note that the t RDP value shown is greater than the t RDP,MIN specification in Table22. This transaction example reads two dualocts, but there is actually enough time to read three dualocts before t RDP becomes the limiting parameter rather than t RAS . If four dualocts were read, the packet with PRER would need to shift right (be delayed) by one t CYCLE (note - this case is not shown). Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time t RC or more after the first ACT command and a time t RP or more after the PRER command. This ensures that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a. Figure 15: Read Transaction Example CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 RD a1 ACT a0 PRER a3 RD a2 Q (a2) t RCD t CAC t CC Q (a1) ACT b0 t RAS t RC t RP Transaction a: RD a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a3 = {Da,Ba} t CAC t RDP Transaction b: xx b0 = {Da,Ba,Rb}

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Write Transaction - Example Figure16 shows an example of a write transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time t RCD -t RTR later a WR a1 command is issued in a COLC packet (note that the t RCD interval is measured to the end of the COLC packet with the first retire command). Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the WR command includes device, bank, and column address (abbreviated as a1). A time t CWD after the WR command the write data dualoct D(a1) is issued. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time t CC after the first COLC packet on the COL pins a second COLC packet is issued. It contains a WR a2 command. The a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time t CWD after the second WR command a second write data dualoct D(a2) is issued. A time t RTR after each WR command an optional COLM packet MSK (a1) is issued, and at the same time a COLC packet is issued causing the write buffer to automatically retire. See Figure17 for more detail on the write/retire mechanism. If a COLM packet is not used, all data bytes are unconditionally written. If the COLC packet which causes the write buffer to retire is delayed, then the COLM packet (if used) must also be delayed. Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time t RAS or more after the original ACT command (the activation operation in any DRAM is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the t RAS interval). A PRER a3 command is issued in an ROWR packet on the ROW pins. The PRER command must occur a time t RTP or more after the last COLC which causes an automatic retire. Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time t RC or more after the first ACT command and a time t RP or more after the PRER command. This ensures that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a. Figure 16: Write Transaction Example CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 MSK (a2) retire (a2) MSK (a1) retire (a1)WR a1 PRER a3 WR a2 D (a2) t RCD D (a1) ACT b0 t RC t RP ACT a0 t CWD Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a3 = {Da,Ba} t CC t CWD t RTR t RAS t RTR t RTP Transaction b: xx b0 = {Da,Ba,Rb}

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Write/Retire - Examples The process of writing a dualoct into a sense amp of an RDRAM bank occurs in two steps. The first step consists of transporting the write command, write address, and write data into the write buffer. The second step happens when the RDRAM automatically retires the write buffer (with an optional bytemask) into the sense amp. This two-step write process reduces the natural turn-around delay due to the internal bidirectional data pins. Figure17 (left) shows an example of this two step process. The first COLC packet contains the WR command and an address specifying device, bank and column. The write data dualoct follows a time t CWD later. This information is loaded into the write buffer of the specified device. The COLC packet which follows a time t RTR later will retire the write buffer. The retire will happen automatically unless (1) a COLC packet is not framed (no COLC packet is present and the S bit is zero), or (2) the COLC packet contains a RD command to the same device. If the retire does not take place at time t RTR after the original WR command, then the device continues to frame COLC packets, looking for the first that is not a RD directed to itself. A bytemask MSK(a1) may be supplied in a COLM packet aligned with the COLC that retires the write buffer at time t RTR after the WR command. The memory controller must be aware of this two-step write/retire process. Controller performance can be improved, but only if the controller design accounts for several side effects. Figure17 (right) shows the first of these side effects. The first COLC packet has a WR command which loads the address and data into the write buffer. The third COLC causes an automatic retire of the write buffer to the sense amp. The second and fourth COLC packets (which bracket the retire packet) contain RD commands with the same device, bank and column address as the original WR command. In other words, the same dualoct address that is written is read both before and after it is actually retired. The first RD returns the old dualoct value from the sense amp before it is overwritten. The second RD returns the new dualoct value that was just written. Figure18 (left) shows the result of performing a RD command to the same device in the same COLC packet slot that would normally be used for the retire operation. The read may be to any bank and column address; all that matters is that it is to the same device as the WR command. The retire operation and MSK(a1) will be delayed by a time tPACKET as a result. If the RD command used the same bank and column address as the WR command, the old data from the sense amp would be returned. If many RD commands to the same device were issued instead of the single one that is shown, then the retire operation would be held off an arbi- trarily long time. However, once a RD to another device or a WR or NOCOP to any device is issued, the retire will take place. Figure18 (right) illustrates a situation in which the controller wants to issue a WR-WR-RD COLC packet sequence, with all commands addressed to the same device, but addressed to any combination of banks and columns. Figure 17: Normal Retire (left) and Retire/Read Ordering (right) CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20T 17 T 21T 18 T 22T 19 T 23 Transaction a: WR a1= {Da,Ba,Ca1} D (a1) WR a1 CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20T 17 T 21T 18 T 22T 19 T 23 Transaction a: WR Transaction b: RD a1= {Da,Ba,Ca1} b1= {Da,Ba,Ca1} retire (a1) MSK (a1) t RTR t CWD D (a1) WR a1 retire (a1) MSK (a1) t RTR RD b1 RD c1 Q (b1) t CWD Transaction c: RD c1= {Da,Ba,Ca1} t CAC This RD gets the old data This RD gets the new dataRetire is automatic here unless: t CAC (1) No COLC packet (S=0) or (2) COLC packet is RD to device Da Q (c1)

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Interleaved Write - Example Figure20 shows an example of an interleaved write transac- tion. Transactions similar to the one presented in Figure16 are directed to non-adjacent banks of a single RDRAM. This allows a new transaction to be issued once every t RR interval rather than once every t RC interval (four times more often). The DQ data pin efficiency is 100% with this sequence. With two dualocts of data written per transaction, the COL, DQA, and DQB pins are fully utilized. Banks are precharged using the WRA autoprecharge option rather than the PRER command in an ROWR packet on the ROW pins. In this example, the first transaction is directed to device Da and bank Ba. The next three transactions are directed to the same device Da, but need to use different, non-adjacent banks Bb, Bc, Bd so there is no bank conflict. The fifth transaction could be redirected back to bank Ba without interference, since the first transaction would have completed by then (t RC has elapsed). Each transaction may use any value of row address (Ra, Rb, ..) and column address (Ca1, Ca2, Cb1, Cb2, ...). Interleaved Read - Example Figure21 shows an example of interleaved read transac- tions. Transactions similar to the one presented in Figure15 are directed to non-adjacent banks of a single RDRAM. The address sequence is identical to the one used in the previous write example. The DQ data pins efficiency is also 100%. The only difference with the write example (aside from the use of the RD command rather than the WR command) is the use of the PREX command in a COLX packet to precharge the banks rather than the RDA command. This is done because the PREX is available for a readtransaction but is not available for a masked write transaction. Interleaved RRWW - Example Figure22 shows a steady-state sequence of 2-dualoct RD/RD/WR/WR.. transactions directed to non-adjacent banks of a single RDRAM. This is similar to the interleaved write and read examples in Figure20 and Figure21 except that bubble cycles need to be inserted by the controller at read/write boundaries. The DQ data pin efficiency for the example in Figure22 is 32/42 or 76%. If there were more RDRAMs on the Channel, the DQ pin efficiency would approach 32/34 or 94% for the two-dualoct RRWW sequence (this case is not shown). In Figure22, the first bubble type t CBUB1 is inserted by the controller between a RD and WR command on the COL pins. This bubble accounts for the round-trip propagation delay that is seen by read data, and is explained in detail in Figure4. This bubble appears on the DQA and DQB pins as tDBUB1 between a write data dualoct D and read data dualoct Q. This bubble also appears on the ROW pins as t RBUB1 . Figure 20: Interleaved Write Transaction with Two Dualoct Data Length CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 ACT a0 MSK (b2) WRA c2 MSK (b1) WR c1WR b1 MSK (a1) WRA b2 MSK (a2) D (b2)D (b1) ACT b0 ACT c0 ACT d0 ACT e0 D (a2)D (a1) WR d1 MSK (c1) D(c1) ACT f0 WR d2 MSK (c2) WR e1 MSK (d1) D (c2) D (d1) WR e2 MSK (d2) D (z2)D (z1)D (x2) D (y1) D (y2) MSK (z2) WRA a2 MSK (z1) WR a1WR z1 MSK (y1) WRA z2 MSK (y2) Q (d1) t RCD t CWD t RC Transaction e can use the same bank as transaction a t RR f3 = {Da,Ba+2}Transaction f: WR f0 = {Da,Ba+2,Rf} f1 = {Da,Ba+2,Cf1} f2= {Da,Ba+2,Cf2} e3 = {Da,Ba}Transaction e: WR e0 = {Da,Ba,Re} e1 = {Da,Ba,Ce1} e2= {Da,Ba,Ce2} d3 = {Da,Ba+6}Transaction d: WR d0 = {Da,Ba+6,Rd} d1 = {Da,Ba+6,Cd1} d2= {Da,Ba+6,Cd2} c3 = {Da,Ba+4}Transaction c: WR c0 = {Da,Ba+4,Rc} c1 = {Da,Ba+4,Cc1} c2= {Da,Ba+4,Cc2} b3 = {Da,Ba+2}Transaction b: WR b0 = {Da,Ba+2,Rb} b1 = {Da,Ba+2,Cb1} b2= {Da,Ba+2,Cb2} a3 = {Da,Ba}Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2= {Da,Ba,Ca2} z3 = {Da,Ba+6}Transaction z: WR z0 = {Da,Ba+6,Rz} z1 = {Da,Ba+6,Cz1} z2= {Da,Ba+6,Cz2} y3 = {Da,Ba+4}Transaction y: WR y0 = {Da,Ba+4,Ry} y1 = {Da,Ba+4,Cy1} y2= {Da,Ba+4,Cy2}

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Control Register Packets Table 14 summarizes the formats of the four packet types for control register transactions. Table 15 summarizes the fields that are used within the packets. Figure25 shows the transaction format for the SETR, CLRR, and SETF commands. These transactions consist of a single SRQ packet, rather than four packets like the SWR and SRD commands. The same framing sequence on the CMD input is used, however. These commands are used during initialization prior to any control register read or write transactions. Figure 25: SETR, CLRR,SETF Transaction SCK CMD SIO0 T 20 SRQ packet - SETR/CLRR/SETF 1111 00000000...00000000 SRQ packet - SETR/CLRR/SETF 0000 SIO1 T 4 The packet is repeated from SIO0 to SIO1 Table 14: Control Register Packet Formats SCK Cycle SIO0 or SIO1 for SRQ SIO0 or SIO1 for SA SIO0 or SIO1 for SINT SIO0 or SIO1 for SD SCK Cycle SIO0 or SIO1 for SRQ SIO0 or SIO1 for SA SIO0 or SIO1 for SINT SIO0 or SIO1 for SD 0 rsrv rsrv 0 SD15 8 SOP1 SA7 0 SD7 1 rsrv rsrv 0 SD14 9 SOP0 SA6 0 SD6 2 rsrv rsrv 0 SD13 10 SBC SA5 0 SD5 3 rsrv rsrv 0 SD12 11 SDEV4 SA4 0 SD4 4 rsrv SA11 0 SD11 12 SDEV3 SA3 0 SD3

5 SDEV5 SA10 0 SD10 13 SDEV2 SA2 0 SD2

6 SOP3 SA9 0 SD9 14 SDEV1 SA1 0 SD1

7 SOP2 SA8 0 SD8 15 SDEV0 SA0 0 SD0

Table 15: Field Description for Control Register Packets Field Description rsrv Reserved. Should be driven as “ 0 ” by controller. 0010 - SETR. Set Reset bit, all control registers assume their reset values. a 16 t SCYCLE delay until CLRR command. 0100 - SETF. Set fast (normal) clock mode. 4 t SCYCLE delay until next command. 1011 - CLRR. Clear Reset bit, all control registers retain their reset values. a 4 t SCYCLE delay until next command. 1111 - NOP. No serial operation. 0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings. tion is directed. SBC Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection. SA11..SA0 Serial address. Selects which control register of the selected RDRAM is read or written. SD15..SD0 Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Initialization Initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. The controller prepares the RDRAM sub-system for normal Channel operation by using a sequence of control register transactions on the serial CMOS pins.The following steps outline the sequence seen by the various memory subsystem components (including the RDRAM compo- nents) during initialization. This sequence is available in the form of reference code.

1.0 Start Clocks - This step calculates the proper clock

frequencies for PClk (controller logic), SynClk (RAC block), RefClk (DRCG component), CTM (RDRAM component), and SCK ( SIO block).

2.0 RAC Initialization - This step causes the INIT block to

generate a sequence of pulses which resets the RAC, performs RAC maintainance operations, and measures timing intervals in order to ensure clock stability.

3.0 RDRAM Initialization - This stage performs most of

the steps needed to initialize the RDRAMs. The rest are are carried out through the SIO block interface. ο 3.1/3.2 SIO Reset - This reset operation is performed before any SIO control register read or write transactions. It clears six registers (TEST34, CCA, CCB, SKIP, TEST78, and TEST79) and places the INIT register into a special state (all bits cleared except SRP and SDEVID fields are set to ones). ο 3.3 Write TEST77 Register - The TEST77 register must be explicitly written with zeros before any other registers are read or written. ο 3.4 Write TCYCLE Register - The TCYCLE register is written with the cycle time tCYCLE of the CTM clock (for Channel and RDRAMs) in units of 64ps. The tCYCLE value is determined in stage 1.0. ο 3.5 Write SDEVID Register - The SDEVID (serial device identification) register of each RDRAM is written with a unique address value so that directed SIO read and write transactions can be performed. This address value increases from 0 to 31 according to the distance an RDRAM is from the ASIC component on the SIO bus ( the closest RDRAM is address 0). ο 3.6 Write DEVID Register - The DEVID (device iden- tification) register of each RDRAM is written with a unique address value so that directed memory read and write transactions can be performed. This address value increases from 0 to 31. The DEVID value is not neces- sarily the same as the SDEVID value. RDRAMs are sorted into regions of the same core configuration (number of bank, row, and column address bits and core type). ο 3.7 Write PDNX, PDNXA Registers - The PDNX and PDNXA registers are written with values that are used to measure the timing intervals connected with an exit from the PDN (powerdown) power state. ο 3.8 Write NAPX Register - The NAPX register is written with values that are used to measure the timing intervals connected with an exit from the NAP power state. ο 3.9 Write TPARM Register - The TPARM register is written with values which determine the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The values written set each RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0. ο 3.10 Write TCDLY1 Register - The TCDLY1 register is written with values which determine the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The values written set each RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0. ο 3.11 Write TFRM Register - The TFRM register is written with a value that is related to the t RCD parameter for the system. The t RCD parameter is the time interval between a ROW packet with an activate command and the COL packet with a read or write command. ο 3.12 SETR/CLRR - Each RDRAM is given a SETR command and a CLRR command through the SIO block. This sequence performs a second reset operation on the RDRAMs. Figure 26: SIO Reset Sequence SCK CMD SIO0 T 16 0000000000000000 00000000...00000000 0000000000000000 1100 SIO1 The packet is repeated from SIO0 to SIO1 0000 T 0

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 ο 3.13 Write CCA and CCB Register - These registers are written with a value halfway between their minimum and maximum values. This shortens the time needed for the RDRAMs to reach their steady-state current control values in stage 5.0. ο 3.14 Powerdown Exit - The RDRAMs are in the PDN power state at this point. A broadcast PDNExit command is performed by the SIO block to place the RDRAMs in the RLX (relax) power state in which they are ready to receive ROW packets. ο 3.15 SETF - Each RDRAM is given a SETF command through the SIO block. One of the operations performed by this step is to generate a value for the AS (autoskip) bit in the SKIP register and fix the RDRAM to a particular read domain.

4.0 Controller Configuration - This stage initializes the

controller block. Each step of this stage will set a field of the ConfigRMC[63:0] bus to the appropriate value. Other controller implementations will have similar initialization requirements, and this stage may be used as a guide. ο 4.1 Initial Read Data Offsets - The configRMC bus is written with a value which determines the time interval between a COL packet with a memory read command and the Q packet with the read data on the Channel. The value written sets RMC.d1 to the minimum value permitted for the system. This will be adjusted later in stage 6.0. ο 4.2 Configure Row/Column Timing - This step deter- mines the values of the t RAS,MIN , t RP,MIN , t RC,MIN , tRCD,MIN , t RR,MIN , and t PP,MIN RDRAM timing parame- ters that are present in the system. The ConfigRMC bus is written with values that will be compatible with all RDRAM devices that are present. ο 4.3 Set Refresh Interval - This step determines the values of the t REF,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. ο 4.4 Set Current Control Interval - This step deter- mines the values of the t CCTRL,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with value that will be compatible with all RDRAM devices that are present. ο 4.5 Set Slew Rate Control Interval - This step deter- mines the values of the t TEMP,MAX RDRAM timing parameter that are present in the system. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present. ο 4.6 Set Bank/Row/Col Address Bits - This step deter- mines the number of RDRAM bank, row, and column address bits that are present in the system. It also deter- mines the RDRAM core types (independent, doubled, or split) that are present. The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.

5.0 RDRAM Current Control - This step causes the INIT

block to generate a sequence of pulses which performs RDRAM maintenance operations.

6.0 RDRAM Core, Read Domain Initialization - This

stage completes the RDRAM initialization ο 6.1 RDRAM Core Initialization - A sequence of 192 memory refresh transactions is performed in order to place the cores of all RDRAMs into the proper operating state. ο 6.2 RDRAM Read Domain Initialization - A memory write and memory read transaction is performed to each RDRAM to determine which read domain each RDRAM occupies. The programmed delay of each RDRAM is then adjusted so the total RDRAM read delay (propagation delay plus programmed delay) is constant. The TPARM and TCDLYI registers of each RDRAM are rewritten with the appropriate read delay values. The ConfigRMC bus is also rewritten with an updated value.

7.0 Other RDRAM Register Fields - This stage rewrites

the INIT register with the final values of the LSR,NSR, and PSR fields. In essence, the controller must read all the read-only config- uration registers of all RDRAMs (or it must read the SPD device present on each RIMM), it must process this informa- tion, and then it must write all the read-write registers to place the RDRAMs into the proper operating mode. Initialization Note [1]: During the initialization process, it is necessary for the controller to perform 128 current control operations (3xCAL, 1xCAL/SAM) and one temperature calibrate operation (TCEN/TCAL) after reset or after power- down (PDN)exit. Initialization Note [2]: There is a class of 72Mbit RDRAM . They are distinguished by the “ S28IECO ” bit in the SPD. The behavior of the RDRAM at initialization is slightly different for the two types: S28IECO=0: Upon powerup the device enters ATTN state. The serial operations SETR, CLRR and SETF are performed without requiring a SDEVID match of the SBC bit (broad- cast) to be set.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 S28IECO=1: Upon powerup the device enters PDN state. The serial operations SETR, CLRR, and SETF require a SDEVID match. See the document detailing the reference initialization proce- dure for more information on how to handle this in a system. Initialization Note [3]: After the step of equalizing the total read delay of each RDRAM has been completed (i.e.after the TCDLY0 and TCDLY1 fields have been written for the final time), a single final memory read transaction should be made to each RDRAM in order to ensure that the output pipeline stages have been cleared. Initialization Note [4]: The SETF command (in the serial SRQ packet) should only be issued once during the Initial- ization process, as should the SETR and CLRR commands. Initialization Note [5]: The CLRR command (in the serial SRQ packet) leaves some of the contents of the memory core in an indeterminate state. Control Register Summary Table16 summarizes the RDRAM control registers. Detail is provided for each control register in Figure27 through Figure43. Read-only bits which are shaded gray are unused and return zero. Read-write bits which are shaded gray are reserved and should always be written with zero. The RIMM configuration registers which are present on Direct RIMMs. The state of the register fields are potentially affected by the IO Reset operation or the SETR/CLRR operation. This is indicated in the text accompanying each register diagram. Table 16: Control Register Summary SA11..SA0 Register Field read-write/ read-only Description 021 16 INIT SDEVID read-write, 6 bits Serial device ID. Device address for control register read/write. PSX read-write, 1 bit Power select exit. PDN/NAP exit with device addr on DQA5..0. SRP read-write, 1 bit SIO repeater. Used to initialize RDRAM. NSR read-write, 1 bit NAP self-refresh. Enables self-refresh in NAP mode. PSR read-write, 1 bit PDN self-refresh. Enables self-refresh in PDN mode. LSR read-write, 1 bit Low power self-refresh. Enables low power self-refresh. TEN read-write, 1 bit Temperature sensing enable. TSQ read-write, 1 bit Temperature sensing output. DIS read-write, 1 bit RDRAM disable. 022 16 TEST34 TEST34 read-write, 16 bits Test register. Do not read or write after SIO reset. 023 16 CNFGA REFBIT read-only, 3 bit Refresh bank bits. Used for multi-bank refresh. DBL read-only, 1 bit Double. Specifies doubled-bank architecture MVER read-only, 6 bit Manufacturer version. Manufacturer identification number. PVER read-only, 6 bit Protocol version. Specifies version of Direct protocol supported. 024 16 CNFGB BYT read-only, 1 bit Byte. Specifies an 8-bit or 9-bit byte size. DEVTYP read-only, 3 bit Device type. Device can be RDRAM or some other device category. SPT read-only, 1 bit Split-core. Each core half is an individual dependent core. CORG read-only, 6 bit Core organization. Bank, row, column address field sizes. SVER read-only, 6 bit Stepping version. Mask version number. 040 16 DEVID DEVID read-write, 5 bits Device ID. Device address for memory read/write. 041 16 REFB REFB read-write, 4 bits Refresh bank. Next bank to be refreshed by self-refresh. 042 16 REFR REFR read-write, 9 bits Refresh row. Next row to be refreshed by REFA, self-refresh. 043 16 CCA CCA read-write, 7 bits Current control A. Controls I OL output current for DQA. ASYMA read-write, 2 bits Asymmetry control. Controls asymmetry of V OL /V OH swing for DQA. 044 16 CCB CCB read-write, 7 bits Current control B. Controls I OL output current for DQB. ASYMB read-write, 2 bits Asymmetry control. Controls asymmetry of V OL /V OH swing for DQB.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 . . 045 16 NAPX NAPXA read-write, 5 bits NAP exit. Specifies length of NAP exit phase A. NAPX read-write, 5 bits NAP exit. Specifies length of NAP exit phase A + phase B. DQS read-write, 1 bits DQ select. Selects CMD framing for NAP/PDN exit. 046 16 PDNXA PDNXA read-write, 13 bits PDN exit. Specifies length of PDN exit phase A. 047 16 PDNX PDNX read-write, 13 bits PDN exit. Specifies length of PDN exit phase A + phase B. 048 16 TPARM TCAS read-write, 2 bits tCAS-C core parameter. Determines t OFFP datasheet parameter. TCLS read-write, 2 bits tCLS-C core parameter. Determines t CAC and t OFFP parameters. TCDLY0 read-write, 3 bits tCDLY0-C core parameter. Programmable delay for read data. 049 16 TFRM TFRM read-write, 4 bits tFRM-C core parameter. Determines ROW-COL packet framing interval. 04a 16 TCDLY1 TCDLY1 read-write, 3 bits tCDLY1-C core parameter. Programmable delay for read data. 04b 16 SKIP AS read, 1 bit Auto Skip value established by the SETF command. MSE read-write, 1 bit Manual Skip Enable. Allows the MS value to override the AS value. MS read-write, 1 bit Manual Skip value. 04c 16 TCYCLE TCYCLE read-write, 14 bits tCYCLE datasheet parameter. Specifies cycle time in 64ps units. 04d 16 TEST77 TEST77 read-write, 16 bits Test register. Write with zero after SIO reset. 04e 16 TEST78 TEST78 read-write, 16 bits Test register. Do not read or write after SIO reset. 04f 16 TEST79 TEST79 read-write, 16 bits Test register. Do not read or write after SIO reset. 080 16 - 0ff 16 reserved reserved vendor-specific Vendor-specific test registers. Do not read or write after SIO reset. Table 16: Control Register Summary SA11..SA0 Register Field read-write/ read-only Description

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Power State Management Table17 summarizes the power states available to a Direct RDRAM. In general, the lowest power states have the longest operational latencies. For example, the relative power levels of PDN state and STBY state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1. PDN state is the lowest power state available. The informa- tion in the RDRAM core is usually maintained with self- refresh; an internal timer automatically refreshes all rows of all banks. PDN has a relatively long exit latency because the TCLK/RCLK block must resynchronize itself to the external clock signal. NAP state is another low-power state in which either self- refresh or REFA-refresh are used to maintain the core. See “ Refresh ” on page 42 for a description of the two refresh mechanisms. NAP has a shorter exit latency than PDN because the TCLK/RCLK block maintains its synchroniza- tion state relative to the external clock signal at the time of NAP entry. This imposes a limit (t NLIMIT ) on how long an RDRAM may remain in NAP state before briefly returning to STBY or ATTN to update this synchronization state. Figure45 summarizes the transition conditions needed for moving between the various power states. Note that NAP and PDN have been divided into two substates (NAP- A/NAP-S and PDN-A/PDN-S) to account for the fact that a NAP or PDN exit may be made to either ATTN or STBY states. At initialization, the SETR/CLRR Reset sequence will put the RDRAM into PDN-S state. The PDN exit sequence involves an optional PDEV specification and bits on the CMD and SIO IN pins. Once the RDRAM is in STBY, it will move to the ATTN/ATTNR/ATTNW states when it receives a non- broadcast ROWA packet or non-broadcast ROWR packet with the ATTN command. The RDRAM returns to STBY from these three states when it receives a RLX command. Alternatively, it may enter NAP or PDN state from ATTN or STBY states with a NAPR or PDNR command in an ROWR packet. The PDN or NAP exit sequence involves an optional PDEV specification and bits on the CMD and SIO0 pins. The RDRAM returns to the ATTN or STBY state it was originally in when it first entered NAP or PDN. An RDRAM may only remain in NAP state for a time tNLIMIT . It must periodically return to ATTN or STBY. The NAPRC command causes a napdown operation if the RDRAM ’s NCBIT is set. The NCBIT is not directly visible. It is undefined on reset. It is set by a NAPR command to the RDRAM, and it is cleared by an ACT command to the RDRAM. It permits a controller to manage a set of RDRAMs in a mixture of power states. STBY state is the normal idle state of the RDRAM. In this state all banks and sense amps have usually been left precharged and ROWA and ROWR packets on the ROW pins are being monitored. When a non-broadcast ROWA packet or non-broadcast ROWR packet (with the ATTN command) packet addressed to the RDRAM is seen, the RDRAM enters ATTN state (see the right side of Figure46). This requires a time t SA during which the RDRAM activates the specified row of the specified bank. A time TFRM •tCYCLE after the ROW packet, the RDRAM will be Table 17: Power State Summary Power State Description Blocks consuming power Power State Description Blocks consuming power PDN Powerdown state. Self-refresh NAP Nap state. Similar to PDN except lower wake-up latency. Self-refresh or REFA-refresh TCLK/RCLK-Nap STBY Standby state. Ready for ROW packets. REFA-refresh TCLK/RCLK ROW demux receiver ATTN Attention state. Ready for ROW and COL packets. REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver ATTNR Attention read state. Ready for ROW and COL packets. Sending Q (read data) packets. REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ mux transmitter Core power ATTNW Attention write state. Ready for ROW and COL packets. Ready for D (write data) packets. REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ demux receiver Core power

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 able to frame COL packets (TFRM is a control register field - see Figure40). Once in ATTN state, the RDRAM will automatically transition to the ATTNW and ATTNR states as it receives WR and RD commands. Once the RDRAM is in ATTN, ATTNW, or ATTNR states, it will remain there until it is explicitly returned to the STBY state with a RLX command. A RLX command may be given in an ROWR, COLC , or COLX packet (see the left side of Figure46). It is usually given after all banks of the RDRAM have been precharged; if other banks are still activated, then the RLX command would probably not be given. If a broadcast ROWA packet or ROWR packet (with the ATTN command) is received, the RDRAM ’s power state doesn ’t change. If a broadcast ROWR packet with RLXR command is received, the RDRAM goes to STBY. Figure47 shows the NAP entry sequence (left). NAP state is entered by sending a NAPR command in a ROW packet. A time t ASN is required to enter NAP state (this specification is provided for power calculation purposes). The clock on CTM/CFM must remain stable for a time t CD after the NAPR command. The RDRAM may be in ATTN or STBY state when the NAPR command is issued. When NAP state is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is specified with NAPR, then the RDRAM will return to STBY state when NAP is exited. Figure47 also shows the PDN entry sequence (right). PDN state is entered by sending a PDNR command in a ROW packet. A time t ASP is required to enter PDN state (this spec- ification is provided for power calculation purposes). The clock on CTM/CFM must remain stable for a time t CD after the PDNR command. The RDRAM may be in ATTN or STBY state when the PDNR command is issued. When PDN state is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is specified with PDNR, then the RDRAM will return to STBY state when PDN is exited. The current- and slew-rate-control levels are re-established. The RDRAM ’s write buffer must be retired with the appro- priate COP command before NAP or PDN are entered. Also, all the RDRAM ’s banks must be precharged before NAP or PDN are entered. The exception to this is if NAP is entered with the NSR bit of the INIT register cleared (disabling self- refresh in NAP). The commands for relaxing, retiring, and precharging may be given to the RDRAM as late as the ROPa0, COPa0, and XOPa0 packets in Figure47. No broad- cast packets nor packets directed to the RDRAM entering Nap or PDN may overlay the quiet window. This window extends for a time t NPQ after the packet with the NAPR or PDNR command. Figure48 shows the NAP and PDN exit sequences. These sequences are virtually identical; the minor differences will be highlighted in the following description. Before NAP or PDN exit, the CTM/CFM clock must be stable for a time t CE . Then, on a falling and rising edge of SCK, if there is a “ 01 ” on the CMD input, NAP or PDN state will be exited. Also, on the falling SCK edge the SIO0 input must be at a 0 for NAP exit and 1 for PDN exit. If the PSX bit of the INIT register is 0, then a device PDEV5..0 is specified for NAP or PDN exit on the DQA5..0 pins. This value is driven on the rising SCK edge 0.5 or 1.5 SCK cycles after the original falling edge, depending upon the value of the DQS bit of the NAPX register. If the PSX bit of the INIT register is 1, then the RDRAM ignores the Figure 45: Power State Transition Diagram automatic automatic a u to m a tic a u to m a tic a u to m a tic a u to m a tic ATTNR ATTNW ATTN STBY SETR/CLRR NAP-A NAPR • RLXR Notation: SETR/CLRR - SETR/CLRR Reset sequence in SRQ packets tNLIMIT NAP NAP-S PDEV.CMD• SIO0 NAPR • RLXR PDEV.CMD• SIO0 PDN-A PDNR • RLXR PDN PDN-S PDEV.CMD•SIO0 PDNR • RLXR PDEV.CMD•SIO0 N A P R P D N R A T T N R L X PDNR - PDNR command in ROWR packet NAPR - NAPR command in ROWR packet RLXR - RLX command in ROWR packet RLX - RLX command in ROWR,COLC,COLX packets SIO0 - SIO0 input value PDEV.CMD - (PDEV=DEVID)•(CMD=01) ATTN - ROWA packet (non-broadcast) or ROWR packet (non-broadcast) with ATTN command

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Refresh RDRAMs, like any other DRAM technology, use volatile storage cells which must be periodically refreshed. This is accomplished with the REFA command. Figure50 shows an example of this. The REFA command in the transaction is typically a broad- cast command (DR4T and DR4F are both set in the ROWR packet), so that in all devices bank number Ba is activated with row number REFR, where REFR is a control register in the RDRAM. When the command is broadcast and ATTN is set, the power state of the RDRAMs (ATTN or STBY) will remain unchanged. The controller increments the bank address Ba for the next REFA command. When Ba is equal to its maximum value, the RDRAM automatically incre- ments REFR for the next REFA command. On average, these REFA commands are sent once every tREF /2 BBIT+RBIT (where BBIT are the number of bank address bits and RBIT are the number of row address bits) so that each row of each bank is refreshed once every tREF interval. The REFA command is equivalent to an ACT command, in terms of the way that it interacts with other packets (see Table10). In the example, an ACT command is sent after tRR to address b0, a different (non-adjacent) bank than the REFA command. A second ACT command can be sent after a time tRC to address c0, the same bank (or an adjacent bank) as the REFA command. Note that a broadcast REFP command is issued a time t RAS after the initial REFA command in order to precharge the refreshed bank in all RDRAMs. After a bank is given a REFA command, no other core operations (activate or precharge) should be issued to it until it receives a REFP. It is also possible to interleave refresh transactions (not shown). In the figure, the ACT b0 command would be replaced by a REFA b0 command. The b0 address would be broadcast to all devices, and would be {Broadcast, Ba+2, REFR}. Note that the bank address should skip by two to avoid adjacent bank interference. A possible bank incre- menting pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10, 12, 14, 18, 20, 22, 31}. Every time bank 31 is reached, the REFA command would automatically increment the REFR register. A second refresh mechanism is available for use in PDN and NAP power states. This mechanism is called self-refresh mode. When the PDN power state is entered, or when NAP power state is entered with the NSR control register bit set, then self-refresh is automatically started for the RDRAM. Self-refresh uses an internal time base reference in the RDRAM. This causes an activate and precharge to be carried out once in every tREF /2 BBIT+RBIT interval. The REFB and REFR control registers are used to keep track of the bank and row being refreshed. Before a controller places an RDRAM into self-refresh mode, it should perform REFA/REFP refreshes until the bank address is equal to the maximum value. This ensures that no rows are skipped. Likewise, when a controller returns an RDRAM to REFA/REFP refresh, it should start with the minimum bank address value (zero). Figure 50: REFA/REFP Refresh Transaction Example CTM/CFM DQA8..0 DQB8..0 COL4 ..COL0 ROW2 ..ROW0 T 0 T 4 T 8 T 12T 1 T 5 T 9 T 13T 2 T 6 T 10 T 14T 3 T 7 T 11 T 15 T 16 T 20 T 24 T 28T 17 T 21 T 25 T 29T 18 T 22 T 26 T 30T 19 T 23 T 27 T 31 T 32 T 36 T 40 T 44T 33 T 37 T 41 T 45T 34 T 38 T 42 T 46T 35 T 39 T 43 T 47 REFA a0 ACT c0 t RAS t RC t RP Transaction a: REFA a0 = {Broadcast,Ba,REFR} a1 = {Broadcast,Ba} Transaction c: xx c0 = {Dc, ==Ba, Rc} REFA d0 t REF /2 BBIT+RBIT BBIT = # bank address bits RBIT = # row address bits ACT b0 Transaction d: REFA d0 = {Broadcast,Ba+1,REFR} REFB = REFB3..REFB0 REFR = REFR8..REFR0 t RR Transaction b: xx b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb} REFP a1

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Electrical Conditions Timing Conditions Table 18: Electrical Conditions Symbol Parameter and Conditions Min Max Unit T J Junction temperature under bias - 100 °C V DD, V DDA Supply voltage 2.50 - 0.13 2.50 + 0.13 V V DD,N, V DDA,N Supply voltage droop (DC) during NAP interval (t NLIMIT ) - 2.0 % v DD,N, v DDA,N Supply voltage ripple (AC) during NAP interval (t NLIMIT ) -2.0 2.0 % V TERM Termination voltage 1.80 - 0.1 1.80 + 0.1 V V REF Reference voltage 1.40 - 0.2 1.40 + 0.2 V V DIL RSL data input - low voltage V REF - 0.5 V REF - 0.2 V V DIH RSL data input - high voltage V REF + 0.2 V REF + 0.5 V V DIS RSL data input swing: V DIS = V DIH - V DIL 0.4 1.0 V A DI RSL data asymmetry: A DI = [(V DIH - V REF ) + (V DIL - V REF )]/V DIS 0 -20 % V X RSL clock input - crossing point of true and complement signals 1.3 1.8 V V CM RSL clock input - common mode V CM = (V CIH +V CIL) /2 1.4 1.7 V V CIS,CTM RSL clock input swing: V CIS = V CIH - V CIL (CTM,CTMN pins). 0.35 0.70 V V CIS,CFM RSL clock input swing: V CIS = V CIH - V CIL (CFM,CFMN pins). 0.125 0.70 V V IL,CMOS CMOS input low voltage - 0.3 V CMOS /2 - 0.25 V V IH,CMOS CMOS input high voltage V CMOS /2 + 0.25 V CMOS +0.3 V Table 19: Timing Conditions Symbol Parameter Min Max Unit Figure(s) tCYCLE CTM and CFM cycle times (-600) 3.33 3.83 ns Figure53 CTM and CFM cycle times (-711) 2.80 3.83 ns Figure53 CTM and CFM cycle times (-800) 2.50 3.83 ns Figure53 tCR , t CF CTM and CFM input rise and fall times 0.2 0.5 ns Figure53 tCH , t CL CTM and CFM high and low times 40% 60% tCYCLE Figure53 tTR CTM-CFM differential (MSE/MS=0/0) CTM-CFM differential (MSE/MS=1/1) a 0.0 0.9 1.0 1.0 tCYCLE Figure42 Figure53 tDCW Domain crossing window -0.1 0.1 tCYCLE Figure59 tDR , t DF DQA/DQB/ROW/COL input rise/fall times 0.2 0.65 ns Figure54 tS , t H DQA/DQB/ROW/COL-to-CFM setup/hold @ t CYCLE =3.33ns @ t CYCLE =2.81ns @t CYCLE =2.50ns 0.275 b ,d 0.240 c ,d 0.200 d - ns Figure54

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 tDR1, tDF1 SIO0, SIO1 input rise and fall times - 5.0 ns Figure56 tDR2, tDF2 CMD, SCK input rise and fall times - 2.0 ns Figure56 tCYCLE1 SCK cycle time - Serial control register transactions 1000 - ns Figure56 SCK cycle time - Power transitions 10 - ns Figure56 tCH1 , t CL1 SCK high and low times 4.25 - ns Figure56 tS1 CMD setup time to SCK rising or falling edge e 1.25 - ns Figure56 tH1 CMD hold time to SCK rising or falling edge e 1 - ns Figure56 tS2 SIO0 setup time to SCK falling edge 40 - ns Figure56 tH2 SIO0 hold time to SCK falling edge 40 - ns Figure56 tS3 PDEV setup time on DQA5..0 to SCK rising edge. 0 - ns Figure48, Figure57 tH3 PDEV hold time on DQA5..0 to SCK rising edge. 5.5 - ns tS4 ROW2..0, COL4..0 setup time for quiet window -1 - tCYCLE Figure48 tH4 ROW2..0, COL4..0 hold time for quiet window f 5 - tCYCLE Figure48 v IL,CMOS CMOS input low voltage - over/undershoot voltage duration is less than or equal to 5ns - 0.7 V CMOS /2 - 0.4 V v IH,CMOS CMOS input high voltage - over/undershoot voltage duration is less than or equal to 5ns V CMOS /2 + 0.4 V CMOS + 0.7 V tNPQ Quiet on ROW/COL bits during NAP/PDN entry 4 - tCYCLE Figure47 tREADTOCC Offset between read data and CC packets (same device) 12 - tCYCLE Figure51 tCCSAMTOREAD Offset between CC packet and read data (same device) 8 - tCYCLE Figure51 tCE CTM/CFM stable before NAP/PDN exit 2 - tCYCLE Figure48 tCD CTM/CFM stable after NAP/PDN entry 100 - tCYCLE Figure47 tFRM ROW packet to COL packet ATTN framing delay 7 - tCYCLE Figure46 tNLIMIT Maximum time in NAP mode 10.0 µs Figure45 tREF Refresh interval 32 ms Figure50 tCCTRL Current control interval 34 t CYCLE 100ms ms/t CYCLE Figure51 tTEMP Temperature control interval 100 ms Figure52 tTCEN TCE command to TCAL command 150 - tCYCLE Figure52 tTCAL TCAL command to quiet window 2 2 tCYCLE Figure52 tTCQUIET Quiet window (no read data) 140 - tCYCLE Figure52 tPAUSE RDRAM delay (no RSL operations allowed) 200.0 µs page28 b. This parameter also applies to a -800 or -711 part when operated with t CYCLE =3.33ns. c. This parameter also applies to a -800 part when operated with t CYCLE =2.81ns. d. t S,MIN and t H,MIN for other t CYCLE values can be interpolated between or extrapolated from the timings at the 3 specified t CYCLE values. f. Effective hold becomes t H4 ’ = tH4 +[PDNXA •64 •tS CYCLE + tPDNXB,MAX ]-[PDNX •256 •tS CYCLE ] if [PDNX •256 •tS CYCLE ] < [PDNXA •64 •tS CYCLE + tPDNXB,MAX ]. See Figure 48. Table 19: Timing Conditions Symbol Parameter Min Max Unit Figure(s)

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000

Electrical Characteristics

Table 20: Electrical Characteristics Symbol Parameter and Conditions Min Max Unit Θ JC Junction-to-Case thermal resistance - 0.2 °C/Watt I REF V REF current @ V REF,MAX -10 10 µA I OH RSL output high current @ (0 ≤V OUT ≤V DD ) -10 10 µA I ALL RSL I OL current @ V OL = 0.9V, V DD,MIN , T J,MAX a 30.0 90.0 mA ΔI OL RSL I OL current resolution step - 2.0 mA r OUT Dynamic output impedance 150 - Ω I I,CMOS CMOS input leakage current @ (0 ≤V I,CMOS ≤V CMOS ) -10.0 10.0 µA V OL,CMOS CMOS output voltage @ I OL,CMOS = 1.0mA - 0.3 V V OH,CMOS CMOS output high voltage @ I OH,CMOS = -0.25mA V CMOS -0.3 - V a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current. Table 21: Timing Characteristics Symbol Parameter Min Max Unit Figure(s) tQ CTM-to-DQA/DQB output time @ t CYCLE =3.33ns @ t CYCLE =2.81ns @ t CYCLE =2.50ns -0.350 a ,c -0.300 b ,c -0.260 c +0.350 a,c +0.300 b ,c +0.260 c ns Figure55 tQR , t QF DQA/DQB output rise and fall times 0.2 0.45 ns Figure55 tQ1 SCK(neg)-to-SIO0 delay @ C LOAD,MAX = 20pF (SD read data valid). - 10 ns Figure58 tHR SCK(pos)-to-SIO0 delay @ C LOAD,MAX = 20pF (SD read data hold). 2 - ns Figure58 tQR1 , t QF1 SIO OUT rise/fall @ C LOAD,MAX = 20pF - 5 ns Figure58 tPROP1 SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C LOAD,MAX = 20pF - 10 ns Figure58 tNAPXA NAP exit delay - phase A - 50 ns Figure48 tNAPXB NAP exit delay - phase B - 40 ns Figure48 tPDNXA PDN exit delay - phase A - 4 µs Figure48 tPDNXB PDN exit delay - phase B - 9000 tCYCLE Figure48 tAS ATTN-to-STBY power state delay - 1 tCYCLE Figure46 tSA STBY-to-ATTN power state delay - 0 tCYCLE Figure46 tASN ATTN/STBY-to-NAP power state delay - 8 tCYCLE Figure47 tASP ATTN/STBY-to-PDN power state delay - 8 tCYCLE Figure47 a. This parameter also applies to a -800 or -711 part when operated with t CYCLE =3.33ns. b. This parameter also applies to a -800 part when operated with t CYCLE =2.81ns. c. t Q,MIN and tQ,MAX for other t CYCLE values can be interpolated between or extrapolated from the timings at the 3 specified t CYCLE values.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 RSL - Clocking Figure53 is a timing diagram which shows the detailed requirements for the RSL clock signals on the Channel. The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and DQB, outputs. Most timing is measured relative to the points where they cross. The t CYCLE parameter is measured from the falling CTM edge to the falling CTM edge. The t CL and t CH param- eters are measured from falling to rising and rising to falling edges of CTM. The t CR and t CF rise- and fall-time parame- ters are measured at the 20% and 80% points. The CFM and CFMN are differential clock outputs used for receiving information on the DQA, DQB, ROW and COL outputs. Most timing is measured relative to the points where they cross. The t CYCLE parameter is measured from the falling CFM edge to the falling CFM edge. The t CL and tCH parameters are measured from falling to rising and rising to falling edges of CFM. The t CR and t CF rise- and fall-time parameters are measured at the 20% and 80% points. The t TR parameter specifies the phase difference that may be tolerated with respect to the CTM and CFM differential clock inputs (the CTM pair is always earlier). Figure 53: RSL Timing - Clock Signals V CIH 50% V CIL 80% 20% CTM CTMN V CIH 50% V CIL 80% 20% CFM CFMN tTR tCF tCF tCR tCR tCYCLE tCL tCH tCF tCF tCR tCR tCYCLE tCL tCH V CM V X+ V X- V CM V X+ V X-

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 RSL - Receive Timing Figure54 is a timing diagram which shows the detailed requirements for the RSL input signals on the Channel. The DQA, DQB, ROW, and COL signals are inputs which receive information transmitted by a Direct RAC on the Channel. Each signal is sampled twice per t CYCLE interval. The set/hold window of the sample points is t S /t H. The sample points are centered at the 0% and 50% points of a cycle, measured relative to the crossing points of the falling CFM clock edge. The set and hold parameters are measured at the V REF voltage point of the input transition. The t DR and t DF rise- and fall-time parameters are measured at the 20% and 80% points of the input transition. Figure 54: RSL Timing - Data Signals for Receive V DIH V REF V DIL 80% 20% V CIH 50% V CIL 80% 20% CFM CFMN DQA tS ROW DQB tDF tDR tH tS tH 0.5•t CYCLE even odd COL V CM V X+ V X-

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 RSL - Transmit Timing Figure55 is a timing diagram which shows the detailed requirements for the RSL output signals on the Channel. The DQA and DQB signals are outputs to transmit informa- tion that is received by a Direct RAC on the Channel. Each signal is driven twice per t CYCLE interval. The beginning and end of the even transmit window is at the 75% point of the previous cycle and at the 25% point of the current cycle. The beginning and end of the odd transmit window is at the 25% point and at the 75% point of the current cycle. These transmit points are measured relative to the crossing points of the falling CTM clock edge. The size of the actual transmit window is less than the ideal t CYCLE /2, as indicated by the non-zero values of t Q,MIN and t Q,MAX . The t Q param- eters are measured at the 50% voltage point of the output transition. The t QR and t QF rise- and fall-time parameters are measured at the 20% and 80% points of the output transition. Figure 55: RSL Timing - Data Signals for Transmit tQ,MIN tQ,MAX tQ,MAX tQ,MIN 0.25•t CYCLE V QH 50% V QL 80% 20% V CIH 50% V CIL 80% 20% CTM CTMN tQF tQR even odd 0.75•t CYCLE 0.75•t CYCLE DQA DQB V CM V X+ V X-

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 CMOS - Receive Timing Figure56 is a timing diagram which shows the detailed requirements for the CMOS input signals. The CMD and SIO0 signals are inputs which receive infor- mation transmitted by a controller or by another RDRAM’s SIO1 output. SCK is the CMOS clock signal driven by the controller. All signals are high true. The cycle time, high phase time, and low phase time of the SCK clock are t CYCLE1 , t CH1 and t CL1 , all measured at the 50% level. The rise and fall times of SCK, CMD, and SIO0 are t DR1 and t DF1 , measured at the 20% and 80% levels. The CMD signal is sampled twice per t CYCLE1 interval, on the rising edge (odd data) and the falling edge (even data). The set/hold window of the sample points is t S1 /t H1. The SCK and CMD timing points are measured at the 50% level. The SIO0 signal is sampled once per t CYCLE1 interval on the falling edge. The set/hold window of the sample points is tS2 /t H2. The SCK and SIO0 timing points are measured at the 50% level. Figure 56: CMOS Timing - Data Signals for Receive V IH,CMOS 50% V IL,CMOS 80% 20% SCK tS1 CMD tDR2 tH1 tS1 tH1 even odd tDF2 V IH,CMOS 50% V IL,CMOS 80% 20% tDR2 tDF2 tCH1 tCL1 tCYCLE1 tS2 SIO0 tDR1 tH2 tDF1 V IH,CMOS 50% V IL,CMOS 80% 20%

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 The SCK clock is also used for sampling data on RSL inputs in one situation. Figure48 shows the PDN and NAP exit sequences. If the PSX field of the INIT register is one (see Figure27), then the PDN and NAP exit sequences are broad- cast; i.e. all RDRAMs that are in PDN or NAP will perform the exit sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. only one RDRAM that is in PDN or NAP will perform the exit sequence. The address of that RDRAM is specified on the DQA[5:0] bus in the set/hold window t S3 /t H3 around the rising edge of SCK. This is shown in Figure57. The SCK timing point is measured at the 50% level, and the DQA[5:0] bus signals are measured at the V REF level. Figure 57: CMOS Timing - Device Address for NAP or PDN Exit V IH,CMOS 50% V IL,CMOS 80% 20% SCK V DIH V REF V DIL 80% 20% DQA[5:0] tS3 tH3 PDEV

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 CMOS - Transmit Timing Figure58 is a timing diagram which shows the detailed requirements for the CMOS output signals. The SIO0 signal is driven once per t CYCLE1 interval on the falling edge. The clock-to-output window is t Q1,MIN /t Q1,MAX. The SCK and SIO0 timing points are measured at the 50% level. The rise and fall times of SIO0 are t QR1 and t QF1 , measured at the 20% and 80% levels. Figure 58: CMOS Timing - Data Signals for Transmit V IH,CMOS 50% V IL,CMOS 80% 20% SCK SIO0 tQR1 tQF1 V OH,CMOS 50% V OL,CMOS 80% 20% tQ1,MAX V IH,CMOS 50% V IL,CMOS 80% 20% tHR,MIN V OH,CMOS 50% V OL,CMOS 80% 20% SIO0 tDR1 tDF1 tQR1 tQF1 tPROP1,MAX tPROP1,MIN or SIO1 SIO1 or SIO0

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Figure58 also shows the combinational path connecting SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read data only). The t PROP1 parameter specified this propagation delay. The rise and fall times of SIO0 and SIO1 inputs must be t DR1 and t DF1 , measured at the 20% and 80% levels. The rise and fall times of SIO0 and SIO1 outputs are t QR1 and tQF1 , measured at the 20% and 80% levels. RSL - Domain Crossing Window When read data is returned by the RDRAM, information must cross from the receive clock domain (CFM) to the transmit clock domain (CTM). The t TR parameter permits the CFM to CTM phase to vary through an entire cycle; i.e. there is no restriction on the alignment of these two clocks. A second parameter t DCW is needed in order to describe how the delay between a RD command packet and read data packet varies as a function of the t TR value. Figure59 shows this timing for five distinct values of t TR . Case A (t TR =0) is what has been used throughout this docu- ment. The delay between the RD command and read data is tCAC . As t TR varies from zero to t CYCLE (cases A through E), the command to data delay is (t CAC -t TR ). When the t TR value is in the range 0 to t DCW,MAX , the command to data delay can also be (t CAC -t TR -t CYCLE ). This is shown as cases A’ and B’ (the gray packets). Similarly, when the t TR value is in the range (t CYCLE +t DCW,MIN ) to t CYCLE , the command to data delay can also be (t CAC -t TR +t CYCLE ). This is shown as cases D’ and E’ (the gray packets). The RDRAM will work reliably with either the white or gray packet timing. The delay value is selected at initialization, and remains fixed thereafter. Figure 59: RSL Transmit - Crossing Read Domains CFM COL tTR CTM DQA/B DQA/B tTR =0 tCYCLE Case A tTR =0Case A’ tTR CTM DQA/B DQA/B tTR =t DCW,MAX Case B tTR =t DCW,MAX Case B’ tTR CTM DQA/B tTR =0.5•t CYCLECase C CTM DQA/B DQA/B tTR =t CYCLE +t DCW,MIN Case D tTR =t CYCLE +t DCW,MIN Case D’ CTM DQA/B DQA/B tTR =t CYCLE Case E tTR =t CYCLE Case E’ tTR tTR RD a1 Q(a1) Q(a1) Q(a1) Q(a1)tCAC -t TR tCAC -t TR -t CYCLE Q(a1) Q(a1) Q(a1) Q(a1) Q(a1) tCAC -t TR tCAC -t TR +t CYCLE tCAC -t TR tCAC -t TR +t CYCLE tCAC -t TR tCAC -t TR -t CYCLE tCAC -t TR

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Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Timing Parameters Table 22: Timing Parameter Summary Parameter Description Min -45 -800 Min -45 -711 Min -53.3 -600 Max Units Figure(s) tRC Row Cycle time of RDRAM banks -the interval between ROWA packets with ACT commands to the same bank. 28 28 28 - tCYCLE Figure15 Figure16 tRAS RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command and next ROWR packet with PRER a command to the same bank. 20 20 20 64 µs b tCYCLE Figure15 Figure16 tRP Row Precharge time of RDRAM banks - the interval between ROWR packet with PRER a command and next ROWA packet with ACT command to the same bank. 8 8 8 - tCYCLE Figure15 Figure16 tPP Precharge-to-precharge time of RDRAM device - the interval between succes- sive ROWR packets with PRER a commands to any banks of the same device. 8 8 8 - tCYCLE Figure12 tRR RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with ACT commands to any banks of the same device. 8 8 8 - tCYCLE Figure13 tRCD RAS-to-CAS Delay - the interval from ROWA packet with ACT command to COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen by the RDRAM core (t RCD-C ) is equal to t RCD-C = 1 + t RCD because of differ- ences in the row and column paths through the RDRAM interface. 9 7 7 - tCYCLE Figure15 Figure16 tCAC CAS Access delay - the interval from RD command to Q read data. The equa- tion for t CAC is given in the TPARM register in Figure39. 8 8 8 12 tCYCLE Figure4 Figure39 tCWD CAS Write Delay (interval from WR command to D write data. 6 6 6 6 tCYCLE Figure4 tCC CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands). 4 4 4 - tCYCLE Figure15 Figure16 tPACKET Length of ROWA, ROWR, COLC, COLM or COLX packet. 4 4 4 4 tCYCLE Figure3 tRTR Interval from COLC packet with WR command to COLC packet which causes retire, and to COLM packet with bytemask. 8 8 8 - tCYCLE Figure17 tOFFP The interval (offset) from COLC packet with RDA command, or from COLC packet with retire command (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet with PREX command to the equivalent ROWR packet with PRER. The equation for t OFFP is given in the TPARM register in Figure39. 4 4 4 4 tCYCLE Figure14 Figure39 tRDP Interval from last COLC packet with RD command to ROWR packet with PRER. 4 4 4 - tCYCLE Figure15 tRTP Interval from last COLC packet with automatic retire command to ROWR packet with PRER. 4 4 4 - tCYCLE Figure16 a. Or equivalent PREC or PREX command. See Figure14 . b. This is a constraint imposed by the core, and is therefore in units of µs rather than t CYCLE .

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Absolute Maximum Ratings IDD - Supply Current Profile Table 23: Absolute Maximum Ratings Symbol Parameter Min Max Unit V I,ABS Voltage applied to any RSL or CMOS pin with respect to Gnd - 0.3 V DD +0.3 V V DD,ABS , V DDA,ABS Voltage on VDD and VDDA with respect to Gnd - 0.5 V DD +1.0 V T STORE Storage temperature - 50 100 °C Table 24: Supply Current Profile I DD value RDRAM blocks consuming power a Max -45 -800 Max -45 -711 Max -53.3 -600 Unit I DD,PDN Self-refresh only for INIT.LSR=0 3000 3000 3000 µA I DD,NAP T/RCLK-Nap 4 4 4 mA I DD,STBY T/RCLK, ROW-demux 105 100 90 mA I DD,ATTN T/RCLK, ROW-demux, COL-demux 165 155 140 mA I DD,ATTN-W T/RCLK, ROW-demux,COL-demux,DQ-demux,1 •WR-SenseAmp, 4 •ACT-Bank 575/625 b 525/580 455/500 mA I DD,ATTN-R T/RCLK, ROW-demux,COL-demux,DQ-mux,1 •RD-SenseAmp, 4 •ACT-Bank c 490/520 450/480 400/420 mA a. The CMOS interface consumes power in all power states. b. x16/x18 RDRAM data width c. This does not include the IOL sink current. The RDRAM dissipates IOL •VOL in each output driver when a logic one is driven.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Capacitance and Inductance Figure60 shows the equivalent load circuit of the RSL and CMOS pins. The circuit models the load that the device presents to the Channel. Figure 60: Equivalent Load Circuit for RSL Pins Gnd Pin CTM,CTMN, Pad L I R I C I Gnd Pin SCK,CMD Pin Pad L I,CMOS C I,CMOS Gnd Pin SIO0,SIO1 Pin Pad L I,CMOS C I,CMOS,SIO Gnd Pin DQA,DQB,RQ Pin Pad L I R I C I CFM,CFMN Pin

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 This circuit does not include pin coupling effects that are often present in the packaged device. Because coupling effects make the effective single-pin inductance L I , and capacitance C I , a function of neighboring pins, these param- eters are intrinsically data-dependent. For purposes of speci- fying the device electrical loading on the Channel, the effective L I and C I are defined as the worst-case values over all specified operating conditions. L I is defined as the effective pin inductance based on the device pin assignment. Because the pad assignment places each RSL signal adjacent to an AC ground (a Gnd or Vdd pin), the effective inductance must be defined based on this configuration. Therefore, L I assumes a loop with the RSL pin adjacent to an AC ground. C I is defined as the effective pin capacitance based on the device pin assignment. It is the sum of the effective package pin capacitance and the IO pad capacitance. Table 25: RSL Pin Parasitics Symbol Parameter and Conditions - RSL pins IO freq. Min Max Unit L I RSL effective input inductance 4.0 nH L 12 Mutual inductance between any DQA or DQB RSL signals. 0.2 nH Mutual inductance between any ROW or COL RSL signals. 0.6 nH ΔL I Difference in L I value between any RSL pins of a single device. - 1.8 nH C I RSL effective input capacitance a -800 2.0 2.4 pF -711 2.0 2.4 -600 2.0 2.6 C 12 Mutual capacitance between any RSL signals. - 0.1 pF ΔC I Difference in C I value between average of CTM/CFM and any RSL pins of a single device. - 0.06 pF R I RSL effective input resistance 4 15 Ω a. This value is a combination of the device IO circuitry and package capacitances. Table 26: CMOS Pin Parasitics Symbol Parameter and Conditions - CMOS pins Min Max Unit L I ,CMOS CMOS effective input inductance 8.0 nH C I ,CMOS CMOS effective input capacitance (SCK,CMD) a 1.7 2.1 pF C I ,CMOS,SIO CMOS effective input capacitance (SIO1, SIO0) a - 7.0 pF a. This value is a combination of the device IO circuitry and package capacitances.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Center-Bonded uBGA Package Figure61 shows the form and dimensions of the recom- mended package for the center-bonded CSP device class. Figure 61: Center-Bonded uBGA Package Table27 lists the numerical values corresponding to dimen- sions shown in Figure61. Table 27: Center-Bonded uBGA Package Dimensions A B C D E F G H J D A e1d E E1 Top Bottom Bottom Bottom Symbol Parameter Min (128Mb/144Mb) Max (128Mb/144Mb) Unit e1 Ball pitch (x-axis) 1.00 1.00 mm e2 Ball pitch (y-axis) 0.80 0.80 mm A Package body length 11.90 12.10 mm D Package body width 10.10 10.30 mm E Package total thickness - 1.00 a mm E1 Ball height 0.20 0.30 mm d Ball diameter 0.30 0.40 mm a. The E,MAX parameter for SO-RIMM applications is 0.94mm.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Glossary of Terms ACT Activate command from AV field. activate To access a row and place in sense amp. adjacent Two RDRAM banks which share sense amps (also called doubled banks). ASYM CCA register field for RSL V OL /V OH . ATTN Power state - ready for ROW/COL packets. ATTNR Power state - transmitting Q packets. ATTNW Power state - receiving D packets. AV Opcode field in ROW packets. bank A block of 2 RBIT •2 CBIT storage cells in the core of the RDRAM. BC Bank address field in COLC packet. BBIT CNFGA register field - # bank address bits. broadcast An operation executed by all RDRAMs. BR Bank address field in ROW packets. bubble Idle cycle(s) on RDRAM pins needed because of a resource constraint. BYT CNFGB register field - 8/9 bits per byte. BX Bank address field in COLX packet. C Column address field in COLC packet. CAL Calibrate (I OL ) command in XOP field. CBIT CNFGB register field - # column address bits. CCA Control register - current control A. CCB Control register - current control B. CFM,CFMN Clock pins for receiving packets. Channel ROW/COL/DQ pins and external wires. CLRR Clear reset command from SOP field. CMD CMOS pin for initialization/power control. CNFGA Control register with configuration fields. CNFGB Control register with configuration fields. COL Pins for column-access control. COL COLC,COLM,COLX packet on COL pins. COLC Column operation packet on COL pins. COLM Write mask packet on COL pins. column Rows in a bank or activated row in sense amps have 2 CBIT dualocts column storage. command A decoded bit-combination from a field. COLX Extended operation packet on COL pins. controller A logic-device which drives the ROW/COL /DQ wires for a Channel of RDRAMs. COP Column opcode field in COLC packet. core The banks and sense amps of an RDRAM. CTM,CTMN Clock pins for transmitting packets. current control Periodic operations to update the proper I OL value of RSL output drivers. D Write data packet on DQ pins. DBL CNFGB register field - doubled-bank. DC Device address field in COLC packet. device An RDRAM on a Channel. DEVID Control register with device address that is matched against DR, DC, and DX fields. DM Device match for ROW packet decode. doubled-bank RDRAM with shared sense amp. DQ DQA and DQB pins. DQA Pins for data byte A. DQB Pins for data byte B. DQS NAPX register field - PDN/NAP exit. DR,DR4T,DR4F Device address field and packet framing fields in ROWA and ROWR packets. dualoct 16 bytes - the smallest addressable datum. DX Device address field in COLX packet. field A collection of bits in a packet. INIT Control register with initialization fields. initialization Configuring a Channel of RDRAMs so they are ready to respond to transactions. LSR CNFGA register field - low-power self- refresh. M Mask opcode field (COLM/COLX packet). MA Field in COLM packet for masking byte A. MB Field in COLM packet for masking byte B. MSK Mask command in M field. MVER Control register - manufacturer ID. NAP Power state - needs SCK/CMD wakeup. NAPR Nap command in ROP field. NAPRC Conditional nap command in ROP field. NAPXA NAPX register field - NAP exit delay A. NAPXB NAPX register field - NAP exit delay B. NOCOP No-operation command in COP field. NOROP No-operation command in ROP field.

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 NOXOP No-operation command in XOP field. NSR INIT register field- NAP self-refresh. packet A collection of bits carried on the Channel. PDN Power state - needs SCK/CMD wakeup. PDNR Powerdown command in ROP field. PDNXA Control register - PDN exit delay A. PDNXB Control register - PDN exit delay B. pin efficiency The fraction of non-idle cycles on a pin. PRE PREC,PRER,PREX precharge commands. PREC Precharge command in COP field. precharge Prepares sense amp and bank for activate. PRER Precharge command in ROP field. PREX Precharge command in XOP field. PSX INIT register field - PDN/NAP exit. PSR INIT register field - PDN self-refresh. PVER CNFGB register field - protocol version. Q Read data packet on DQ pins. R Row address field of ROWA packet. RBIT CNFGB register field - # row address bits. RD/RDA Read (/precharge) command in COP field. read Operation of accesssing sense amp data. receive Moving information from the Channel into the RDRAM (a serial stream is demuxed). REFA Refresh-activate command in ROP field. REFB Control register - next bank (self-refresh). REFBIT CNFGA register field - ignore bank bits (for REFA and self-refresh). REFP Refresh-precharge command in ROP field. REFR Control register - next row for REFA. refresh Periodic operations to restore storage cells. retire The automatic operation that stores write buffer into sense amp after WR command. RLX RLXC,RLXR,RLXX relax commands. RLXC Relax command in COP field. RLXR Relax command in ROP field. RLXX Relax command in XOP field. ROP Row-opcode field in ROWR packet. row 2 CBIT dualocts of cells (bank/sense amp). ROW Pins for row-access control ROW ROWA or ROWR packets on ROW pins. ROWA Activate packet on ROW pins. ROWR Row operation packet on ROW pins. RQ Alternate name for ROW/COL pins. RSL Rambus Signaling Levels. SAM Sample (I OL ) command in XOP field. SA Serial address packet for control register transactions w/ SA address field. SBC Serial broadcast field in SRQ. SCK CMOS clock pin. SD Serial data packet for control register transactions w/ SD data field. SDEV Serial device address in SRQ packet. SDEVID INIT register field - Serial device ID. self-refresh Refresh mode for PDN and NAP. sense amp Fast storage that holds copy of bank’s row. SETF Set fast clock command from SOP field. SETR Set reset command from SOP field. SINT Serial interval packet for control register read/write transactions. SIO0,SIO1 CMOS serial pins for control registers. SOP Serial opcode field in SRQ. SRD Serial read opcode command from SOP. SRP INIT register field - Serial repeat bit. SRQ Serial request packet for control register read/write transactions. STBY Power state - ready for ROW packets. SVER Control register - stepping version. SWR Serial write opcode command from SOP. TCAS TCLSCAS register field - t CAS core delay. TCLS TCLSCAS register field - t CLS core delay. TCLSCAS Control register - t CAS and t CLS delays. TCYCLE Control register - t CYCLE delay. TDAC Control register - t DAC delay. TEST77 Control register - for test purposes. TEST78 Control register - for test purposes. TRDLY Control register - t RDLY delay. transaction ROW,COL,DQ packets for memory access. transmit Moving information from the RDRAM onto the Channel (parallel word is muxed). WR/WRA Write (/precharge) command in COP field. write Operation of modifying sense amp data. XOP Extended opcode field in COLX packet

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000 Table Of Contents © Copyright January 2000 Samsung Electronics. All rights reserved. Direct Rambus and Direct RDRAM are trademarks of Rambus Inc. Rambus, RDRAM, and the Rambus Logo are registered trademarks of Rambus Inc. This document contains advanced information that is subject to change by Samsung without notice. Document Version 1.02 Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Kiheung-Eup Yongin-City Kyunggi-Do, KOREA Telephone: 82-331-209-4519 Fax: 82-2-760-7990 http://www.samsungsemi.com

Direct RDRAM ™K4R271669A/K4R441869A Rev. 1.02 Jan. 2000