K4M513233E-MEC

K4M513233E SAMSUNG | Alldatasheet

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Technical content

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM

• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation.
• Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• 2Chips DDP 90Balls FBGA with 0.8mm ball pitch ( -MXXX : Leaded, -EXXX : Lead Free).

FEATURES

The K4M513233E is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technol- ogy. Synchronous design allows pr ecise cycle control with the use of system clock and I/O tr ansactions are pos sible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high per- formance memory system applications. GENERAL DESCRIPTION

ORDERING INFORMATION

• M(E)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C) NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top computers for the first three years of five year term of this license. Nothing herein limits the rights of Samsung to use Multi-Die Plastic DRAM in other products or other applications under paragrangh such as mobile, telecom or non-computer application(which include by way of example laptop or notebook computers, cell phones, televisions or visual monitors) Violation may subject the customer to legal claims and also excludes any warranty against infringement from Samsung." . 3. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. Part No. Max Freq. Interface Package K4M513233E-M(E)C/L/F75 133MHz(CL=3) LVCMOS 90 FBGA Leaded (Lead Free)K4M513233E-M(E)C/L/F1H 105MHz(CL=2) K4M513233E-M(E)C/L/F1L 105MHz(CL=3)*1 4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM Bank Select Data Input Register 4M x 32 4M x 32 Sense AMP Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Address Register Row Buffer Refresh Counter Row Decoder Col. Buffer LRAS LCBR LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE DQM LWE LDQM DQi CLK ADD LCAS LWCBR 4M x 32 4M x 32 Timing Register FUNCTIONAL BLOCK DIAGRAM

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM 90Ball(6x15) FBGA 123789 A DQ26 DQ24 V SS VDD DQ23 DQ21 BD Q 2 8 V DDQ VSSQ VDDQ VSSQ DQ19 CV SSQ DQ27 DQ25 DQ22 DQ20 V DDQ DV SSQ DQ29 DQ30 DQ17 DQ18 V DDQ EV DDQ DQ31 NC NC DQ16 V SSQ FV SS DQM3 A3 A2 DQM2 V DD G A 4A 5A 6 A 1 0 A 0A 1 H A7 A8 A12 NC BA1 A11 J CLK CKE A9 BA0 CS RAS KD Q M 1 N C N C C A S WE DQM0 LV DDQ DQ8 V SS VDD DQ7 V SSQ MV SSQ DQ10 DQ9 DQ6 DQ5 V DDQ NV SSQ DQ12 DQ14 DQ1 DQ3 V DDQ PD Q 1 1 V DDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 V SS VDD DQ0 DQ2 Pin Name Pin Function CLK System Clock CS Chip Select CKE Clock Enable A0 ~ A12 Address BA0 ~ BA1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DQM0 ~ DQM3 Data Input/Output Mask DQ0 ~ 31 Data Input/Output VDD/VSS Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground Package Dimension and Pin Configuration < Bottom View*1 > < Top View*2 > < Top View*2 > Symbol Min Typ Max A - 1.30 1.40 A1 0.30 0.35 0.40 E- 1 1 . 0 0 - E1 -6 . 4 0- D - 13.00 - D1 -1 1 . 2 0- e- 0 . 8 0 - b 0.40 0.45 0.50 z-- 0 . 1 0 [Unit:mm] 52 163 4897 F E D C B J H G A e D D/2 E E/2 zbSubstrate(2Layer) #A1 Ball Origin Indicator M L K R P N K4M513233E-XXXX SAMSUNG Week A

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 70°C) NOTES : 1. VIH (max) = 5.3V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ. Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 2.7 3.0 3.6 V VDDQ 2.7 3.0 3.6 V Input logic high voltage VIH 2.2 3.0 VDDQ + 0.3 V 1 Input logic low voltage VIL -0.3 0 0.5 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA Input leakage current ILI -10 - 10 uA 3 CAPACITANCE (VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV) Pin Symbol Min Max Unit Note Clock CCLK 3.0 12.0 pF RAS, CAS, WE, CS, CKE CIN 3.0 12.0 pF DQM CIN 1.5 6.0 pF Address CADD 3.0 12.0 pF DQ0 ~ DQ31 COUT 3.0 6.5 pF ABSOLUTE MAXIMUM RATINGS NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1.0 W Short circuit current I OS 50 mA

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 70°C) NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Internal TCSR can be supported(In commercial Temp : Max 40°C/Max 70°C) 4. K4M513233E-M(E)C 5. K4M513233E-M(E)L 6. K4M513233E-M(E)F** 7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ). Parameter Symbol Test Condition Version Unit Note -75 -1H -1L Operating Current (One Bank Active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 170 160 150 mA 1 Precharge Standby Current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 1.5 mA ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 1.5 Precharge Standby Current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 20 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 Active Standby Current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 8 mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 8 Active Standby Current in non power-down mode (One Bank Active) ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 45 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 40 mA Operating Current (Burst Mode) ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 230 210 210 mA 1 Refresh Current ICC5 tRC ≥ tRC(min) 350 330 300 mA 2 Self Refresh Current ICC6 CKE ≤ 0.2V -C 1800 uA -L 1500 5 Internal TCSR Max 40 Max 70 °C 3 Full Array 850 1300 uA 61/2 of Full Array 600 900 1/4 of Full Array 500 700

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) NOTES: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command (tRP). 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. Parameter Symbol Version Unit Note -75 -1H -1L Row active to row active delay tRRD(min) 15 19 19 ns 1 RAS to CAS delay tRCD(min) 19 19 24 ns 1 Row precharge time tRP(min) 19 19 24 ns 1 Row active time tRAS(min) 45 50 60 ns 1 tRAS(max) 100 us Row cycle time tRC(min) 64 69 84 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to Active delay tDAL(min) tRDL + tRP - 3 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 4 Number of valid output data CAS latency=3 2 ea 5Number of valid output data CAS latency=2 1 Number of valid output data CAS latency=1 0

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM AC CHARACTERISTICS(AC operating conditions unless otherwise noted) NOTES : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Parameter Symbol -75 -1H -1L Unit Note Min Max Min Max Min Max CLK cycle time CAS latency=3 tCC 7.5 1000 9.5 1000 9.5 1000 ns 1CLK cycle time CAS latency=2 tCC 9.5 9.5 12 CLK cycle time CAS latency=1 tCC - - 25 CLK to valid output delay CAS latency=3 tSAC 5.4 7 7 ns 1,2CLK to valid output delay CAS latency=2 tSAC 7 7 8 CLK to valid output delay CAS latency=1 tSAC - - 20 Output data hold time CAS latency=3 tOH 2.5 2.5 2.5 ns 2Output data hold time CAS latency=2 tOH 2.5 2.5 2.5 Output data hold time CAS latency=1 tOH - - 2.5 CLK high pulse width tCH 2.5 3.0 3.0 ns 3 CLK low pulse width tCL 2.5 3.0 3.0 ns 3 Input setup time tSS 2.0 2.5 2.5 ns 3 Input hold time tSH 1.0 1.5 1.5 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 tSHZ 5.4 7 7 nsCAS latency=2 7 7 8 CAS latency=1 - - 20

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) NOTES : 1. OP Code : Operand Code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only after setting partial self refresh mode of EMRS. 4. BA0 ~ BA1 : Bank select addresses. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A12, A11, A9 ~ A0 Note Register Mode Register Set H X L L L L X OP CODE 1, 2 Refresh Auto Refresh H H L L L H X X Self Refresh Entry L 3 Exit L H L H H H X X H X X X 3 Bank Active & Row Addr. H X L L H H X V Row Address Read & Column Address Auto Precharge Disable H X L H L H X V L Column Address (A0~A8) Auto Precharge Enable H 4, 5 Write & Column Address Auto Precharge Disable H X L H L L X V L Column Address (A0~A8) Auto Precharge Enable H 4, 5 Burst Stop H X L H H L X X 6 Precharge Bank Selection H X L L H L X V L X All Banks X H Clock Suspend or Active Power Down Entry H L H X X X X XL V V V Exit L H X X X X X Precharge Power Down Mode Entry H L H X X X X X L H H H Exit L H H X X X X L V V V DQM H X V X 7 No Operation Command H X H X X X X X L H H H

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM Normal MRS Mode Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 Mode Select 0 1 0 4 4 1 1 Reserved 0 1 1 3 BA1 BA0 Mode 0 1 1 8 8 Write Burst Length 1 0 0 Reserved 0 0 Setting for Nor- mal MRS 1 0 0 Reserved Reserved A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved

0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved

1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved

Register Programmed with Normal MRS Address BA0 ~ BA1 A12 ~ A10/AP A9*2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function "0" Setting for Normal MRS RFU*1 W.B.L Test Mode CAS Latency BT Burst Length A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Extended MRS Address BA1 BA0 A12 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function Mode Select RFU*1 DS RFU*1 PASR NOTES: 1. RFU(Reserved for future use) should stay "0" during MRS cycle. 2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. Mode Select Driver Strength PASR BA1 BA0 Mode A6 A5 Driver Strength A2 A1 A0 Size of Refreshed Array 0 0 Normal MRS 0 0 Full 0 0 0 Full Array 0 1 Reserved 0 1 1/2 0 0 1 1/2 of Full Array 1 0 EMRS for Mobile SDRAM 1 0 Reserved 0 1 0 1/4 of Full Array 1 1 Reserved 1 1 Reserved 0 1 1 Reserved Reserved Address 1 0 0 Reserved A12~A10/AP A9 A8 A7 A4 A3 1 0 1 Reserved 0 0 0 0 0 0 1 1 0 Reserved 1 1 1 Reserved EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength) Full Page Length x32 : 512Mb(512)

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM 1. In order to save power consumption, Mobile SDRAM has PASR option. 2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode :Full Array, 1/2 of Full Array and 1/4 of Full Array. BA1=0 Partial Self Refresh Area 1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range : Max 40 °C and Max 70 °C(for Commercial Temperature). 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. Temperature Range Self Refresh Current (Icc6) Unit - C -L - F Full Array 1/2 of Full Array 1/4 of Full Array Max 70 °C 1800 1500 1300 900 700 uA Max 40 °C 850 600 500 BA0=0 BA1=0 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 BA1=1 BA0=0 Partial Array Self Refresh Temperature Compensated Self Refresh B. POWER UP SEQUENCE 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS. EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used. The default state without EMRS command issued is the full driver strength and full array refreshed. The device is now ready for the operation selected by EMRS. For operating with DS or PASR, set DS or PASR mode in EMRS setting stage. In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set. - Full Array - 1/2 Array - 1/4 Array

K4M513233E - M(E)C/L/F February 2004 Mobile-SDRAM C. BURST SEQUENCE 1. BURST LENGTH = 4 Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 2. BURST LENGTH = 8 Initial Address Sequential Interleave A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0