K4H510838C-ZLCC

K4H511638C-Z SAMSUNG | Alldatasheet

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Technical content

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) * Samsung Electronics reserves the right to change products or specification without notice. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. 512Mb C-die DDR SDRAM Specification

60 FBGA with Pb-Free

(RoHS compliant)

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) Table of Contents

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16)

Revision History

Revision Month Year History

0.0 October 2004 - First version for internal review

1.0 February 2005 - Release the Rev. 1.0 spec 1.1 June 2005 - Changed master format.

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16)

• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs -. Read latency : DDR333(2.5 Clock), DDR400(3 Clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA Pb-Free package
• RoHS compliant CC(DDR400@CL=3) B3(DDR333@CL=2.5) Speed @CL2 - 133MHz Speed @CL2.5 166MHz 166MHz Speed @CL3 200MHz - CL-tRCD-tRP 3-3-3 2.5-3-3 Part No. Org. Max Freq. Interface Package K4H510438C-ZC/LCC 128M x 4 CC(DDR400@CL=3) SSTL2 60ball FBGA K4H510438C-ZC/LB3 B3(DDR333@CL=2.5) K4H510838C-ZC/LCC 64M x 8 CC(DDR400@CL=3) SSTL2 60ball FBGA K4H510838C-ZC/LB3 B3(DDR333@CL=2.5) K4H511638C-ZC/LCC 32M x 16 CC(DDR400@CL=3) SSTL2 60ball FBGA K4H511638C-ZC/LB3 B3(DDR333@CL=2.5)

1.0 Key Features

2.0 Ordering Information

3.0 Operating Frequencies

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) DM is internally loaded to match DQ and DQS identically. Row & Column address configuration Organization Row Address Column Address 128Mx4 A0~A12 A0-A9, A11, A12 64Mx8 A0~A12 A0-A9, A11 32Mx16 A0~A12 A0-A9

4.0 Ball Description (Bottom View)

1 VSSQ NC NC NC NC VREF

2 NC VDDQ VSSQ VDDQ VSSQ VSS CK A12 A11 A8 A6 A4

3 VSS DQ3 NC DQ2 DQS DM CK C K E A 9A 7A 5 V S S

7 VDD DQ0 NC DQ1 NC NC WE RAS BA1 A0 A2 VDD

8 NC VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3

9 VDDQ NC NC NC NC NC

2 DQ7 VDDQ VSSQ VDDQ VSSQ VSS CK A12 A11 A8 A6 A4

3 VSS DQ6 DQ5 DQ4 DQS DM CK CKE A9 A7 A5 VSS

7 VDD DQ1 DQ2 DQ3 NC NC WE RAS BA1 A0 A2 VDD

8 DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3

1 VSSQ DQ14 DQ12 DQ10 DQ8 VREF

2 DQ15 VDDQ VSSQ VDDQ VSSQ VSS CK A12 A11 A8 A6 A4

3 VSS DQ13 DQ11 DQ9 UDQS UDM CK CKE A9 A7 A5 VSS

7 VDD DQ2 DQ4 DQ6 LDQS LDM WE RAS BA1 A0 A2 VDD

9 VDDQ DQ1 DQ3 DQ5 DQ7 NC

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16)

5.0 Package Physical Dimension

60Ball FBGA 512Mb Package Dimension 10.00 ± 0.10 0.80 6.40 1.60 WINDOW MOLD AREA x8 = B 5.50 1.00 11.00x11 A (Datum B) 12.00 ± 0.10 A B C D E F G H J K L M 0.50 60-∅0.45 ± 0.05

0.20 M A B

1.00MAX 12.00 ± 0.10 12.00 ± 0.10 10.00 ± 0.10 #A1

1.20 MAX

0.45 ± 0.05 0.80 x2= 1.600.80 x2 = #A1 MARK(option) 1.00 0.80 4-CORNER MARK(option) (Datum A) 987654321 (0.90)(0.90) (1.80) 0.80 x4 = 0.50 3.20

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16)

6.0 Block Diagram (32Mb x 4 / 16Mb x 8 / 8Mb x 16 I/O x4 Banks)

Row DecoderCol. Buffer Data Input Register Serial to parallel 16Mx8/ 8Mx16/ 4Mx32 16Mx8/ 8Mx16/ 4Mx32 16Mx8/ 8Mx16/ 4Mx32 16Mx8/ 8Mx16/ 4Mx32 Sense AMP 2-bit prefetch Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register DLL Strobe Gen. CK, CK ADD LCKE CK, CK CKE CS RAS CAS WE CK, CK LCAS LRAS LCBR LWE LWCBR LRAS LCBR CK, CK x8/16/32 x8/16/32 x4/8/16 x4/8/16 LWE LDM (x4x8) x4/8/16 DQi Data Strobe LUDM (x16) LDM (x4x8) LUDM (x16) DM Input Register LDM (x4x8) LUDM (x16)

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) SYMBOL TYPE DESCRIPTION CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE Low provides PRECHARGE POWER- DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughput READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS Low level after Vdd is applied upon 1st power up, After VREF has become stable during the power on and ini- tialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH entry and exit, VREF must be maintained to this input. CS Input Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs : RAS , CAS and WE (along with CS) define the command being entered. LDM,(UDM) Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15. DM may be driven high, low, or floating during READs. BA0, BA1 Input Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE- CHARGE command is being applied. A [0 : 12] Input Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem- ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter- mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). DQ I/O Data Input/Output : Data bus LDQS,(U)DQS I/O Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen- tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15 NC - No Connect : No internal electrical connection is present. VSSQ Supply DQ Ground. VSS Supply Ground. VREF Input SSTL_2 reference voltage.

7.0 Input/Output Function Description

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code. A0 ~ A13& BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9, A11 ~ A12 Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 Refresh Auto Refresh H H LL L H X Self Refresh Entry L 3 Exit L H LH H H X HX X X 3 Bank Active & Row Addr. H X L L H H V Row Address Read & Column Address Auto Precharge Disable HX L H L H V L Column Address Auto Precharge Enable H 4 Write & Column Address Auto Precharge Disable HX L H L L V L Column Address Auto Precharge Enable H 4, 6 Burst Stop H X L H H L X 7 Precharge Bank Selection HX L L H L VL X All Banks X H 5 Active Power Down Entry H L HX X X XLV V V Exit L H X X X X Precharge Power Down Mode Entry H L HX X X X LH H H Exit L H HX X X LV V V DM(UDM/LDM for x16 only) H X X 8 No operation (NOP) : Not defined H X HX X X X LH H H 9

8.0 Command Truth Table

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) 32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks Double Data Rate SDRAM The K4H510438C / K4H510838C / K4H511638C is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Syn- chronous features with Data Strobe allow extremely high perfo rmance up to 400Mb/s per pin. I/ O transactions are possible on bot h edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be usefu l for a variety of high performance memory system applications. Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1.5 W Short circuit current I OS 50 mA Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C) Note : 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track vari- ations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0. Parameter Symbol Min Max Unit Note Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) V DD 2.3 2.7 Supply voltage(for device with a nominal VDD of 2.6V for DDR400) V DD 2.5 2.7 I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) V DDQ 2.3 2.7 V I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR400) V DDQ 2.5 2.7 I/O Reference voltage V REF 0.49*VDDQ 0.51*VDDQ V 1 I/O Termination voltage(system) V TT VREF-0.04 V REF+0.04 V2 Input logic high voltage V IH(DC) V REF+0.15 V DDQ+0.3 V Input logic low voltage V IL(DC) -0.3 V REF-0.15 V Input Voltage Level, CK and CK inputs V IN(DC) -0.3 V DDQ+0.3 V Input Differential Voltage, CK and CK inputs V ID(DC) 0.36 V DDQ+0.6 V 3 V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4 Input leakage current I I -2 2 uA Output leakage current I OZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9m A

9.0 General Description

10.0 Absolute Maximum Rating

11.0 DC Operating Conditions

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) Conditions Symbol Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. IDD0 Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition IDD1 Precharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Vin = Vref for DQ,DQS and DM. IDD2P Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM IDD2F Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs stable at >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM IDD2Q Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Vin = Vref for DQ,DQS and DM IDD3P Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax; tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle IDD3N Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at 7.5ns for DDR266(A2), CL=2.5 at tCK=7.5ns for DDR266(B0), tCK=6ns for DDR333, CL=3 at tCK=5ns for DDR400; 50% of data changing on every transfer; lout = 0 m A IDD4R Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at tCK=7.5ns for DDR266(A2), CL=2.5 at tCK=7.5ns for DDR266(B0), 6ns for DDR333, 5ns for DDR400; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst IDD4W Auto refresh current; tRC = tRFC(min) which is 12*tCK for DDR200 at tCK=10ns; 16*tCK for DDR266 at tCK=7.5ns; 20*tCK for DDR333 at tCK=6ns, 24*tCK for DDR400 at tCK=5ns; distributed refresh IDD5 Self refresh current; CKE =< 0.2V; External clock on; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400. IDD6 Operating current - Four bank operation ; Four bank interleaving with BL=4 -Refer to the following page for detailed test condition IDD7A ( TA= 25°C, f=100MHz) Note : 1.These values are guaranteed by design and are tested on a sample basis only. 2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system. 3. Unused pins are tied to ground. peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). Parameter Symbol Min Max DeltaCap(max) Unit Note Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) CIN1 1.5 2.5 0.5 pF 4 Input capacitance( CK, CK ) CIN2 1.5 2.5 0.25 pF 4 Data & DQS input/output capacitance COUT 3.5 4.5 0.5 pF 1,2,3,4 Input capacitance(DM for x4/8, UDM/LDM for x16) CIN3 3.5 4.5 pF 1,2,3,4

12.0 DDR SDRAM Spec Items & Test Conditions

13.0 Input/Output Capacitance

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) IDD7A : Operating current: Four bank operation 1. Typical Case: Fro DDR200,266,333: Vdd = 2.5V, T=25’C; For DDR400: Vdd=2.6V,T=25’C Worst Case : Vdd = 2.7V, T= 10’ C 2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *50% of data changing at every burst - A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *50% of data changing at every burst - B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *50% of data changing at every burst - CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing *50% of data changing at every transfer Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT IDD1 : Operating current: One bank operation 1. Typical Case: Fro DDR200,266,333: Vdd = 2.5V, T=25’C; For DDR400: Vdd=2.6V,T=25’C Worst Case : Vdd = 2.7V, T= 10’c 2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 3. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing *50% of data changing at every transfer Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT

14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) (VDD=2.7V, T = 10°C) Symbol 128Mx4 (K4H510438C) Unit Notes CC(DDR400@CL=3) B3(DDR333@CL=2.5) IDD0 120 105 mA IDD1 150 135 mA IDD2P 5 5 mA IDD2F 30 30 mA IDD2Q 25 25 mA IDD3P 45 30 mA IDD3N 60 45 mA IDD4R 155 140 mA IDD4W 175 150 mA IDD5 220 205 mA IDD6 Normal 5 5 mA Low power 3 3 mA Optional IDD7A 385 360 mA Symbol 64Mx8 (K4H510838C) Unit Notes CC(DDR400@CL=3) B3(DDR333@CL=2.5) IDD0 120 105 mA IDD1 150 135 mA IDD2P 5 5 mA IDD2F 30 30 mA IDD2Q 25 25 mA IDD3P 45 30 mA IDD3N 60 45 mA IDD4R 155 140 mA IDD4W 175 150 mA IDD5 220 205 mA IDD6 Normal 5 5 mA Low power 3 3 mA Optional IDD7A 385 360 mA Symbol 32Mx16 (K4H511638C) Unit Notes CC(DDR400@CL=3) B3(DDR333@CL=2.5) IDD0 120 105 mA IDD1 160 140 mA IDD2P 5 5 mA IDD2F 30 30 mA IDD2Q 25 25 mA IDD3P 45 30 mA IDD3N 60 45 mA IDD4R 190 170 mA IDD4W 215 185 mA IDD5 220 205 mA IDD6 Normal 5 5 mA Low power 3 3 mA Optional IDD7A 400 380 mA

15.0 DDR SDRAM IDD spec table

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. Parameter/Condition Symbol Min Max Unit Note Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Parameter Specification DDR400 DDR333 DDR200/266 Maximum peak amplitude allowed for overshoot TBD TBD 1.5 V Maximum peak amplitude allowed for undershoot TBD TBD 1.5 V The area between the overshoot signal and VDD must be less than or equal to TBD TBD 4.5 V-ns The area between the undershoot signal and GND must be less than or equal to TBD TBD 4.5 V-ns 0.5 0.6875 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.3125 6.5 7.0 VDD Overshoot Maximum Amplitude = 1.5V Area = 4.5V-ns Maximum Amplitude = 1.5V undershoot GND Volts (V) Tims(ns) AC overshoot/Undershoot Definition

16.0 AC Operating Conditions

17.0 AC Overshoot/Undershoot specification for Address and Control Pins

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) Parameter Specification DDR400 DDR333 DDR200/266 Maximum peak amplitude allowed for overshoot TBD TBD 1.2 V Maximum peak amplitude allowed for undershoot TBD TBD 1.2 V The area between the overshoot signal and VDD must be less than or equal to TBD TBD 2.4 V-ns The area between the undershoot signal and GND must be less than or equal to TBD TBD 2.4 V-ns VDDQ Overshoot Maximum Amplitude = 1.2V Area = 2.4V-ns Maximum Amplitude = 1.2V undershoot GND Volts (V) Tims(ns) DQ/DM/DQS AC overshoot/Undershoot Definition

18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) Parameter Symbol CC (DDR400@CL=3.0) (DDR333@CL=2.5) Unit Note Min Max Min Max Row cycle time tRC 55 60 ns Refresh row cycle time tRFC 70 72 ns Row active time tRAS 40 70K 42 70K ns RAS to CAS delay tRCD 15 18 ns Row precharge time tRP 15 18 ns Row active to Row active delay tRRD 10 12 ns Write recovery time tWR 15 15 ns Last data in to Read command tWTR 2 1 tCK Clock cycle time CL=2.0 tCK -- 7 . 5 1 2 n s C L = 2 . 5 61 261 2 n s CL=3.0 5 10 - - Clock high level width tCH 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 tCK DQS-out access time from CK/CK tDQSCK -0.55 +0.55 -0.6 +0.6 ns Output data access time from CK/CK tAC -0.65 +0.65 -0.7 +0.7 ns Data strobe edge to ouput data edge tDQSQ - 0.4 - 0.45 ns 22 Read Preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.72 1.28 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 ns 13 DQS-in hold time tWPRE 0.25 0.25 tCK DQS falling edge to CK rising-setup time tDSS 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 tCK Address and Control Input setup time(fast) tIS 0.6 0.75 ns 15, 17~19 Address and Control Input hold time(fast) tIH 0.6 0.75 ns 15, 17~19 Address and Control Input setup tIS 0.7 0.8 ns 16~19 Address and Control Input hold time(slow) tIH 0.7 0.8 ns 16~19 Data-out high impedence time from CK/CK tHZ -0.65 +0.65 -0.7 +0.7 ns 11 Data-out low impedence time from CK/CK tLZ -0.65 +0.65 -0.7 +0.7 ns 11 Mode register set cycle time tMRD 10 12 ns DQ & DM setup time to DQS tDS 0.4 0.45 ns j, k DQ & DM hold time to DQS tDH 0.4 0.45 ns j, k Control & Address input pulse width tIPW 2.2 2.2 ns 18 DQ & DM input pulse width tDIPW 1.75 1.75 ns 18 Exit self refresh to non-Read command tXSNR 75 75 ns Exit self refresh to read command tXSRD 200 200 tCK Refresh interval time tREFI 7.8 7.8 us 14 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - ns 21 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - ns 20, 21 Data hold skew factor tQHS 0.5 0.55 ns 21 DQS write postamble time tWPST 0.4 0.6 0.4 0.6 tCK 12 Active to Read with Auto precharge command tRAP 15 18 Autoprecharge write recovery + Precharge time tDAL (tWR/tCK) (tRP/tCK) (tWR/tCK) (tRP/tCK) tCK 23

19.0 AC Timming Parameters & Specifications

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM Table 2 : Input Setup & Hold Time Derating for Slew Rate Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only) Table 6 : Output Slew Rate Characteristice (X16 Devices only) Table 7 : Output Slew Rate Matching Ratio Characteristics AC CHARACTERISTICS DDR333 DDR266 DDR200 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX Units Notes DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW TBD TBD TBD TBD 0.5 4.0 V/ns a, m Input Slew Rate ∆tIS ∆tIH Units Notes

0.5 V/ns 0 0 ps i

0.4 V/ns +50 0 ps i

0.3 V/ns +100 0 ps i

Input Slew Rate ∆tDS ∆tDH Units Notes

0.5 V/ns 0 0 ps k

0.4 V/ns +75 +75 ps k

0.3 V/ns +150 +150 ps k

Delta Slew Rate ∆tDS ∆tDH Units Notes +/- 0.0 V/ns 0 0 ps j Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h AC CHARACTERISTICS DDR266B DDR200 PARAMETER MIN MAX MIN MAX Notes Output Slew Rate Matching Ratio (Pullup to Pulldown) TBD TBD 0.67 1.5 e,m

20.0 System Characteristics for DDR SDRAM

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec- tronics). 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under nor- mal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is recognized as LOW. 7. Enables on.chip refresh and address counters. 8. IDD specifications are tested after the device is properly initialized. 9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK, is VREF. 10. The output timing reference voltage level is VTT. 11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 15. For command/address input slew rate ≥ 1.0 V/ns 16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns Output VDDQ 50Ω 30pF(Vout) Figure 1 : Timing Reference Load

21.0 Component Notes

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) Component Notes 17. For CK & CK slew rate ≥ 1.0 V/ns 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(ac) and VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 21. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers. 22. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 23. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks

Rev. 1.1 June. 2005 DDR SDRAMDDR SDRAM 512Mb C-die (x4, x8, x16) b. Pulldown slew rate is measured under the test conditions shown in Figure 3. Output Test point VDDQ 50Ω Figure 3 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2. Output Test point VSSQ 50Ω Figure 2 : Pullup slew rate test load

22.0 System Notes

Figure 3. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1.

1. The full variation in driver current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines

the of the V-I curve of Figure 3 and 4.

1. It is recommended that the "typical" IBIS V-I curve lie within the inner bounding lines of the V-I curves of Figure 3 and 4.
2. The full variation in the ratio of the "typical" IBIS pullup to "typical" IBIS pulldown current should be unity +/- 10%, for device drain to

23.0 IBIS : I/V Characteristics for Input and Output Buffers

Table 8. Full Strength Driver Characteristics

Figure 4. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)

Table 9. Weak Driver Characteristics