K4H510638E-TC/LB0

K4H510738E SAMSUNG | Alldatasheet

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DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 Stacked 512Mb E-die DDR SDRAM Specification Revision 1.0 (x4/x8)

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 st. 512Mb E-die Revision History Revision 1.0 (July, 2003) - First version release.

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003

• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe DQS
• Four banks operation
• Differential clock inputs(CK and CK
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package

Ordering Information

Part No. Org. Max Freq. Interface Package K4H510638E-TC/LAA st.128M x 4 AA(DDR266@CL=2) SSTL2 66pin TSOP IIK4H510638E-TC/LA2 A2(DDR266@CL=2) K4H510638E-TC/LB0 B0(DDR266@CL=2.5) K4H510738E-TC/LAA st.64M x 8 AA(DDR266@CL=2) SSTL2 66pin TSOP IIK4H510738E-TC/LA2 A2(DDR266@CL=2) K4H510738E-TC/LB0 B0(DDR266@CL=2.5) Key Features *CL : CAS Latency Operating Frequencies AA(DDR266@CL=2.0) A2(DDR266@CL=2.0) B0(DDR266@CL=2.5) Speed @CL2 133MHz 133MHz 100MHz Speed @CL2.5 133MHz 133MHz 133MHz CL-tRCD-tRP 2-2-2 2-3-3 2.5-3-3

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 Pin Description DM is internally loaded to match DQ and DQS identically. stacked 512Mb TSOP-II Package Pinout Row & Column address configuration VDD 1 66Pin TSOPII (400mil x 875mil) DQ0 2 VDDQ 3 NC 4 DQ1 5 VSSQ 6 NC 7 DQ2 8 VDDQ 9 NC 10 DQ3 11 VSSQ 12 BA0 CS0 RAS CAS WE NC 15VDDQ NC 13 VDD AP/A10 BA1 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ A11 CKE0 CK DM VREF VSSQ NC VSS (0.65mm Pin Pitch) NC NC NC NC CS1 VDD NC DQS NC VSS CK CKE1 A VSS NC V SSQ NC DQ VDDQ NC NC V SSQ NC DQ VDDQ A11 CKE0 CK DM VREF VSSQ NC VSS NC DQS NC VSS CK CKE1 A VDD NC VDDQ NC DQ0 VSSQ NC NC V DDQ NC DQ1 VSSQ BA0 CS0 RAS CAS WE NC VDDQ NC VDD AP/A10 BA1 NC NC NC NC CS1 VDD Bank Address BA0~BA1 Auto Precharge A10 Organization Row Address Column Address st.128Mx4 A0~A12 A0-A9, A11 st.64Mx8 A0~A12 A0-A9 st.128Mb x 4 st.64Mb x 8

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 Units : Millimeters NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY 66pin TSOPII / Package dimension Package Physical Dimension Block Diagram 64Mx4 64Mx4 CK,CK,CAS RAS,WE,DM CKE1,CS1 CKE0,CS0 I/O0-I/O3,DQS A0-A12,BA0,BA1 32Mx8 32Mx8 CK,CK,CAS RAS,WE,DM CKE1,CS1 CKE0,CS0 I/O 0 ~ I/O 3, DQS A0-A12, BA0,BA1 st.128Mb x 4 st.64Mb x 8 10.16 (0.50) 0.45~0.75 0.125 +0.075 - 0.035 0×~8× (4×) (R0.25) (R0.2 0.45~0.75 0.25TYP 22.62MAX 22.22 ± 0.10 2.54(max) 0.05(min) 11.76±0.20 #1 #33 #66 #34

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 SYMBOL TYPE DESCRIPTION CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled dur- ing power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being stable on power-up. CS Input Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs : RAS , CAS and WE (along with CS) define the command being entered. DM Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. BA0, BA1 Input Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE- CHARGE command is being applied. A [0 : 12] Input Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem- ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter- mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). DQ I/O Data Input/Output : Data bus DQS I/O Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen- tered in write data. Used to capture write data. NC - No Connect : No internal el ectrical connection is present. VDDQ Supply DQ Power Supply : +2.5V ± 0.2V. VSSQ Supply DQ Ground. VDD Supply Power Supply : +2.5V ± 0.2V (device specific). VSS Supply Ground. VREF Input SSTL_2 reference voltage. Input/Output Function Description

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 Command Truth Table (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9, A11,A12 Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 Refresh Auto Refresh H H LL L H X Self Refresh Entry L 3 Exit L H LH H H X HX X X 3 Bank Active & Row Addr. H X L L H H V Row Address Read & Column Address Auto Precharge Disable HX L H L H V L Column Address Auto Precharge Enable H 4 Write & Column Address Auto Precharge Disable HX L H L L V L Column Address Auto Precharge Enable H 4, 6 Burst Stop H X L H H L X 7 Precharge Bank Selection HX L L H L VL X All Banks X H 5 Active Power Down Entry H L HX X X XLV V V Exit L H X X X X Precharge Power Down Mode Entry H L HX X X X LH H H Exit L H HX X X LV V V DM(UDM/LDM for x16 only) H X X 8 No operation (NOP) : Not defined H X HX X X X LH H H 9 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM(x4x8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Note :

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 st. 32M x 4Bit x 4 Banks / st. 16M x 8Bit x 4 Banks Double Data Rate SDRAM The K4H510638E / K4H510738E is 536,870,912 bits of double data rate synchronous DRAM or ganized as 4x 33,553,332 / 4x 16,777,216 words by 4/ 8bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 266Mb/s per pin. I/O trans actions are possible on both edges of DQS. Range of operating fre- quencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance mem- ory system applications. General Description Absolute Maximum Rating Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1.5 W Short circuit current I OS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C) Parameter Symbol Min Max Unit Note Supply voltage(for device with a nominal VDD of 2.5V) V DD 2.3 2.7 I/O Supply voltage V DDQ 2.3 2.7 V I/O Reference voltage V REF 0.49*VDDQ 0.51*VDDQ V 1 I/O Termination voltage(system) V TT VREF-0.04 V REF+0.04 V2 Input logic high voltage V IH(DC) V REF+0.15 V DDQ+0.3 V Input logic low voltage V IL(DC) -0.3 V REF-0.15 V Input Voltage Level, CK and CK inputs V IN(DC) -0.3 V DDQ+0.3 V Input Differential Voltage, CK and CK inputs V ID(DC) 0.36 V DDQ+0.6 V 3 V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4 Input leakage current I I -2 2 uA Output leakage current I OZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9m A 1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. Note :

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 DDR SDRAM Spec Items & Test Conditions Conditions Symbol Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. IDD0 Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition IDD1 Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=10ns for DDR200,7.5ns for DDR266, 6ns for DDR333; Vin = Vref for DQ,DQS and DM. IDD2P Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM IDD2F Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333; Address and other control inputs stable at >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM IDD2Q Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333; Vin = Vref for DQ,DQS and DM IDD3P Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax; tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle IDD3N Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at 7.5ns for DDR266(A2), CL=2.5 at 7.5ns for DDR266(B0), 6ns for DDR333; 50% of data changing on every transfer; lout = 0 m A IDD4R Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=2 at tCK= 10ns for DDR200, CL=2 at tCK=7.5ns for DDR266(A2), CL=2.5 at tCK=7.5ns for DDR266(B0), 6ns for DDR333; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst IDD4W Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at tCK=10ns; 10*tCK for DDR266 at tCK=7.5ns; 12*tCK for DDR333 at tCK=6ns; distributed refresh IDD5 Self refresh current; CKE =< 0.2V; External clock on; tCK = 10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333. IDD6 Orerating current - Four bank operation ; Four bank interleaving with BL=4 -Refer to the following page for detailed test condition IDD7A Input/Output Capacitance (VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz) Parameter Symbol Min Max Delta Unit Note Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE0,CKE1, CS0, CS1 , RAS,CAS, WE) CIN1 2 3 0.5 pF 4 Input capacitance( CK, CK ) CIN2 2 3 0.25 pF 4 Data & DQS input/output capacitance COUT 4 5 0.5 pF 1,2,3,4 Input capacitance(DM for x4/8,) CIN3 4 5 pF 1,2,3,4 1.These values are guaranteed by design and are tested on a sample basis only. 2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system. 3. Unused pins are tied to ground. VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). Note :

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 IDD7A : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25’ C 2. Worst Case : Vdd = 2.7V, T= 10’ C 3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst - A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst - AA(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > IDD1 : Operating current: One bank operation 1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 2. Timing patterns - B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - AA(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing *100% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 DDR SDRAM IDD spec table (VDD=2.7V, T = 10°C) Symbol st 128Mx4 (K4H510638E) Unit Notes AA(DDR266@CL=2.0) A2(DDR266@CL=2.0) B0(DDR266@CL=2.5) IDD0 100 100 100 mA IDD1 120 120 120 mA IDD2P 6 6 6 mA IDD2F 40 40 40 mA IDD2Q 36 36 36 mA IDD3P 35 35 35 mA IDD3N 65 65 65 mA IDD4R 165 165 165 mA IDD4W 140 140 140 mA IDD5 180 180 180 mA IDD6 Normal 6 6 6 mA Low power 3 3 3 mA Optional IDD7A 290 290 290 mA Symbol st 64Mx8 (K4H510738E) Unit Notes AA(DDR266@CL=2.0) A2(DDR266@CL=2.0) B0(DDR266@CL=2.5) IDD0 100 100 100 mA IDD1 120 120 120 mA IDD2P 6 6 6 mA IDD2F 40 40 40 mA IDD2Q 36 36 36 mA IDD3P 35 35 35 mA IDD3N 65 65 65 mA IDD4R 165 165 165 mA IDD4W 140 140 140 mA IDD5 180 180 180 mA IDD6 Normal 6 6 6 mA Low power 3 3 3 mA Optional IDD7A 290 290 290 mA

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 AC Operating Conditions Parameter/Condition Symbol Min Max-10 Unit Note Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 AC Overshoot/Undershoot specification for Address and Control Pins Parameter Specification DDR333 DDR200/266 Maximum peak amplitude allowed for overshoot TBD 1.5 V Maximum peak amplitude allowed for undershoot TBD 1.5 V The area between the overshoot signal and VDD must be less than or equal to TBD 4.5 V-ns The area between the undershoot signal and GND must be less than or equal to TBD 4.5 V-ns 0.5 0.6875 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.3125 6.5 7.0 VDD Overshoot Maximum Amplitude = 1.5V Area = 4.5V-ns Maximum Amplitude = 1.5V undershoot GND Volts (V) Tims(ns) AC overshoot/Undershoot Definition Notes : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 Overshoot/Undershoot specification for Data, Strobe, and Mask Pins Parameter Specification DDR200/266 Maximum peak amplitude allowed for overshoot 1.2 V Maximum peak amplitude allowed for undershoot 1.2 V The area between the overshoot signal and VDD must be less than or equal to 2.4 V-ns The area between the undershoot signal and GND must be less than or equal to 2.4 V-ns VDDQ Overshoot Maximum Amplitude = 1.2V Area = 2.4V-ns Maximum Amplitude = 1.2V undershoot GND Volts (V) Tims(ns) DQ/DM/DQS AC overshoot/Undershoot Definition

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 AC Timming Parameters & Specifications Parameter Symbol AA (DDR266@CL=2.0) (DDR266@CL=2.0) (DDR266@CL=2.5)) Unit Note Min Max Min Max Min Max Row cycle time tRC 60 65 65 ns Refresh row cycle time tRFC 75 75 75 ns Row active time tRAS 45 120K 45 120K 45 120K ns RAS to CAS delay tRCD 15 20 20 ns Row precharge time tRP 15 20 20 ns Row active to Row active delay tRRD 15 15 15 ns Write recovery time tWR 15 15 15 ns Last data in to Read command tWTR 1 1 1 tCK Col. address to Col. address delay tCCD 1 1 1 tCK Clock cycle time CL=2.0 tCK 7.5 12 7.5 12 10 12 ns CL=2.5 7.5 12 7.5 12 7.5 12 ns DQS-out access time from CK/CK Data strobe edge to ouput data edge tDQSQ - 0.5 - 0.5 - 0.5 ns 12 DQS-in setup time tWPRES 0 0 0 ns 3 DQS-in hold time tWPRE 0.25 0.25 0.25 tCK DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK Address and Control Input setup time(fast) tIS 0.9 0.9 0.9 ns i,5.7~9 Address and Control Input hold time(fast) tIH 0.9 0.9 0.9 ns i,5.7~9 Address and Control Input setup time(slow) tIS 1.0 1.0 1.0 ns i, 6~9 Address and Control Input hold time(slow) tIH 1.0 1.0 1.0 ns i, 6~9 Data-out high impedence time from CK/CK

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM Table 2 : Input Setup & Hold Time Derating for Slew Rate Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate AC CHARACTERISTICS DDR333 DDR266 DDR200 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX Units Notes DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW TBD TBD TBD TBD 0.5 4.0 V/ns a, m Input Slew Rate tIS tIH Units Notes

0.5 V/ns 0 0 ps i

0.4 V/ns +50 0 ps i

0.3 V/ns +100 0 ps i

Input Slew Rate tDS tDH Units Notes

0.5 V/ns 0 0 ps k

0.4 V/ns +75 +75 ps k

0.3 V/ns +150 +150 ps k

(DDR266@CL=2.0) (DDR266@CL=2.0) (DDR266@CL=2.5)) Unit Note Min Max Min Max Min Max Mode register set cycle time tMRD 15 15 15 ns DQ & DM setup time to DQS tDS 0.5 0.5 0.5 ns j, k DQ & DM hold time to DQS tDH 0.5 0.5 0.5 ns j, k Control & Address input pulse width tIPW 2.2 2.2 2.2 ns 8 DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns 8 Power down exit time tPDEX 7.5 7.5 7.5 ns Exit self refresh to non-Read command tXSNR 75 75 75 ns Exit self refresh to read command tXSRD 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 7.8 us 4 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - tHP -tQHS -n s 1 1 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin -n s 1 0 , 1 1 Data hold skew factor tQHS 0.75 0.75 0.75 ns 11 Active to Read with Auto precharge command tRAP 20 20 20 Autoprecharge write recovery + Precharge time tDAL (tWR/tCK) (tRP/tCK) (tWR/tCK) (tRP/tCK) (tWR/tCK) (tRP/tCK) tCK 13

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only) Table 6 : Output Slew Rate Characteristice (X16 Devices only) Table 7 : Output Slew Rate Matching Ratio Characteristics Delta Slew Rate tDS tDH Units Notes +/- 0.0 V/ns 0 0 ps j Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h AC CHARACTERISTICS DDR266 DDR200 PARAMETER MIN MAX MIN MAX Notes Output Slew Rate Matching Ratio (Pullup to Pulldown) TBD TBD 0.67 1.5 e,m

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 Component Notes 1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). 2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 5. For command/address input slew rate ≥ 1.0 V/ns 6. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns 7. For CK & CK slew rate ≥ 1.0 V/ns 8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 9. Slew Rate is measured between VOH(ac) and VOL(ac). 10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 11. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers. 12. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 13. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. Output Test point VSSQ 50Ω Figure 1 : Pullup slew rate test load

DDR SDRAMDDR SDRAM stacked 512Mb E-die (x4/x8) Rev. 1.0 July. 2003 b. Pulldown slew rate is measured under the test conditions shown in Figure 2. Output Test point VDDQ 50Ω Figure 2 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotony.

Figure 3. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1.

1. The full variation in driver current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines

the of the V-I curve of Figure 3 and 4.

1. It is recommended that the "typical" IBIS V-I curve lie within the inner bounding lines of the V-I curves of Figure 3 and 4.
2. The full variation in the ratio of the "typical" IBIS pullup to "typical" IBIS pulldown current should be unity +/- 10%, for device drain to

Table 8. Full Strength Driver Characteristics

Figure 4. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)

Table 9. Weak Driver Characteristics