K4H280438B-TCA0 SAMSUNG | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.1 Features
- 1.2 Operating Frequencies
- 2.1 Package Pintout
- 2.2 Input/Output Function Description
- 3.1 Simplified State Diagram
- 3.2 Basic Functionality
- 3.2.1 Power-Up Sequence
- 3.2.2 Mode Register Definition
- 3.2.2.1 Mode Register Set(MRS)
- 3.2.2.2 Extended Mode Register Set(EMRS)
- 3.2.3 Precharge
- 3.2.4 No Operation(NOP) & Device Deselect
- 3.2.5 Row Active
- 3.2.6 Read Bank
- 3.2.7 Write Bank
- 3.3 Essential Functionality for DDR SDRAM
- 3.3.1 Burst Read Operation
- 3.3.2 Burst Write Operation
- 3.3.3 Read Interrupted by a Read
- 3.3.4 Read Interrupted by a Write & Burst Stop
- 3.3.5 Read Interrupted by a Precharge
- 3.3.6 Write Interrupted by a Write
- 1 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM DDR SDRAM Specification Version 1.0
- 2 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM
Revision History
Version 0 (May, 1998) - First version for internal review Version 0.1(June, 1998) - Added x4 organization Version 0.2(Sep,1998) 1. Added "Issue prcharge command for all banks of the device" as the fourth step of power-up squence. 2. In power down mode timing diagram, NOP condition is added to precharge power down exit. Version 0.3(Dec,1998) - Added QFC Function. - Added DC current value - Reduce I/O capacitance values Version 0.4(Feb,1999) -Added DDR SDRAM history for reference(refer to the following page) -Added low power version DC spec Version 0.5(Apr,1999) -Revised following first showing for JEDEC standard - Added DC target current based on new DC test condition Version 0.6(July 1,1999) 1.Modified binning policy From To -Z (133Mhz) -Z (133Mhz/266Mbps@CL=2) -8 (125Mhz) -Y (133Mhz/266Mbps@CL=2.5) -0 (100Mhz) -0 (100Mhz/200Mbps@CL=2) 2.Modified the following AC spec values *1 : Changed description method for the same functionality. This means no difference from the previous version. 3.Changed the following AC parameter symbol From. To. Output data access time from CK/ CK tDQCK tAC Version 0.61(August 9,1999) - Changed the some values of "write with auto precharge" table for different bank in page 31. From. To. -Z -0 -Z -Y -0 tDQSCK +/- 0.75ns +/- 1ns +/- 0.75ns +/- 0.75ns +/- 0.8ns tCDLR *1 2.5tCK-tDQSS 2.5tCK-tDQSS 1tCK 1tCK 1tCK tHZQ *1 tCK/2 +/- 0.75ns tCK/2 +/- 1ns +/- 0.75ns +/- 0.75ns +/-0.8ns Asserted command For Different Bank 3 4 Old New Old New Read Legal Illegal Legal Illegal Read + AP *1 Legal Illegal Legal Illegal
- 3 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Revision History(continued) Version 0.7 (March, 2000) - Changed 128Mb spec from target to Preliminary version. - Changed partnames as follows. - Changed input cap. spec. - Changed operating condition. - Added Overshoot/Undershoot spec . Vih(max) = 4.2V, the overshoot voltage duration is ≤ 3ns at VDD. . Vil(min) =- 1.5V, the overshoot voltage duration is ≤ 3ns at VSS. - Changed AC parameters as follows. - Added DC spec values. Version 0.71 (April, 2000) - Corrected a typo for tRAS at 133Mhz/CL2.5 from 48ns t0 45ns. - Corrected a typo in "General Information" table from 64Mx4 to 8Mx16. Version 0.72(May,2000) - Changed DC spec item & test condition Version 0.73(June,2000) - Added updated DC spec values - Deleted tDAL in AC parameter Version 1.0(November,2000) - Eliminate "preliminary" from to KM44L32031BT-G(L)Z/Y/0 K4H280438B-TC(L)A2/B0/A0 KM48L16031BT-G(L)Z/Y/0 K4H280838B-TC(L)A2/B0/A0 KM416L8031BT-G(L)Z/Y/0 K4H281638B-TC(L)A2/B0/A0 from to CK/ CK from to Vil/Vih(ac) Vref +/- 0.35V Vref +/- 0.31V V IL /V IH (dc) Vref +/- 0.18V Vref +/- 0.15V from to Comments tDV +/- 0.35tCK - Removed tQH - tHPmin - 0.75ns(PC266) New Definition tHPmin - 1.0ns(PC200) tHP - tCLmin or tCHmin New Definition
- 5 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM
3.3.7 Write Interrupted by a Read & DM
3.3.8 Write Interrupted by a Precharge & DM
3.3.9 Burst Stop
3.3.10 DM masking
3.3.11 Read With Auto Precharge
3.3.12 Write With Auto Precharge
3.3.13 Auto Refresh & Self Refresh
3.3.14 Power Down
- Command Truth Table 5. Functional Truth Table 6. Absolute Maximum Rating 7. DC Operating Conditions & Specifications
7.1 DC Operating Conditions
7.2 DC Specifications
- AC Operating Conditions & Timming Specification
8.1 AC Operating Conditions
8.2 AC Timming Parameters & Specification
- AC Operating Test Conditions 10. Input/Output Capacitance 11. IBIS: I/V Characteristics for Input and Output Buffers
11.1 Normal strength driver
11.2 Half strength driver( will be included in the future)
- QFC function QFC definition QFC timming on Read Operation QFC timming on Write operation with tDQSSmax QFC timming on Write operation with tDQSSmin QFC timming example for interrupted writes operation Timing Diagram
Table 2. : Column address configurtion
- 8 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM General Information Organization 133Mhz w/ CL=2 133Mhz w/ CL=2.5 100Mhz w/ CL=2 32Mx4 K4H280438B-TCA2 K4H280438B-TCB0 K4H280438B-TCA0 K4H280438B-TLA2 K4H280438B-TLB0 K4H280438B-TLA0 16Mx8 K4H280838B-TCA2 K4H280838B-TCB0 K4H280838B-TCA0 K4H280838B-TLA2 K4H280838B-TLB0 K4H280838B-TLA0 8Mx16 K4H281638B-TCA2 K4H281638B-TCB0 K4H281638B-TCA0 K4H281638B-TLA2 K4H281638B-TLB0 K4H281638B-TLA0 T : TSOP2 (400mil x 875mil) A0 : 10ns@CL2 A2 : 7.5ns@CL2 B0 : 7.5ns@CL2.5 C : (Commercial, Normal) L : (Commercial, Low) 04 : x4 08 : x8 16 : x16 32 : x32 64 : 64M 4K/64ms 28 : 128M 4K/64ms 56 : 256M 8K/64ms 51 : 512M 8K/64ms 1G : 1G 16K/32ms H : DDR SDRAM M : 1st Generation A : 2nd Generation B : 3rd Generation C : 4th Generation D : 5th Generation E : 6th Generation K 4 H XX XX X X X - X X Memory DRAM Small Classification Density and Refresh Temperature & Power Package Organization Version Interface (VDD & VDDQ) 1. SAMSUNG Memory : K 2. DRAM : 4 3. Small Classification 4. Density & Refresh 5. Organization 8. Version 9. Package 10. Temperature & Power 11. Speed 3 : 4 Bank 6. Bank 1 2 3 4 5 6 7 8 9 10 11 XX 8 : SSTL-2(2.5V, 2.5V) 7. Interface (VDD & VDDQ) Speed Bank
- Double-data-rate architecture; two data transfers per clock cycle
- Bidirectional data strobe(DQS)
- Four banks operation
- Differential clock inputs(CK and CK )
- DLL aligns DQ and DQS transition with CK transition
- MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave)
- All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
- Data I/O transactions on both edges of data strobe
- Edge aligned data output, center aligned data input
- LDM,UDM/DM for write masking only
- Auto & Self refresh
- 15.6us refresh interval(4K/64ms refresh)
- Maximum burst refresh cycle : 8
- 66pin TSOP II package 1. Key Features
1.1 Features
1.2 Operating Frequencies
Table 1. Operating frequency and DLL jitter
66 PIN TSOP(II)
DM is internally loaded to match DQ and DQS identically.
2.1 Package Pinout
FIgure 1. 128Mb package Pinout Table 2. Column address configuration
- Package Pinout & Dimension
2.2 Input/Output Function Description
Table 3. Input/Output Function Description both edges of CK. Internal clock signals are derived from CK/ CK . an LVCMOS LOW level prior to VREF being stable on power-up. bank selection on systems with multiple banks. CS is considered part of the command code. RAS , CAS , WE Input Command Inputs : RAS , CAS and WE (along with CS ) define the command being entered. CHARGE command is being applied. DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. isolation switches on modules. NC - No Connect : No internal electrical connection is present. V DD Q Supply DQ Power Supply : +2.5V ± 0.2V. V DD Supply Power Supply : +2.5V ± 0.2V (device specific). V REF Input SSTL_2 reference voltage.
0.10 MAX
0.075 MAX[ ]
- [ ] IS ASS ’ Y OUT QUALITY
Figure 2. Package dimension
3.1 Simplified State Diagram
Figure 3. State diagram
3.2.1 Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
- Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
- Start clock and maintain stable condition for a minimum of 200us.
- The minimum of 200us after stable power and clock(CK, CK
), apply NOP & take CKE high.
- Issue precharge commands for all banks of the device.
- Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low"
- Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to
- Issue precharge commands for all banks of the device.
- Issue 2 or more auto-refresh commands.
- Issue a mode register set command with low to A8 to initialize device operation.
*1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6 & 7 is regardless of the order.
3.2 Basic Functionality
Figure 4. Power up and initialization sequence
3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
specific codes for various burst lengths, addressing modes and CAS latencies.
0 Normal
1 Test
0 Sequential
1 Interleave
1 Yes
1 Extended Funtions(EMRS)
Figure 5. Mode Register Set
*1 : MRS can be issued only at all bank precharge state. *2 : Minimum tRP is required to issue MRS command. must occur before a READ command can be issued. normal drive strength and weak drive strength will be included in a future revision of this document. Table 4. Burst address ordering for burst length Figure 6. Mode Register Set sequence
3.2.2.2 Extended Mode Register Set(EMRS)
pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
0 Enable
1 Disable
0 Disable(Default)
1 Enable
1 Weak
Figure 7. Extend Mode Register set
3.2.3 Precharge
3.2.4 No Operation(NOP) & Device Deselect
an active command to the same bank can be initiated.
1 X X All Banks
Table 5. Bank selection for precharge by Bank address bits
3.2.5 Row Active
3.2.6 Read Bank
3.2.7 Write Bank
the values programmed during the MRS command. Figure 8. Bank activation command cycle timing
3.3.1 Burst Read Operation
3.3 Essential Functionality for DDR SDRAM
Figure 9. Burst read operation timing
3.3.2 Burst Write Operation
additional data supplied to the DQ pins will be ignored. Figure 10. Burst write operation timing
- The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown
(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
3.3.3 Read Interrupted by a Read
appears. Read to Read interval is minimum 1 Clock.
3.3.4 Read Interrupted by a Write & Burst Stop
clock cycles for CL=2 and at least 3 clock cycles for CL=2.5 before the Write command. The following functionality establishes how a Write command may interrupt a Read burst.
- For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read
- It is illegal for a Write command to interrupt a Read with autoprecharge command.
Figure 11. Read interrupted by a read timing Figure 12. Read interrupted by a write and burst stop timing.
3.3.5 Read Interrupted by a Precharge
may be given during a Read burst and when a new Bank Activate command may be issued to the same bank.
- For the earliest possible Precharge command without interrupting a Read burst, the Precharge command
- When a Precharge command interrupts a Read burst operation, the Precharge command may be given on
Bank Activate command may be issued to the same bank after tRP.
- For a Read with autoprecharge command, a new Bank Activate command may be issued to the same
precharge operation without interrupting the Read burst as described in 1 above.
- For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of
can only be given on a rising clock edge). the earliest possible Precharge command which does not interrupt the burst. Figure 13. Read interrupted by a precharge timing
3.3.6 Write Interrupted by a Write
device until the programmed burst length is satisfied. Figure 14. Write interrupted by a write timing
state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to avoid the data contention DRAM inside. memory. Read command interrupting write can not be issued at the next clock edge of that of write command. not written into the memory.
- For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock
- For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words
- For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip
- If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM.
- Refer to "3.3.2 Burst write operation"
Figure 15. Write interrupted by a read and DM timing
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. operation and a Precharge command to the same bank. the address path by switching clock domains from the data strobe clock domain to the input clock domain. i.e., the input clock domain. ends on the rising clock edge that strobes in the precharge command.
- For the earliest possible Precharge command following a Write burst without interrupting the burst, the
minimum time for write recovery is defined by tWR.
- When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask
Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. Figure 16. Write interrupted by a precharge and DM timing
- For a Write with autoprecharge command, a new Bank Activate command may be issued to the same
external Precharge command without interrupting the Write burst as described in 1 above.
- In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to
command followed by the earliest possible Precharge command which does not interrupt the burst.
- Refer to "3.3.2 Burst write operation"
ing a write burst operation. The burst ends after a delay equal to the CAS latency.
- The BST command may only be issued on the rising edge of the input clock, CK.
- BST is only a valid command during Read bursts.
- BST during a Write burst is undefined and shall not be used.
- BST applies to all burst lengths.
- BST is an undefined command during Read with autoprecharge and shall not be used.
Figure 17. Burst stop timing
corresponding data.(DM to data-mask latency is zero).
- When terminating a burst Read command, the BST command must be issued L BST (“BST Latency”) clock
- When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). Figure 18. DM masking timing
time(tRP) has been satisfied. Figure 19. Read with auto precharge timing Table 6. Operating description when new command asserted
charge begins after keeping tWR(min). Figure 20. Write with auto precharge timing *2 : DM : Refer to " 3.3.7 Write Interrupted by a Read & DM " in page 25. Table 7. Operating description when new command asserted
must be greater than or equal to the tRFC(min). high for longer than tXSR for locking of DLL. Figure 21. Auto refresh timing Figure 22. Self refresh timing
- Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after
- Exit self refresh to read command
the refresh period(Data retension time) of the device. Figure 23. Power down entry and exit timing
- OP Code : Operand Code. A 0 ~ A 11 & BA 0 ~ BA 1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.
- Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.
- BA 0 ~ BA 1 : Bank select addresses.
If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected.
- If A 10 /AP is "High" at row precharge, BA 0 and BA 1 are ignored and all banks are selected.
- During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst.
- Burst stop command is valid at every burst length.
- DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
- This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Table 8. Command truth table
- 34 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM 5. Functional Truth Table Current State CS RAS CAS WE Address Command Action PRECHARGE STANDBY L H H L X Burst Stop ILLEGAL*2 L H L X BA, CA, A 10 READ/WRITE ILLEGAL*2 L L H H BA, RA Active Bank Active, Latch RA L L H L BA, A 10 PRE/PREA ILLEGAL *4 L L L H X Refresh AUTO-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 ACTIVE STANDBY L H H L X Burst Stop NOP L H L H BA, CA, A 10 READ/READA Begin Read, Latch CA, Determine Auto-Precharge L H L L BA, CA, A 10 WRITE/WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A 10 PRE/PREA Precharge/Precharge All L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ L H H L X Burst Stop Terminate Burst L H L H BA, CA, A 10 READ/READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 L H L L BA, CA, A 10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A 10 PRE/PREA Terminate Burst, Precharge L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Table 9-1. Functional truth table
- 35 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Current State CS RAS CAS WE Address Command Action WRITE L H H L X Burst Stop ILLEGAL L H L H BA, CA, A 10 READ/READA Terminate Burst With DM=High, Latch CA, Begin Read, Deter- mine Auto-Precharge*3 L H L L BA, CA, A 10 WRITE/WRITEA Terminate Burst, Latch CA, Begin new Write, Determine Auto-Precharge*3 L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A 10 PRE/PREA Terminate Burst With DM=High, Precharge L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ with AUTO PRECHARGE *6 (READA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A 10 READ/READA *6 L H L L BA, CA, A 10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active *6 L L H L BA, A 10 PRE/PREA *6 L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE with AUTO RECHARGE *7 (WRITEA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A 10 READ/READA *7 L H L L BA, CA, A 10 WRITE/WRITEA *7 L L H H BA, RA Active *7 L L H L BA, A 10 PRE/PREA *7 L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Table 9-2. Functional truth table
- 36 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Current State CS RAS CAS WE Address Command Action PRECHARG- ING (DURING tRP) L H H L X Burst Stop ILLEGAL*2 L H L X BA, CA, A 10 READ/WRITE ILLEGAL*2 L L H H BA, RA Active ILLEGAL*2 L L H L BA, A 10 PRE/PREA NOP*4(Idle after tRP ) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING (FROM ROW ACTIVE TO tRCD) L H H L X Burst Stop ILLEGAL*2 L H L X BA, CA, A 10 READ/WRITE ILLEGAL*2 L L H H BA, RA Active ILLEGAL*2 L L H L BA, A 10 PRE/PREA ILLEGAL*2 L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE RECOVERING (DURING tWR OR tCDLR) L H H L X Burst Stop ILLEGAL*2 L H L H BA, CA, A 10 READ ILLEGAL*2 L H L L BA, CA, A 10 WRITE WRITE L L H H BA, RA Active ILLEGAL*2 L L H L BA, A 10 PRE/PREA ILLEGAL*2 L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Table 9-3. Functional truth table
- 37 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM Current State CS RAS CAS WE Address Command Action RE- FRESHING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A 10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A 10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MODE REGISTER SETTING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A 10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A 10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Table 9-4. Functional truth table
- 38 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM ABBREVIATIONS : H=High Level, L=Low level, X=Don ′t Care Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to "3.3.11 Read with Auto Precharge" in page 29 for detailed information. 7. Refer to "3.3.12 Write with Auto Precharge" in page 30 for detailed information. 8 . CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9. Power-Down and Self-Refresh can be entered only from All Bank Idle state. ILLEGAL = Device operation and/or data integrity are not guaranteed. Current State CKE n-1 CKE n CS RAS CAS WE Add Action SELF- REFRESHING *8 L H H X X X X Exit Self-Refresh L H L H H H X Exit Self-Refresh L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOPeration(Maintain Self-Refresh) POWER DOWN L H X X X X X Exit Power Down(Idle after tPDEX ) L L X X X X X NOPeration(Maintain Power Down) ALL BANKS IDLE *9 H H X X X X X Refer to Function True Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State=Power Down ANY STATE other than listed above H H X X X X X Refer to Function Truth Table Table 9-5. Functional truth table
- DC Operating Conditions & Specifications
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition.
- V ID is the magnitude of the difference between the input level on CK and the input level on CK .
Table 10. Absolute maximum ratings Table 11. DC operating condition
- 40 - REV. 1.0 November. 2. 2000 128Mb DDR SDRAM
7.2 DDR SDRAM SPEC Items and Test Conditions
Typical case: VDD = 2.5V, T = 25’C Worst case : VDD = 2.7V, T = 10’C Conditions Symbol Typical Worst Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle IDD0 - - Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition IDD1 - - Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM IDD2F - - Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM IDD2Q - - Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle IDD3N - - Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A IDD4R - - Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst IDD4W - - Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh IDD5 - - Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B IDD6 - - Orerating current - Four bank operation ; Four bank interleaving with BL=4 -Refer to the following page for detailed test condition IDD7 - -
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7.3 DDR SDRAM I DD spec table
(DDR266A) K4H280438B-TCB0 (DDR266B) K4H280438B-TCA0 (DDR200) Unit Notes typical worst typical worst typical worst IDD0 85 95 85 95 75 85 mA IDD1 125 140 125 140 120 130 mA IDD2P 21 25 21 25 18 22 mA IDD2F 40 45 40 45 35 40 mA IDD2Q 30 35 30 35 25 30 mA IDD3P 25 30 25 30 20 25 mA IDD3N 35 40 35 40 30 35 mA IDD4R 140 155 140 155 115 130 mA IDD4W 125 140 125 140 100 115 mA IDD5 185 200 185 200 175 190 mA IDD6 Normal 2 2 2 2 2 2 mA Low power 1 1 1 1 1 1 mA Optional IDD7 250 265 250 265 240 255 mA Symbol K4H280838BT-CA2 (DDR266A) K4H280838B-TCB0 (DDR266B) K4H280838B-TCA0 (DDR200) Unit Notes typical worst typical worst typical worst IDD0 90 95 90 95 80 85 mA IDD1 140 150 140 150 125 135 mA IDD2P 21 25 21 25 19 23 mA IDD2F 40 45 40 45 35 40 mA IDD2Q 30 35 30 35 27 32 mA IDD3P 25 30 25 30 20 25 mA IDD3N 40 45 40 45 30 35 mA IDD4R 150 165 150 165 125 140 mA IDD4W 135 150 135 150 105 120 mA IDD5 195 205 195 205 180 190 mA IDD6 Normal 2 2 2 2 2 2 mA Low power 1 1 1 1 1 1 mA Optional IDD7 260 280 260 280 250 275 mA
Table 12. 128Mb DDR SDRAM IDD SPEC Table
- Typical Case : Vdd = 2.5V, T=25’ C
- Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
- AC Operating Conditions & Timming Specification
Note 1. Vih(max) = 4.2V. The overshoot voltage duration is ≤ 3ns at VDD.
- Vil(min) = -1.5V. The undershoot voltage duration is ≤ 3ns at VSS.
- VID is the magnitude of the difference between the input level on CK and the input on CK .
- The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Table 13. AC operating conditions
- Typical Case : Vdd = 2.5V, T=25’ C
- Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
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8.2 AC Timming Parameters & Specifications
-TCA2 (DDR266A) K4H281638B -TCB0 (DDR266B) K4H281638B -TCA0 (DDR200) Unit Note Min Max Min Max Min Max Row cycle time tRC 65 65 70 ns Refresh row cycle time tRFC 75 75 80 ns Row active time tRAS 45 120K 45 120K 48 120K ns RAS to CAS delay tRCD 20 20 20 ns Row precharge time tRP 20 20 20 ns Row active to Row active delay tRRD 15 15 15 ns Write recovery time tWR 2 2 2 tCK Last data in to Read command tCDLR 1 1 1 tCK Col. address to Col. address delay tCCD 1 1 1 tCK Clock cycle time CL=2.0 tCK 7.5 15 10 15 10 15 ns CL=2.5 15 7.5 15 15 ns Data strobe edge to ouput data edge tDQSQ - +0.5 - +0.5 - +0.6 ns DQS-in setup time tWPRES 0 0 0 ns 3 DQS-in hold time tWPREH 0.25 0.25 0.25 tCK Address and Control Input setup time tIS 0.9 0.9 1.1 ns Address and Control Input hold time tIH 0.9 0.9 1.1 ns Mode register set cycle time tMRD 15 15 16 ns DQ & DM setup time to DQS tDS 0.5 0.5 0.6 ns DQ & DM hold time to DQS tDH 0.5 0.5 0.6 ns DQ & DM input pulse width tDIPW 1.75 1.75 2 ns Power down exit time tPDEX 10 10 10 ns Exit self refresh to write command tXSW 95 116 ns
Table 14. AC timing parameters and specifications
- Maximum burst refresh of 8
- tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
- The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
DQS could be High at this time, depending on tDQSS.
- The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
- The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC
- the value of tQCSWI max. is 1.5tcK from the first high going clock edge after the last low going data strobe
- A write command can be applied with tRCD satisfied after this command.
- AC Operating Test Conditions
- Input/Output Capacitance
Table 15. AC operating test conditions Table 16. Input/output capacitance Figure 24. Output Load Circuit (SSTL_2)
- IBIS: I/V Characteristics for Input and Output Buffers
Figure 25. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)
- The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a.
- The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the ou ter
bounding lines the of the V-I curve of Figure a.
- The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b .
- The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the oute r
bounding lines of the V-I curve of Figrue b.
- The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain t o source
- The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source v oltages
Table 17. Pull down and pull up current values
Figure 26. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)
11.2 Half strength driver
- The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain t o source
- The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source vo ltages
- The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a.
- The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the ou ter
bounding lines the of the V-I curve of Figure a.
- Thenominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b.
- The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the oute r
bounding lines of the V-I curve of Figrue b.
Table 18. Pull down and pull up current values
external data switch. QFC can be enabled or disabled through EMRS control . Figure 26. QFC timing on read operation
Figure 29. : QFC timing example for Interrupted writes operation