K4F641612E

K4F661612E SAMSUNG | Alldatasheet

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Technical content

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low pow er) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung ′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Fast Page Mode operation
• 2CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) packages
• +3.3V ±0.3V power supply
• Industrial Temperature operating ( -40~85 °C ) SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 4M x 16bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

W Vcc Vss DQ0 to DQ7 A0~A12 (A0~A11)*1 A0~A8 (A0~A9)*1 Memory Array 4,194,304 x 16 Cells FUNCTIONAL BLOCK DIAGRAM Note) *1 : 4K Refresh Sense Am ps & I/O Upper Data in Buffer Upper Data out Buffer Lower Data in Buffer DQ8 to DQ15 OE Row Decoder Column Decoder VBB Generator Refresh Timer Refresh Control Refresh Counter Row Address Buffer Col. Address Buffer

• Part Identification - K4F661612E-TI/P(3.3V, 8K Ref.) - K4F641612E-TI/P(3.3V, 4K Ref.)

FEATURES

• Refresh Cycles Part NO. Refresh cycle Refresh time Normal L-ver K4F661612E* 8K 64ms 128ms K4F641612E 4K
• Performance Range Speed tRAC tCAC tRC tPC -45 45ns 12ns 80ns 31ns -50 50ns 13ns 90ns 35ns -60 60ns 15ns 110ns 40ns
• Active Power Dissipation Speed 8K 4K -45 324 468 -50 288 432 -60 252 396 Unit : mW * Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature PIN CONFIGURATION (Top Views) VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C VCC VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 VSS Pin Name Pin function A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 15 Data In/Out VSS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+3.3V) N.C No Connection (400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product

• K4F661612E-T
• K4F641612E-T

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature ABSOLUTE MAXIMUM RATINGS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. Parameter Symbol Rating Units Voltage on any pin relative to V SS VIN, VOUT -0.5 to +4.6 V Voltage on VCC supply relative to V SS VCC -0.5 to +4.6 V Storage Temperature Tstg -55 to +150 °C Power Dissipation PD 1 W Short Circuit Output Current IOS Address 50 mA RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= -40 to 85 °C) *1 : Vcc+1.3V at pulse width ≤15ns which is measured at V CC *2 : -1.3 at pulse width ≤15ns which is measured at V SS Parameter Symbol Min Typ Max Units Supply Voltage VCC 3.0 3.3 3.6 V Ground VSS 0 0 0 V Input High Voltage VIH 2.0 - Vcc+0.3 *1 V Input Low Voltage VIL -0.3*2 - 0.8 V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0 ≤VIN≤VCC+0.3V, all other pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V ≤VOUT ≤VCC ) IO(L) -5 5 uA Output High Voltage Level(I OH=-2mA) VOH 2.4 - V Output Low Voltage Level(I OL=2mA) VOL - 0.4 V

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature *Note : ICC1 , ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 , ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In I CC4 , address can be changed maximum once within one fast page mode cycle time, tPC. DC AND OPERATING CHARACTERISTICS (Continued) ICC1 * : Operating Current ( RAS and UCAS, LCAS, Address cycling @ tRC =min.) ICC2 : Standby Current ( RAS=UCAS=LCAS=W=VIH) ICC3 * : RAS-only Refresh Current ( UCAS=LCAS=VIH, RAS, Address cycling @ tRC =min.) ICC4 * : Fast Page Mode Current ( RAS=VIL , UCAS or LCAS, Address cycling @ tPC=min.) ICC5 : Standby Current ( RAS=UCAS=LCAS=W=VCC -0.2V) ICC6 * : CAS-Before- RAS Refresh Current ( RAS and UCAS or LCAS cycling @tRC =min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(V IH)=VCC -0.2V, Input low voltage(V IL )=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V, W, OE=VIH, Address=Don ′t care, DQ=Open, T RC =31.25us ICCS : Self Refresh Current Symbol Power Speed Max Units K4F661612E K4F641612E ICC1 Don′t care -45 -50 -60 130 120 110 mA mA mA ICC2 Normal L Don′t care 1 mA mA ICC3 Don′t care -45 -50 -60 130 120 110 mA mA mA ICC4 Don′t care -45 -50 -60 mA mA mA ICC5 Normal L Don′t care 0.5 200 0.5 200 mA uA ICC6 Don′t care -45 -50 -60 130 120 110 130 120 110 mA mA mA ICC7 L Don′t care 350 350 uA ICCS L Don′t care 350 350 uA

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A12] CIN1 - 5 pF Input capacitance [ RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ15] CDQ - 7 pF Parameter Symbol -45 -50 -60 Units Note Min Max Min Max Min Max Random read or write cycle time tRC 80 90 110 ns Read-modify-write cycle time tRWC 115 133 153 ns Access time from RAS tRAC 45 50 60 ns 3,4,10 Access time from CAS tCAC 12 13 15 ns 3,4,5 Access time from column address tAA 23 25 30 ns 3,10 CAS to output in Low-Z tCLZ 0 0 0 ns 3 Output buffer turn-off delay tOFF 0 13 0 13 0 13 ns 6 Transition time (rise and fall) tT 1 50 1 50 1 50 ns 2 RAS precharge time tRP 25 30 40 ns RAS pulse width tRAS 45 10K 50 10K 60 10K ns RAS hold time tRSH 12 13 15 ns CAS hold time tCSH 45 50 60 ns CAS pulse width tCAS 12 10K 13 10K 15 10K ns RAS to CAS delay time tRCD 18 33 20 37 20 45 ns 4 RAS to column address delay time tRAD 13 22 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 8 10 10 ns Column address set-up time tASC 0 0 0 ns 13 Column address hold time tCAH 8 10 10 ns 13 Column address to RAS lead time tRAL 23 25 30 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 0 ns 8 Write command hold time tWCH 8 10 10 ns Write command pulse width tWP 8 10 10 ns Write command to RAS lead time tRWL 13 15 15 ns Write command to CAS lead time tCWL 12 13 15 ns 16 Data set-up time tDS 0 0 0 ns 9,19 Data hold time tDH 10 10 10 ns 9,19 AC CHARACTERISTICS (-40°C≤TA≤85°C, See note 2)

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature AC CHARACTERISTICS (Continued) Parameter Symbol -45 -50 -60 Units Note Min Max Min Max Min Max Refresh period (Normal) tREF 64 64 64 ms Refresh period (L-ver) tREF 128 128 128 ms Write command set-up time tWCS 0 0 0 ns 7 CAS to W delay time tCWD 32 36 38 ns 7,15 RAS to W delay time tRWD 67 73 83 ns 7 Column address to W delay time tAWD 43 48 53 ns 7 CAS precharge W delay time tCPWD 48 53 60 ns CAS set-up time ( CAS -before-RAS refresh) tCSR 5 5 5 ns 17 CAS hold time ( CAS -before-RAS refresh) tCHR 10 10 10 ns 18 RAS to CAS precharge time tRPC 5 5 5 ns Access time from CAS precharge tCPA 26 30 35 ns 3 Fast Page mode cycle time tPC 31 35 40 ns Fast Page mode read-modify-write cycle time tPRWC 70 76 85 ns CAS precharge time (Fast page cycle) tCP 9 10 10 ns 14 RAS pulse width (Fast page cycle) tRASP 45 200K 50 200 60 200 ns RAS hold time from CAS precharge tRHCP 28 30 35 ns OE access time tOEA 12 13 15 ns 3 OE to data delay tOED 12 13 13 ns Output buffer turn off delay time from OE tOEZ 0 13 0 13 0 13 ns 6 OE command hold time tOEH 12 13 15 ns Write command set-up time (Test mode in) tWTS 10 10 10 ns 11 Write command hold time (Test mode in) tWTH 15 15 15 ns 11 W to RAS precharge time (C-B-R refresh) tWRP 10 10 10 ns W to RAS hold time (C-B-R refresh) tWRH 10 10 10 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 20,21,22 RAS precharge time (C-B-R self refresh) tRPS 80 90 110 ns 20,21,22 CAS hold time (C-B-R self refresh) tCHS -50 -50 -50 ns 20,21,22

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature TEST MODE CYCLE Parameter Symbol -45 -50 -60 Units Note Min Max Min Max Min Max Random read or write cycle time tRC 85 95 115 ns Read-modify-write cycle time tRWC 120 138 160 ns Access time from RAS tRAC 50 55 65 ns 3,4,10,12 Access time from CAS tCAC 17 18 20 ns 3,4,5,12 Access time from column address tAA 28 30 35 ns 3,10,12 RAS pulse width tRAS 50 10K 55 10K 65 10K ns CAS pulse width tCAS 17 10K 18 10K 20 10K ns RAS hold time tRSH 17 18 20 ns CAS hold time tCSH 50 55 65 ns Column Address to RAS lead time tRAL 28 30 35 ns CAS to W delay time tCWD 37 41 43 ns 7 RAS to W delay time tRWD 72 78 88 ns 7 Column Address to W delay time tAWD 48 53 58 ns 7 Fast Page mode cycle time tPC 36 40 45 ns Fast Page mode read-modify-write cycle time tPRWC 75 81 90 ns RAS pulse width (Fast page cycle) tRASP 50 200K 55 200K 65 200K ns Access time from CAS precharge tCPA 31 35 40 ns 3 OE access time tOEA 17 18 20 ns OE to data delay tOED 17 18 18 ns OE command hold time tOEH 17 18 20 ns ( Note 11 )

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature NOTES An initial pause of 200 §Á is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved. VIH(min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and V IL (max) and are assumed to be 5ns for all inputs. Measured with a load equivalent to 1 TTL load and 100pF. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . Assumes that tRCD ≥tRCD (max). tOFF(min)and tOEZ (max) define the time at which the output achieves the open circuit condition and are not referenced V oh or Vol. tWCS , tRWD , tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac- teristics only. If tWCS ≥tWCS (min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min) and tAWD ≥tAWD (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in read-modify- write cycles. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. These specifications are applied in the test mode. In test mode read cycle, the value of tRAC , tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 10. 11. 12. K4F64(6)1612E Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H X X X X Hi-Z Hi-Z Standby L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z -

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tASC , tCAH are referenced to the earlier CAS falling edge. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. tCWL is specified from W falling edge to the earlier CAS rising edge. tCSR is referenced to earlier CAS falling before RAS transition low. tCHR is referenced to the later CAS rising high after RAS transition low. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. tCSR tCHR RAS LCAS UCAS tDS tDH LCAS UCAS DQ0 ~ DQ15 Din 21. 20. 19. 15. 14. 13. 18. 17. 16. 22.

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - VOH - VOL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRALtASR tRAH tASC tCAH tCRP tAA tOEA tCAC tCLZ tRAC OPEN tOFF tRCH Don′t care Undefined LCAS VIH - VIL - tCRP tCSH tRSHtRCD tCAS tRAD tCRP tRRH VOH - VOL - DQ8 ~ DQ15 tCAC tCLZ tRAC OPEN DATA-OUT DATA-OUT tOFF tOEZ tOEZ tRCS WORD READ CYCLE

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tCRP NOTE : D IN = OPEN LOWER BYTE READ CYCLE RAS VIH - VIL - LCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - VOH - VOL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP tAA tOEA tCAC tCLZ tRAC OPEN DATA-OUT tOEZ tOFF tRCH Don′t care Undefined tRPC UCAS VIH - VIL - OPEN VOH - VOL - DQ8 ~ DQ15 tRCS tRRH

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature NOTE : D IN = OPEN UPPER BYTE READ CYCLE RAS VIH - VIL - LCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - VOH - VOL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP tAA tOEA tCAC tCLZ tRAC OPEN DATA-OUT tOEZ tOFF tRRH tRCH Don′t care Undefined UCAS VIH - VIL - OPEN VOH - VOL - DQ8 ~ DQ15 tCRP tRPC tRCS

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don′t care WORD WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS VIH - VIL - tWCS VIH - VIL - DQ0 ~ DQ7 tDS VIH - VIL - DQ8 ~ DQ15 tCRP tCSH tRSHtRCD tCAS tCRP tWCH tWP tDH DATA-IN tDS tDH DATA-IN

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tCRP RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tRP tRAL tRAD tASR tRAH tASC tCAH Don′t care LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS VIH - VIL - tWCS VIH - VIL - DQ0 ~ DQ7 tDS VIH - VIL - DQ8 ~ DQ15 tCRP tCSH tRSHtRCD tCAS tWCH tWP tDH DATA-IN tCRP tRPC

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don′t care UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS VIH - VIL - tWCS VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tWCH tWP tDS tDH DATA-IN tCRP tRPC

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCRP Don′t care WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS VIH - VIL - VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tCRPtRSHtRCD tCAS tCRP tRWL tWP tCWL tDH tDH DATA-IN COLUMN ADDRESS tOEHtOED tDS tDS DATA-IN tCSH tCAH

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tRP tRAL tRAD tASR tRAH tASC tCAH Don′t care LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS VIH - VIL - tRWL VIH - VIL - DQ0 ~ DQ7 tDS VIH - VIL - DQ8 ~ DQ15 tCRP tCSH tRSHtRCD tCAS tCRP tWP tCWL tDH DATA-IN tCRP tRPC tOEH tOED

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don′t care UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS VIH - VIL - VIH - VIL - VIH - VIL - tCRP tRWL tWP tCWL tDS tDH DATA-IN tOEH tOED DQ0 ~ DQ7 DQ8 ~ DQ15 tRPC

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tRWL RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP Don′t care WORD READ - MODIFY - WRITE CYCLE Undefined LCAS VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 VI/OH - VI/OL - DQ8 ~ DQ15 tWP tCWL tDS tDH tRSHtRCD tCAS tCRP tAWD tCWD tOEA tRWD tOED tOEZtRAC tAA tOEZtRAC tAA tDS tOED tDH VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tCAC tCLZ tCAC tCLZ

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tRWL RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRAS tRWC tRP tCSH tRAD tASR tRAH tASC tCAH tCRP Don′t care LOWER-BYTE READ - MODIFY - WRITE CYCLE Undefined LCAS VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 VI/OH - VI/OL - DQ8 ~ DQ15 tWP tCWL tDS tDH tRSHtRCD tCAS tCRP tAWD tCWD tOEA tRWD tOED tOEZtRAC tAA VALID DATA-OUT VALID DATA-IN tRPC tCAC tCLZ OPEN

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tCRP tRWL RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP Don′t care UPPER-BYTE READ - MODIFY - WRITE CYCLE Undefined LCAS VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 VI/OH - VI/OL - DQ8 ~ DQ15 tWP tCWL tAWD tCWD tOEA tRWD tOEZtRAC tAA tDS tOED tDH VALID DATA-OUT VALID DATA-IN tRPC tCAC tCLZ OPEN

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tASR tCRP Don′t care FAST PAGE MODE WORD READ CYCLE Undefined LCAS VIH - VIL - VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 tOEZ tOFF COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tCP tRPC tPC tPC tPC tRHCPtCSH tRCD tCRP tCAS tCAS tCAS tCAS tCP tCP tRPC tRAD tRAH tASC tCAH tCAH tCAH tASC tCAH tRCS tRCS tOEA tAA tRCS tRCH tRCH tRCS tRCH tRCH tRRH tASC COLUMN ADDRESS COLUMN ADDR VALID DATA-OUT tOEZ tOFF tOEA tCPA tAA tCAC tOEA tCPA tAA tCAC tOEA tCPA tAA tCAC VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT tOEZ tOFF tOEZ tOFF tOEZ tOFF VALID DATA-OUT tOEZ tOFF VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT tOEZ tOFF tOEZ tOFF tCLZ tRAC tCAC tCAC tCLZ tRAC tASC tCP tRAL

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tCRP tCRP RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tASR Don′t care FAST PAGE MODE LOWER BYTE READ CYCLE Undefined LCAS VIH - VIL - VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 tOEZ tOFF COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tRPC tPC tPC tPC tRHCP tCSH tRAD tRAH tASC tCAH tASC tCAH tCAH tASC tCAH tRCS tRCS tOEA tAA tRCS tRCH tRCH tRCS tRCH tRCH tRRH tASC COLUMN ADDRESS COLUMN ADDR VALID DATA-OUT tOEZ tOFF tOEA tCPA tAA tCAC tOEA tCPA tAA tCAC tOEA tCPA tAA tCAC VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT tOEZ tOFF tOEZ tOFF tCLZ tRAC tCAC tRPC OPEN tRAL tCP

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tCP RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tASR tCRP Don′t care FAST PAGE MODE UPPER BYTE READ CYCLE Undefined LCAS VIH - VIL - VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tRPC tPC tPC tPC tRHCPtCSH tCRP tRPC tRAD tRAH tASC tCAH tASC tCAH tCAH tCAH tRCS tRCS tOEA tAA tRCS tRCH tRCH tRCS tRCH tRCH tRRH tASC COLUMN ADDRESS COLUMN ADDR tOEA tCPA tOEA tCPA tOEA tCPA tOEZ tOFF VALID DATA-OUT tOEZ tOFF VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT tOEZ tOFF tOEZ tOFFtCAC tCLZ tRAC OPEN tAA tCAC tAA tCAC tAA tCAC tRAL tASC

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tASC RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tASR tCRP Don′t care FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) Undefined LCAS VIH - VIL - VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tCRP tPC tPC tRHCP tRAD tRAH tCAH tCAH tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tCAS tCP tCAS tCP tCAS tRSH tRCD tCRP tPC tPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH VALID DATA-IN VALID DATA-IN VALID DATA-IN tDH tDH tDHtDStDStDS NOTE : D OUT = OPEN tRAL

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tASR tCRP Don′t care FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) Undefined LCAS VIH - VIL - VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tRPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tRCD tCRP tPC tPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH NOTE : D OUT = OPEN tRAL

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR. tRASP tRP tASR tCRP Don′t care FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) Undefined LCAS VIH - VIL - VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tRPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tRCD tCRP tPC tPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH NOTE : D OUT = OPEN tRAL

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don′t care FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE Undefined tRCD tCP tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAS tCAS tCRP tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tASC tCLZ tOEA tCAC tAA tDH tOED tRWL LCAS VIH - VIL - tRCD tCP tCAS tCAS tCRP tCRP tCRP VI/OH - VI/OL - DQ8 ~ DQ15 VALID DATA-OUT tDHtAA tRAC tCLZ tCAC VALID DATA-IN VALID DATA-OUT VALID DATA-IN tCLZ tCAC tAA tDH tOEZ tOED tDS tDS tDS tOEZ tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tPRWC tRSH tWP tRCS tRAH tOED

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don′t care FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE Undefined tRAD tCAH tWP tDH COL. ADDR COL. ADDR tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tASC tCLZ tOEA tCAC tAA tDH tOED tRWL LCAS VIH - VIL - tRCD tCP tCAS tCAS tCRP tCRP tCRP VI/OH - VI/OL - DQ8 ~ DQ15 tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tRPC tRSHtPRWC OPEN tRCS tRAH

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature RAS VIH - VIL - VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don′t care FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE Undefined tRAD tCAH tWP tDH COL. ADDR COL. ADDR tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tASC tCLZ tOEA tCAC tAA tDH tOED tRWL VIH - VIL - tRCD tCP tCAS tCAS tCRP tCRP tCRP VI/OH - VI/OL - DQ8 ~ DQ15 tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tRPC tRSHtPRWC OPEN UCAS LCAS tRCS tRAH

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tCSR OPEN RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - ROW ADDR tRC tRP tASR tCRP RAS - ONLY REFRESH CYCLE LCAS VIH - VIL - tRAS tRAH NOTE : W, OE , DIN = Don′t care DOUT = OPEN tRPC tCRP CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don′t care RAS VIH - VIL - UCAS VIH - VIL - tRC tRP LCAS VIH - VIL - tRAS tRPC tCP tCRP tCHR tCP tCSR tCHR tOFF OPEN VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 tWRP tWRH W VIH - VIL - Don′t care tRP Undefined

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tOEZ DATA-IN DATA-OUT tRP RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don′t care HIDDEN REFRESH CYCLE ( READ ) Undefined LCAS VIH - VIL - VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 tRSHtRCDtCRP tWRH COLUMN ADDRESS tOEA tRAS tRC tCHR tCAH tRCS tAA tRAC tCLZ tCAC DATA-OUT tOFF OPEN OPEN tRP tRAL

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tWCS tRP RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don′t care HIDDEN REFRESH CYCLE ( WRITE ) Undefined LCAS VIH - VIL - VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tRSHtRCDtCRP tWRH COLUMN ADDRESS tRAS tRC tCHR tCAH tWRP tDS NOTE : D OUT = OPEN tWP tWCH DATA-IN tDH tDS DATA-IN tDH tRP tRAL

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature tCSR OPEN CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don′t care RAS VIH - VIL - UCAS VIH - VIL - tRPS LCAS VIH - VIL - tRASS tRPC tCP tRPC tCSR tOFF OPEN VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 tWRP tWRH W VIH - VIL - tCHS tCP tCHS TEST MODE IN CYCLE NOTE : OE , A = Don′t care RAS VIH - VIL - UCAS VIH - VIL - tRP LCAS VIH - VIL - tRC tRPC tCP tCRP tCSR OPEN VOH - VOL - DQ0 ~ DQ15 tCHR tCP tCSR tCHR tRP tRAS tRP Don′t care Undefined tWTS tWTH W VIH - VIL - tOFF

CMOS DRAMK4F661612E, K4F641612E Industrial Temperature

50 TSOP(II) 400mil Units : Inches (millimeters)

0.047 (1.20) MIN 0.002 (0.05) 0.018 (0.45) 0.010 (0.25) 0.821 (20.85) 0.829 (21.05) 0.841 (21.35) MAX 0.010 (0.25) 0.004 (0.10) 0.400 (10.16) 0.471 (11.96) 0.455 (11.56) 0~8 0.030 (0.75) 0.018 (0.45) TYP 0.010 (0.25) O PACKAGE DIMENSION