K4F170412D

K4F170411D SAMSUNG | Alldatasheet

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K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D This is a family of 4,194,304 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS - before- RAS refresh, RAS -only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx4 Fast Page Mode DRAM family is fabricated using Samsung ′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as main memory for high level computer, microcomputer and personal computer.

• Part Identification - K4F170411D-B(F) (5V, 4K Ref.) - K4F160411D-B(F) (5V, 2K Ref.) - K4F170412D-B(F) (3.3V, 4K Ref.) - K4F160412D-B(F) (3.3V, 2K Ref.)
• Fast Page Mode operation
• CAS -before- RAS refresh capability
• RAS -only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V ±10% power supply (5V product)
• Single +3.3V ±0.3V power supply (3.3V product) Control Clocks RAS CAS W Vcc Vss DQ0 to DQ3 A0-A11 (A0 - A10) *1 A0 - A9 (A0 - A10) *1 Memory Array 4,194,304 x 4 Cells SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 4M x 4Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM• Refresh Cycles Part NO. V CC Refresh cycle Refresh period Normal L-ver K4F170411D 5V 4K 64ms 128msK4F170412D 3.3V K4F160411D 5V 2K 32ms K4F160412D 3.3V

• Performance Range Speed tRAC tCAC tRC tPC Remark -50 50ns 13ns 90ns 35ns 5V/3.3V -60 60ns 15ns 110ns 40ns 5V/3.3V
• Active Power Dissipation Speed 3.3V 5V 4K 2K 4K 2K -50 324 396 495 605 -60 288 360 440 550 Unit : mW S e n s e A m p s & I/O Data out Buffer Data in Buffer OE Note) *1 : 2K Refresh Col. Address Buffer Row Address Buffer Refresh Counter Refresh Control Refresh Timer Column Decoder Row Decoder VBB Generator

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D V CC DQ0 DQ1 W RAS *A11(N.C) A10 V CC V SS DQ3 DQ2 CAS OE V SS PIN CONFIGURATION (Top Views) Pin Name Pin Function A0 - A11 Address Inputs (4K Product) A0 - A10 Address Inputs (2K Product) DQ0 - 3 Data In/Out V SS Ground RAS Row Address Strobe CAS Column Address Strobe W Read/Write Input OE Data Output Enable V CC Power(+5V) Power(+3.3V) N.C No Connection (2K Ref. product) V CC DQ0 DQ1 W RAS *A11(N.C) A10 V CC V SS DQ3 DQ2 CAS OE V SS *A11 is N.C for K4F160411(2)D(5V/3.3V, 2K Ref. product) B : 300mil 26(24) SOJ F : 300mil 26(24) TSOP II

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D ABSOLUTE MAXIMUM RATINGS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. Parameter Symbol Rating Units 3.3V 5V Voltage on any pin relative to V SS V IN, V OUT -0.5 to +4.6 -1.0 to +7.0 V Voltage on V CC supply relative to V SS V CC -0.5 to +4.6 -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 -55 to +150 °C Power Dissipation P D 1 1 W Short Circuit Output Current IOS Address 50 50 mA RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A = 0 to 70 °C) *1 : V CC +1.3V/15ns(3.3V), V CC +2.0V/20ns(5V), Pulse width is measured at V CC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V SS Parameter Symbol 3.3V 5V Units Min Typ Max Min Typ Max Ground V SS 0 0 0 0 0 0 V Input High Voltage V IH 2.0 - V CC +0.3 *1 2.4 - V CC +1.0 *1 V Input Low Voltage V IL -0.3 *2 - 0.8 -1.0 *2 - 0.8 V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Max Parameter Symbol Min Max Units 3.3V Input Leakage Current (Any input 0 ≤V IN ≤V IN +0.3V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V ≤V OUT ≤V CC ) IO(L) -5 5 uA Output High Voltage Level(I OH =-2mA) V OH 2.4 - V Output Low Voltage Level(I OL =2mA) V OL - 0.4 V Input Leakage Current (Any input 0 ≤V IN ≤V IN +0.5V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V ≤V OUT ≤V CC ) IO(L) -5 5 uA Output High Voltage Level(I OH =-5mA) V OH 2.4 - V Output Low Voltage Level(I OL =4.2mA) V OL - 0.4 V

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D *Note : ICC1 , I CC3 , I CC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 , I CC3 and I CC6 address can be changed maximum once while RAS =V IL . In I CC4 , address can be changed maximum once within one fast page mode cycle time, t PC . DC AND OPERATING CHARACTERISTICS (Continued) ICC1 * : Operating Current ( RAS and CAS , Address cycling @t RC =min.) ICC2 : Standby Current ( RAS = CAS = W =V IH ) ICC3 * : RAS -only Refresh Current ( CAS =V IH , RAS , Address cycling @t RC =min.) ICC4 * : Fast Page Mode Current ( RAS =V IL , CAS , Address cycling @t PC =min.) ICC5 : Standby Current ( RAS = CAS = W =V CC -0.2V) ICC6 * : CAS -Before- RAS Refresh Current ( RAS and CAS cycling @t RC =min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(V IH )=V CC -0.2V, Input low voltage(V IL )=0.2V, CAS =0.2V, DQ=Don ′t care, T RC =31.25us(4K/L-ver), 62.5us(2K/L-ver), T RAS =T RAS min~300ns ICCS : Self Refresh Current RAS = CAS =0.2V, W = OE =A0 ~ A11=V CC -0.2V or 0.2V, DQ0 ~ DQ3=V CC -0.2V, 0.2V or Open Symbol Power Speed Max Units K4F170412D K4F160412D K4F170411D K4F160411D ICC1 Don ′t care -50 -60 110 100 110 100 mA mA ICC2 Normal L Don ′t care 1 mA mA ICC3 Don ′t care -50 -60 110 100 110 100 mA mA ICC4 Don ′t care -50 -60 mA mA ICC5 Normal L Don ′t care 0.5 200 0.5 200 250 250 mA uA ICC6 Don ′t care -50 -60 110 100 110 100 mA mA ICC7 L Don ′t care 250 250 300 300 uA ICCS L Don ′t care 200 200 250 250 uA

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D CAPACITANCE (T A =25 °C, V CC =5V or 3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A11] C IN1 - 5 pF Input capacitance [ RAS , CAS , W , OE ] C IN2 - 7 pF Output capacitance [DQ0 - DQ3] C DQ - 7 pF Parameter Symbol -50 -60 Units Notes Min Max Min Max Random read or write cycle time tRC 90 110 ns Read-modify-write cycle time tRWC 133 155 ns Access time from RAS tRAC 50 60 ns 3,4,10 Access time from CAS tCAC 13 15 ns 3,4,5 Access time from column address tAA 25 30 ns 3,10 CAS to output in Low-Z tCLZ 0 0 ns 3 Output buffer turn-off delay tOFF 0 13 0 15 ns 6 Transition time (rise and fall) tT 3 50 3 50 ns 2 RAS precharge time tRP 30 40 ns RAS pulse width tRAS 50 10K 60 10K ns RAS hold time tRSH 13 15 ns CAS hold time tCSH 50 60 ns CAS pulse width tCAS 13 10K 15 10K ns RAS to CAS delay time tRCD 20 37 20 45 ns 4 RAS to column address delay time tRAD 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns Column address hold time tCAH 10 10 ns Column address to RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold time referenced to CAS tRCH 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 ns 8 Write command hold time tWCH 10 10 ns Write command pulse width tWP 10 10 ns Write command to RAS lead time tRWL 13 15 ns Write command to CAS lead time tCWL 13 15 ns AC CHARACTERISTICS (0 °C ≤T A ≤70 °C, See note 1,2)

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D AC CHARACTERISTICS (Continued) Parameter Symbol -50 -60 Units Note Min Max Min Max Data set-up time tDS 0 0 ns 9 Data hold time tDH 10 10 ns 9 Refresh period (2K, Normal) tREF 32 32 ms Refresh period (4K, Normal) tREF 64 64 ms Refresh period (L-ver) tREF 128 128 ms Write command set-up time tWCS 0 0 ns 7 CAS to W delay time tCWD 36 40 ns 7 RAS to W delay time tRWD 73 85 ns 7 Column address to W delay time tAWD 48 55 ns 7 CAS precharge to W delay time tCPWD 53 60 ns CAS set-up time ( CAS -before- RAS refresh) tCSR 5 5 ns CAS hold time ( CAS -before- RAS refresh) tCHR 10 10 ns RAS to CAS precharge time tRPC 5 5 ns Access time from CAS precharge tCPA 30 35 ns 3 Fast Page cycle time tPC 35 40 ns Fast Page read-modify-write cycle time tPRWC 76 85 ns CAS precharge time (Fast Page cycle) tCP 10 10 ns RAS pulse width (Fast Page cycle) tRASP 50 200K 60 200K ns RAS hold time from CAS precharge tRHCP 30 35 ns OE access time tOEA 13 15 ns OE to data delay tOED 13 15 ns Output buffer turn off delay time from OE tOEZ 0 13 0 15 ns 6 OE command hold time tOEH 13 15 ns Write command set-up time (Test mode in) tWTS 10 10 ns 11 Write command hold time (Test mode in) tWTH 10 10 ns 11 W to RAS precharge time( C -B- R refresh) tWRP 10 10 ns W to RAS hold time( C -B- R refresh) tWRH 10 10 ns RAS pulse width ( C -B- R self refresh) tRASS 100 100 us 13,14,15 RAS precharge time ( C -B- R self refresh) tRPS 90 110 ns 13,14,15 CAS hold time ( C -B- R self refresh) tCHS -50 -50 ns 13,14,15

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D TEST MODE CYCLE Parameter Symbol -50 -60 Units Notes Min Max Min Max Random read or write cycle time tRC 95 115 ns Read-modify-write cycle time tRWC 138 160 ns Access time from RAS tRAC 55 65 ns 3,4,10,12 Access time from CAS tCAC 18 20 ns 3,4,5,12 Access time from column address tAA 30 35 ns 3,10,12 RAS pulse width tRAS 55 10K 65 10K ns CAS pulse width tCAS 18 10K 20 10K ns RAS hold time tRSH 18 20 ns CAS hold time tCSH 55 65 ns Column address to RAS lead time tRAL 30 35 ns CAS to W delay time tCWD 41 45 ns 7 RAS to W delay time tRWD 78 90 ns 7 Column address to W delay time tAWD 53 60 ns 7 CAS precharge to W delay time tCPWD 58 65 ns Fast Page cycle time tPC 40 45 ns Fast Page read-modify-write cycle time tPRWC 81 90 ns RAS pulse width (Fast Page cycle) tRASP 55 200K 65 200K ns Access time from CAS precharge tCPA 35 40 ns 3 OE access time tOEA 18 20 ns OE to data delay tOED 18 20 ns OE command hold time tOEH 18 20 ns ( Note 11 )

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D NOTES An initial pause of 200us is required after power-up followed by any 8 RAS -only refresh or CAS -before- RAS refresh cycles before proper device operation is achieved. V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH (min) and V IL (max) and are assumed to be 5ns for all inputs. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . Assumes that tRCD ≥tRCD (max). tOFF (min)and tOEZ (max) define the time at which the output achieves the open circuit condition and are not referenced V oh or V ol . tWCS , tRWD , tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical charac- teristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the dura- tion of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min) and tAWD ≥tAWD (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA . These specifications are applied in the test mode. In test mode read cycle, the value of tRAC , tAA , tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP . For RAS -only refresh and burst CAS -before- RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe- cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification. For distributed CAS -before- RAS with 15.6us interval CAS -before- RAS refresh should be executed with in 15.6us immedi- ately before and after self refresh in order to meet refresh specification. 10. 11. 12. 13. 14. 15.

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D tCRP RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ3(7) READ CYCLE COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tAA tOEA tCAC tCLZ tRAC OPEN DATA-OUT tOEZ tRRH tRCH Don ′t care Undefined tRCS tOFF

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D tWCS WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V IH - V IL - DQ0 ~ DQ3(7) COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP tWP tDS tDH tWCH tCWL tRWL Don ′t care DATA-IN Undefined

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D tOED RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V IH - V IL - DQ0 ~ DQ3(7) COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP DATA-IN tWP Don ′t care WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN tCWL tRWL tDS tDH tOEH Undefined

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ3(7) ROW ADDR tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP VALID tWP Don ′t care READ - MODIFY - WRTIE CYCLE tRWL tCWL tOEZ tOEA tOED tAWD tCWD tRWD DATA-OUT Undefined VALID DATA-IN tRAC tAA tCAC tCLZ tDS tDH COLUMN ADDRESS

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D tRCH tOEZtCLZ RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ3(7) COLUMN ADDRESS ROW ADDR tRHCP tRASP tCAS tASC tRAD tASR tRAH tASC tCAH tCRP VALID Don ′t care FAST PAGE READ CYCLE tOEZ tRRH DATA-OUT Undefined VALID DATA-OUT COLUMN ADDRESS COLUMN ADDRESS tRSH tCAS tRCD tPC tCSH tCAH tASC tCAH tRCH tRCS tRCStRCS tOEA tCAC tOEA tCAC tOEA tCAC VALID DATA-OUT tCLZ tOFF tAA tOFF tAA tCLZ tOFF tOEZ tRAC tAA tCP tCAS tRP tCP tRAL

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D tASCtCAH RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V IH - V IL - DQ0 ~ DQ3(7) COLUMN ADDRESS ROW ADDR tRHCP tRASP tCAS tRAD tASR tRAH tASC tCRP VALID Don ′t care FAST PAGE WRITE CYCLE ( EARLY WRITE ) DATA-IN Undefined VALID DATA-IN tDS NOTE : D OUT = OPEN COLUMN ADDRESS COLUMN ADDRESS tRSH tCAS tRCD tPC tCSH tCAH tCAH tWCS tWCH tWCS VALID DATA-IN tWP tCWL tWP tWCH tWP tWCS tWCH tCWL tRWL tCWL tDH tDS tDH tDS tDH tRP tCPtCP tCAS tPC tRAL tASC

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D tCAC tASCtASC RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ3(7) ROW ADDR tCSH tRASP tASR VALID Don ′t care FAST PAGE READ - MODIFY - WRITE CYCLE DATA-OUT Undefined tRCD tCP tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAS tCAS tCRP tCAH tRAL tPRWC tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED VALID DATA-IN VALID DATA-OUT VALID DATA-IN tCLZ tDS tOEA tAA tDH tDS tOEZ tOED tRWL tRP tRSH tRAH

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - ROW ADDR tRAS tRC tRP tASR tRAH tCRP Don ′t care RAS - ONLY REFRESH CYCLE Undefined NOTE : W , OE , D IN = Don ′t care D OUT = OPEN tRPC tCRP CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - CAS V IH - V IL - tRAS tRC tRP tWRP tRPC tRP tCP tCHR tCSR W V IH - V IL - tWRH tOFF tRPC V OH - V OL - DQ0 ~ DQ3(7) OPEN

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D tWRH tOFF RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ3(7) HIDDEN REFRESH CYCLE ( READ ) COLUMN ADDRESS ROW ADDRESS tRAS tRC tCHRtRCD tRAD tASR tRAH tASC tCAH tCRP tRCS tAA tOEA tCAC tCLZ tRAC OPEN Don ′t care tRSH tOEZ Undefined tRC DATA-OUT tRP tRPtRAS tRAL

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V IH - V IL - DQ0 ~ DQ3(7) HIDDEN REFRESH CYCLE ( WRITE ) COLUMN ADDRESS ROW ADDRESS tRAS tRC tCHRtRCD tRAD tASR tRAH tASC tCAH tCRP Don ′t care tRSH DATA-IN tWRP tWRH Undefined tRC NOTE : D OUT = OPEN tWCH tWP tDH tRPtRP tRAS tDS tWCS tRAL

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D Don ′t care Undefined CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - CAS V IH - V IL - tRASS tRPS tRPC tWRP tCHS tRP tCP tCSR W V IH - V IL - tWRH tOFF tRPC OPEN V OH - V OL - DQ0 ~ DQ3(7) TEST MODE IN CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - CAS V IH - V IL - tRAS tRC tRP tRPC tWTS tRPC tRP tCP tCHR tCSR W V IH - V IL - tWTH tOFF OPENV OH - V OL - DQ0 ~ DQ3(7)

K4F170411D, K4F160411D CMOS DRAMK4F170412D, K4F160412D 0 .3 0 0 ( 7 .6 2 ) 0 .3 3 0 ( 8 .3 9 ) 0 .3 4 0 ( 8 .6 3 ) 0.680 (17.28) 0.670 (17.03) MAX 0.691 (17.55) M A X 0 .1 4 8 ( 3 .7 6 ) 0.0375 (0.95) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 .2 6 0 ( 6 .6 1 ) 0 .2 8 0 ( 7 .1 1 ) MIN #26(24) 0.050 (1.27) 26(24) SOJ 300mil Units : Inches (millimeters) PACKAGE DIMENSION 26(24) TSOP(II) 300mil MAX 0.047 (1.20) MIN 0.002 (0.05) 0.020 (0.50) 0.012 (0.30) 0.671 (17.04) 0.679 (17.24) 0.691 (17.54) MAX 0.010 (0.25) 0.004 (0.10) 0 .3 0 0 ( 7 .6 2 ) 0 . 3 7 1 ( 9 .4 2 ) 0 . 3 5 5 ( 9 .0 2 ) Units : Inches (millimeters) 0~8 0.030 (0.75) 0.018 (0.45) TYP 0.010 (0.25) O