K4E660812B

K4E660812B SAMSUNG | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 21

Technical content

CMOS DRAMK4E660812B, K4E640812B This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption( Nor- mal or Low power) are optional features of this family. All of this family have CAS -before- RAS refresh, RAS -only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricate d using Samsung ′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Extended Data Out Mode operation
• CAS -before- RAS refresh capability
• RAS -only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V ±0.3V power supply Control Clocks RAS CAS W Vcc Vss A0~A12 (A0~A11)*1 A0~A9 (A0~A10)*1 Memory Array 8,388,608 x 8 Cells SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 8M x 8bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

Note) *1 : 4K Refresh S e n s e A m p s & I/ O DQ0 to DQ7 Data out Buffer Data in Buffer Row Decoder Column Decoder VBB Generator Refresh Timer Refresh Control Refresh Counter Row Address Buffer Col. Address Buffer OE

• Part Identification - K4E660812B-JC/L(3.3V, 8K Ref., SOJ) - K4E640812B-JC/L(3.3V, 4K Ref., SOJ) - K4E660812B-TC/L(3.3V, 8K Ref., TSOP) - K4E640812B-TC/L(3.3V, 4K Ref., TSOP)

FEATURES

• Refresh Cycles Part NO. Refresh cycle Refresh time Normal L-ver K4E660812B* 8K 64ms 128ms K4E640812B 4K Unit : mW * Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS -before- RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
• Active Power Dissipation Speed 8K 4K -45 360 468 -50 324 432 -60 288 396 ¡Ü Performance Range Speed tRAC tCAC tRC tHPC -45 45ns 12ns 74ns 17ns -50 50ns 13ns 84ns 20ns -60 60ns 15ns 104ns 25ns

CMOS DRAMK4E660812B, K4E640812B V CC DQ0 DQ1 DQ2 DQ3 N.C V CC W RAS V CC V SS DQ7 DQ6 DQ5 DQ4 V SS CAS OE A12(N.C)* A11 A10 V SS PIN CONFIGURATION (Top Views) * (N.C) : N.C for 4K Refresh product Pin Name Pin Function A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 7 Data In/Out V SS Ground RAS Row Address Strobe CAS Column Address Strobe W Read/Write Input OE Data Output Enable V CC Power(+3.3V) N.C No Connection V CC DQ0 DQ1 DQ2 DQ3 N.C V CC W RAS V CC V SS DQ7 DQ6 DQ5 DQ4 V SS CAS OE A12(N.C)* A11 A10 V SS ¡Û ¡Û (T : 400mil TSOP(II))(J : 400mil SOJ)

• K4E660812B-J
• K4E640812B-J
• K4E660812B-T
• K4E640812B-T

CMOS DRAMK4E660812B, K4E640812B ABSOLUTE MAXIMUM RATINGS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. Parameter Symbol Rating Units Voltage on any pin relative to V SS V IN, V OUT -0.5 to +6.5 V Voltage on V CC supply relative to V SS V CC -0.5 to +4.6 V Storage Temperature Tstg -55 to +150 °C Power Dissipation P D 1 W Short Circuit Output Current IOS Address 50 mA RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A = 0 to 70 °C) *1 : 6.5V at pulse width ≤15ns which is measured at V CC *2 : -1.3 at pulse width ≤15ns which is measured at V SS Parameter Symbol Min Typ Max Units Supply Voltage V CC 3.0 3.3 3.6 V Ground V SS 0 0 0 V Input High Voltage V IH 2.0 - +5.5 *1 V Input Low Voltage V IL -0.3 *2 - 0.8 V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0 ≤V IN ≤V CC +0.3V, all other pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V ≤V OUT ≤V CC ) I O(L) -5 5 uA Output High Voltage Level(IOH=-2mA) V OH 2.4 - V Output Low Voltage Level(IOL=2mA) V OL - 0.4 V

CMOS DRAMK4E660812B, K4E640812B *Note : ICC1 , I CC3 , I CC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 , I CC3 and I CC6, address can be changed maximum once while RAS =V IL . In I CC4 , address can be changed maximum once within one EDO mode cycle time, tHPC . DC AND OPERATING CHARACTERISTICS (Continued) ICC1 * : Operating Current ( RAS and CAS , Address cycling @ tRC =min.) ICC2 : Standby Current ( RAS = CAS = W =V IH ) ICC3 * : RAS -only Refresh Current ( CAS =V IH , RAS cycling @ tRC =min.) ICC4 * : Extended Data Out Mode Current ( RAS =V IL , CAS , Address cycling @ tHPC =min.) ICC5 : Standby Current ( RAS = CAS = W =V CC -0.2V) ICC6 * : CAS -Before- RAS Refresh Current ( RAS and CAS cycling @ tRC =min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(V IH )=V CC -0.2V, Input low voltage(V IL )=0.2V, CAS = CAS -before- RAS cycling or 0.2V W , OE =V IH , Address=Don ′t care, DQ=Open, T RC =31.25us ICCS : Self Refresh Current Symbol Power Speed Max Units K4E660812B K4E640812B ICC1 Don ′t care -45 -50 -60 100 130 120 110 mA mA mA ICC2 Normal L Don ′t care 2 mA mA ICC3 Don ′t care -45 -50 -60 100 130 120 110 mA mA mA ICC4 Don ′t care -45 -50 -60 110 100 120 110 100 mA mA mA ICC5 Normal L Don ′t care 500 300 500 300 uA uA ICC6 Don ′t care -45 -50 -60 100 130 120 110 mA mA mA ICC7 L Don ′t care 400 400 uA I CCS L Don ′t care 400 400 uA

CMOS DRAMK4E660812B, K4E640812B CAPACITANCE (T A =25 °C, V CC =3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A12] C IN1 - 5 pF Input capacitance [ RAS , CAS , W , OE ] C IN2 - 7 pF Output capacitance [DQ0 - DQ7] C DQ - 7 pF AC CHARACTERISTICS (0 °C ≤T A ≤70 °C, See note 1,2) Parameter Symbol -45 -50 -60 Units Note Min Max Min Max Min Max Random read or write cycle time tRC 74 84 104 ns Read-modify-write cycle time tRWC 101 113 138 ns Access time from RAS tRAC 45 50 60 ns 3,4,10 Access time from CAS tCAC 12 13 15 ns 3,4,5 Access time from column address tAA 23 25 30 ns 3,10 CAS to output in Low-Z tCLZ 3 3 3 ns 3 Output buffer turn-off delay from CAS tCEZ 3 13 3 13 3 13 ns 6,14 OE to output in Low-Z tOLZ 3 3 3 ns 3 Transition time (rise and fall) tT 1 50 1 50 1 50 ns 2 RAS precharge time tRP 25 30 40 ns RAS pulse width tRAS 45 10K 50 10K 60 10K ns RAS hold time tRSH 8 8 10 ns CAS hold time tCSH 35 38 40 ns CAS pulse width tCAS 7 5K 8 10K 10 10K ns RAS to CAS delay time tRCD 11 33 11 37 14 45 ns 4 RAS to column address delay time tRAD 9 22 9 25 12 30 ns 10 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 7 7 10 ns Column address set-up time tASC 0 0 0 ns Column address hold time tCAH 7 7 10 ns Column address to RAS lead time tRAL 23 25 30 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 0 ns 8 Write command hold time tWCH 7 7 10 ns Write command pulse width tWP 6 7 10 ns Write command to RAS lead time tRWL 8 8 10 ns Write command to CAS lead time tCWL 7 7 10 ns Data set-up time tDS 0 0 0 ns 9

CMOS DRAMK4E660812B, K4E640812B AC CHARACTERISTICS (Continued) Parameter Symbol -45 -50 -60 Units Note Min Max Min Max Min Max Data hold time tDH 7 7 10 ns 9 Refresh period (Normal) tREF 64 64 64 ms Refresh period (L-ver) tREF 128 128 128 ms Write command set-up time tWCS 0 0 0 ns 7 CAS to W delay time tCWD 24 27 32 ns 7 RAS to W delay time tRWD 57 64 77 ns 7 Column address to W delay time tAWD 35 39 47 ns 7 CAS set-up time ( CAS -before- RAS refresh) tCSR 5 5 5 ns CAS hold time ( CAS -before- RAS refresh) tCHR 10 10 10 ns RAS to CAS precharge time tRPC 5 5 5 ns Access time from CAS precharge tCPA 24 28 35 ns 3 Hyper Page cycle time tHPC 17 20 25 ns 13 Hyper Page read-modify-write cycle time tHPRWC 47 47 56 ns 13 CAS precharge time (Hyper page cycle) tCP 6.5 7 10 ns RAS pulse width (Hyper page cycle) tRASP 45 200K 50 200K 60 200K ns RAS hold time from CAS precharge tRHCP 24 30 35 ns OE access time tOEA 12 13 15 ns OE to data delay tOED 8 10 13 ns CAS precharge to W delay time tCPWD 36 41 52 ns Output buffer turn off delay time from OE tOEZ 3 11 3 13 3 13 ns 6 OE command hold time tOEH 5 5 5 ns Write command set-up time (Test mode in) tWTS 10 10 10 ns 11 Write command hold time (Test mode in) tWTH 10 10 10 ns 11 W to RAS precharge time ( C -B- R refresh) tWRP 10 10 10 ns W to RAS hold time ( C -B- R refresh) tWRH 10 10 10 ns Output data hold time tDOH 4 5 5 ns Output buffer turn off delay from RAS tREZ 3 13 3 13 3 13 ns 6,14 Output buffer turn off delay from W tWEZ 3 13 3 13 3 13 ns 6 W to data delay tWED 8 15 15 ns OE to CAS hold time tOCH 5 5 5 ns CAS hold time to OE tCHO 5 5 5 ns OE precharge time tOEP 5 5 5 ns W pulse width (Hyper Page Cycle) tWPE 5 5 5 ns RAS pulse width ( C -B- R self refresh) tRASS 100 100 100 us 15,16,17 RAS precharge time ( C -B- R self refresh) tRPS 74 90 110 ns 15,16,17 CAS hold time ( C -B- R self refresh) tCHS -50 -50 -50 ns 15,16,17

CMOS DRAMK4E660812B, K4E640812B TEST MODE CYCLE Parameter Symbol -45 -50 -60 Units Note Min Max Min Max Min Max Random read or write cycle time tRC 79 89 109 ns Read-modify-write cycle time tRWC 110 121 145 ns Access time from RAS tRAC 50 55 65 ns 3,4,10,12 Access time from CAS tCAC 17 18 20 ns 3,4,5,12 Access time from column address tAA 28 30 35 ns 3,10,12 RAS pulse width tRAS 50 10K 55 10K 65 10K ns CAS pulse width tCAS 12 10K 13 10K 15 10K ns RAS hold time tRSH 18 18 20 ns CAS hold time tCSH 39 43 50 ns Column Address to RAS lead time tRAL 28 30 35 ns CAS to W delay time tCWD 29 35 39 ns 7 RAS to W delay time tRWD 62 72 84 ns 7 Column Address to W delay time tAWD 40 47 54 ns 7 Hyper Page cycle time tHPC 22 25 30 ns 13 Hyper Page read-modify-write cycle time tHPRWC 52 53 61 ns 13 RAS pulse width (Hyper page cycle) tRASP 50 200K 55 200K 65 200K ns Access time from CAS precharge tCPA 29 33 40 ns 3 OE access time tOEA 17 18 20 ns OE to data delay tOED 13 18 20 ns OE command hold time tOEH 13 18 20 ns ( Note 11 )

CMOS DRAMK4E660812B, K4E640812B NOTES An initial pause of 200us is required after power-up followed by any 8 RAS -only refresh or CAS -before- RAS refresh cycles before proper device operation is achieved. V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH (min) and V IL (max) and are assumed to be 2ns for all inputs. Measured with a load equivalent to 1 TTL load and 100pF. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . Assumes that tRCD ≥tRCD (max). This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V oh or V ol . tWCS , tRWD , tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical char- acteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min) and tAWD ≥tAWD (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA . These specifications are applied in the test mode. In test mode read cycle, the value of tRAC , tAA , tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. tASC ≥6ns, Assume t T = 2.0ns If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP . For RAS -only refresh and burst CAS -before- RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. For distributed CAS -before- RAS with 15.6us interval CAS -before- RAS refresh should be executed with in 15.6us immedi- ately before and after self refresh in order to meet refresh specification. 10. 11. 12. 13. 14. 15. 16. 17.

CMOS DRAMK4E660812B, K4E640812B RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRALtASR tRAH tASC tCAH tCRP tAA tOEA tCLZ tRAC OPEN tRCH Don ′t care Undefined tRAD tRRH DATA-OUT tREZ tRCS READ CYCLE tOEZ tCEZ tWEZ DQ0 ~ DQ3(7) tOLZ tCAC

CMOS DRAMK4E660812B, K4E640812B tWCS NOTE : D OUT = OPEN WRITE CYCLE ( EARLY WRITE ) RAS V IH - V IL - V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don ′t care Undefined tWCH tWP CAS tRWL tCWL tDS tDH DATA-IN DQ0 ~ DQ3(7)

CMOS DRAMK4E660812B, K4E640812B NOTE : D OUT = OPEN WRITE CYCLE ( OE CONTROLLED WRITE ) RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V IH - V IL - DQ0 ~ DQ3(7) COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP tWP Don ′t care Undefined CAS V IH - V IL - tRWL tCWL tDH tOEHtOED DATA-IN tDS

CMOS DRAMK4E660812B, K4E640812B READ - MODIFY - WRITE CYCLE RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ3(7) ROW ADDR tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP VALID tWP Don ′t care tRWL tCWL tOEZ tOEA tOED tAWD tCWD tRWD DATA-OUT Undefined VALID DATA-IN tRAC tAA tCAC tCLZ tDS tDH COLUMN ADDRESS tOLZ

CMOS DRAMK4E660812B, K4E640812B tDOH HYPER PAGE READ CYCLE RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tASR tCRP Don ′t care Undefined V OH - V OL - DQ0 ~ DQ3(7) tOEP COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tCP tHPC tHPC tHPC tRHCPtCSH tRAD tRAH tASC tCAH tCAH tCAH tASC tCAH tRCS tAA tRCH tASC COLUMN ADDRESS COLUMN ADDR VALID DATA-OUT tOEZ tOEA tOEP tAA tCAC tAA tCPA tCPA VALID DATA-OUT VALID DATA-OUT tOEZ tCLZ tRAC tOEA tOLZ tCAC tRRH tCHO tREZ tOEZ tCAC tOCH tCPA tCAC VALID DATA-OUT tASC tAA tRAL tOEA

CMOS DRAMK4E660812B, K4E640812B RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR. tRASP tRP tRCD tASR tCRP Don ′t care HYPER PAGE WRITE CYCLE ( EARLY WRITE ) Undefined V IH - V IL - DQ0 ~ DQ3(7) tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH tCWL tCWL tCWL tRWL NOTE : D OUT = OPEN tHPC tHPC tWCS tRAL

CMOS DRAMK4E660812B, K4E640812B Don ′t care HYPER PAGE READ-MODIFY-WRITE CYCLE Undefined RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - ROW ADDR tCSH tRASP tRP tASR tRCD tCP tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAS tCAS tCRP tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tRAC tOEA tCLZ tOEZ tCPWD tOED tASC tCLZ tOEA tCAC tAA tDH tOED tRWL tCRP tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS DQ0 ~ DQ3(7) tRSH tOLZ tOLZ tHPRWC tCAC tAA tRAH

CMOS DRAMK4E660812B, K4E640812B HYPER PAGE READ AND WRITE MIXED CYCLE RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP Don ′t care Undefined V I/OH - V I/OL - DQ0 ~ DQ3(7) tWEZ tCP tCP tHPC tHPC tHPC tRAD tRAH tASC tCAH tCAH tCAH tASC tCAH tRCHtRCS tRCS tRCH tASC COLUMN ADDRESS COL. ADDR VALID DATA-OUT tREZtAA tWCS VALID DATA-OUT VALID DATA-OUT VALID DATA-IN tRAC COL. ADDR tCAS tASR tCAStCAS tCAS tASC tCP tRCH tWCH tWPE tCLZ tCPA tWED tAA tWEZ tDS tDH tCAC tOEA READ( t CAC ) READ( tCPA ) WRITE READ( tAA ) tRHCP tRAL tCLZ

CMOS DRAMK4E660812B, K4E640812B Don ′t care RAS - ONLY REFRESH CYCLE* NOTE : W , OE , D IN = Don ′t care Undefined D OUT = OPEN RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - ROW ADDR tRC tRP tASR tCRP tRAS tRAH tRPC tCRP OPEN CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - CAS V IH - V IL - tRC tRP tRAS tRPC tCP tRPC tCSR tCHR tCEZ V OH - V OL - DQ0 ~ DQ3(7) tWRP tWRH W V IH - V IL - tRP

CMOS DRAMK4E660812B, K4E640812B HIDDEN REFRESH CYCLE ( READ ) tOEZ DATA-OUT tRP RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don ′t care Undefined V OH - V OL - DQ0 ~ DQ3(7) tWRH COLUMN ADDRESS tOEA tRAS tRC tCAH tRCS tAA tRAC tCLZ tCAC tCEZ OPEN tRP tWEZ tREZ tOLZ * In Hidden refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. tRAL

CMOS DRAMK4E660812B, K4E640812B tCRP tWCS tRP RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tRAD tASR tRAH tASC Don ′t care HIDDEN REFRESH CYCLE ( WRITE ) Undefined CAS V IH - V IL - V IH - V IL - DQ0 ~ DQ3(7) tRSHtRCD tWRH COLUMN ADDRESS tRAS tRC tCHR tCAH tWRP tDS NOTE : D OUT = OPEN tWP tWCH DATA-IN tDH tRP tRAL

CMOS DRAMK4E660812B, K4E640812B OPEN CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - CAS V IH - V IL - tRPStRASS tRPC tCP tRPC tCSR tCEZ V OH - V OL - DQ0 ~ DQ3(7) tRP Don ′t care Undefined tCHS tWRP tWRH W V IH - V IL - OPEN TEST MODE IN CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - CAS V IH - V IL - tRP tRC tRPC tCP tRPC tCSR tOFF V OH - V OL - DQ0 ~ DQ3(7) tWTS tWTH W V IH - V IL - tCHR tRP tRAS

CMOS DRAMK4E660812B, K4E640812B

32 SOJ 400mil

0 . 4 0 0 ( 1 0 .1 6 ) 0 .4 3 5 ( 1 1 . 0 6 ) 0 .4 4 5 ( 1 1 . 3 0 ) 0.830 (21.08) 0.820 (20.84) MAX 0.841 (21.36) M A X 0 . 1 4 8 ( 3 .7 6 ) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 . 3 6 0 ( 9 .1 5 ) 0 . 3 8 0 ( 9 .6 5 ) MIN #32 Units : Inches (millimeters) PACKAGE DIMENSION

32 TSOP(II) 400mil

0 . 4 5 5 ( 1 1 .5 6 ) 0 . 4 7 1 ( 1 1 .9 6 ) 0.829 (21.05) 0.821 (20.85) MAX 0.841 (21.35) Units : Inches (millimeters) 0.047 (1.20) MIN 0.002 (0.05) 0.020 (0.50) 0.012 (0.30) MAX 0.010 (0.25) 0.004 (0.10) 0 . 4 0 0 ( 1 0 .1 6 ) 0~8 0.030 (0.75) 0.018 (0.45) TYP 0.010 (0.25) O