K4E641612D

K4E661612D SAMSUNG | Alldatasheet

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Technical content

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption( Nor- mal or Low power) are optional features of this family. All of this family have CAS -before- RAS refresh, RAS -only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricat ed using Samsung ′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS -before- RAS refresh capability
• RAS -only and Hidden refresh capability
• Fast parallel test mode capability
• Self-refresh capability (L-ver only)
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) packages
• +3.3V ±0.3V power supply
• Industrial Temperature operating ( -40~85 °C ) Control Clocks Lower Data out Buffer RAS UCAS LCAS W Vcc Vss DQ0 to DQ7 A0~A12 (A0~A11)*1 A0~A8 (A0~A9)*1 Memory Array 4,194,304 x 16 Cells SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 4M x 16bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

Note) *1 : 4K Refresh S en s e A m p s & I/ O Upper Data in Buffer Upper Data out Buffer Lower Data in Buffer DQ 8 to DQ15 OE Row Decoder Column Decoder VBB Generator Refresh Timer Refresh Control Refresh Counter Row Address Buffer Col. Address Buffer

• Part Identification - K4E661612D-TI/P(3.3V, 8K Ref.) - K4E641612D-TI/P(3.3V, 4K Ref.)

FEATURES

• Refresh Cycles Part NO. Refresh cycle Refresh time Normal L-ver K4E661612D* 8K 64ms 128ms K4E641612D 4K Unit : mW * Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS -before- RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
• Active Power Dissipation Speed 8K 4K -45 324 468 -50 288 432 -60 252 396
• Performance Range Speed tRAC tCAC tRC tHPC -45 45ns 12ns 74ns 17ns -50 50ns 13ns 84ns 20ns -60 60ns 15ns 104ns 25ns

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature V CC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C VCC VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 VSS PIN CONFIGURATION (Top Views) Pin Name Pin function A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 15 Data In/Out VSS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+3.3V) N.C No Connection (400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product

• K4E661612D-T
• K4E641612D-T

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature ABSOLUTE MAXIMUM RATINGS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. Parameter Symbol Rating Units Voltage on any pin relative to V SS VIN, VOUT -0.5 to +4.6 V Voltage on V CC supply relative to V SS VCC -0.5 to +4.6 V Storage Temperature Tstg -55 to +150 °C Power Dissipation PD 1 W Short Circuit Output Current IOS Address 50 mA RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= -40 to 85 °C) *1 : Vcc+1.3V at pulse width ≤15ns which is measured at V CC *2 : -1.3 at pulse width ≤15ns which is measured at V SS Parameter Symbol Min Typ Max Units Supply Voltage VCC 3.0 3.3 3.6 V Ground VSS 0 0 0 V Input High Voltage VIH 2.0 - Vcc+0.3 *1 V Input Low Voltage VIL -0.3*2 - 0.8 V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0 ≤VIN≤VCC+0.3V, all other pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V ≤VOUT ≤VCC ) IO(L) -5 5 uA Output High Voltage Level(I OH=-2mA) VOH 2.4 - V Output Low Voltage Level(I OL =2mA) VOL - 0.4 V

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature *Note : ICC1 , I CC3 , I CC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 , I CC3 and I CC6, address can be changed maximum once while RAS =V IL . In I CC4 , address can be changed maximum once within one EDO mode cycle time, t HPC . DC AND OPERATING CHARACTERISTICS (Continued) ICC1 * : Operating Current ( RAS and UCAS , LCAS , Address cycling @ t RC =min.) ICC2 : Standby Current ( RAS = UCAS = LCAS = W =V IH ) ICC3 * : RAS -only Refresh Current ( UCAS = LCAS =V IH , RAS , Address cycling @ tRC =min.) ICC4 * : Extended Data Out Mode Current ( RAS =V IL , UCAS or LCAS , Address cycling @ tHPC =min.) ICC5 : Standby Current ( RAS = UCAS = LCAS = W =V CC -0.2V) ICC6 * : CAS -Before- RAS Refresh Current ( RAS and UCAS or LCAS cycling @ t RC =min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(V IH )=V CC -0.2V, Input low voltage(V IL )=0.2V, UCAS , LCAS = CAS -before- RAS cycling or 0.2V W , OE =V IH , Address=Don ′t care, DQ=Open, T RC =31.25us ICCS : Self Refresh Current Symbol Power Speed Max Units K4E661612D K4E641612D ICC1 Don ′t care -45 -50 -60 130 120 110 mA mA mA ICC2 Normal L Don ′t care mA mA ICC3 Don ′t care -45 -50 -60 130 120 110 mA mA mA ICC4 Don ′t care -45 -50 -60 100 100 mA mA mA ICC5 Normal L Don ′t care 0.5 200 0.5 200 mA uA ICC6 Don ′t care -45 -50 -60 130 120 110 130 120 110 mA mA mA ICC7 L Don ′t care 350 350 uA ICCS L Don ′t care 350 350 uA

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature CAPACITANCE (T A =25 °C, V CC =3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A12] C IN1 - 5 pF Input capacitance [ RAS , UCAS , LCAS , W , OE ] C IN2 - 7 pF Output capacitance [DQ0 - DQ15] C DQ - 7 pF AC CHARACTERISTICS (-40 °C ≤ T A ≤ 85 °C, See note 2) Parameter Symbol -45 -50 -60 Unit s Note Min Max Min Max Min Max Random read or write cycle time t RC 74 84 104 ns Read-modify-write cycle time t RWC 101 113 138 ns Access time from RAS t RAC 45 50 60 ns 3,4,10 Access time from CAS t CAC 12 13 15 ns 3,4,5 Access time from column address t AA 23 25 30 ns 3,10 CAS to output in Low-Z t CLZ 3 3 3 ns 3 Output buffer turn-off delay from CAS t CEZ 3 13 3 13 3 13 ns 6,20 OE to output in Low-Z t OLZ 3 3 3 ns 3 Transition time (rise and fall) t T 1 50 1 50 1 50 ns 2 RAS precharge time t RP 25 30 40 ns RAS pulse width t RAS 45 10K 50 10K 60 10K ns RAS hold time t RSH 8 8 10 ns CAS hold time t CSH 35 38 40 ns CAS pulse width t CAS 7 5K 8 10K 10 10K ns RAS to CAS delay time t RCD 11 33 11 37 14 45 ns 4 RAS to column address delay time t RAD 9 22 9 25 12 30 ns 10 CAS to RAS precharge time t CRP 5 5 5 ns Row address set-up time t ASR 0 0 0 ns Row address hold time t RAH 7 7 10 ns Column address set-up time t ASC 0 0 0 ns 13 Column address hold time t CAH 7 7 10 ns 13 Column address to RAS lead time t RAL 23 25 30 ns Read command set-up time t RCS 0 0 0 ns Read command hold time referenced to CAS t RCH 0 0 0 ns 8 Read command hold time referenced to RAS t RRH 0 0 0 ns 8 Write command hold time t WCH 7 7 10 ns Write command pulse width t WP 6 7 10 ns Write command to RAS lead time t RWL 8 8 10 ns Write command to CAS lead time t CWL 7 7 10 ns 16 Data set-up time t DS 0 0 0 ns 9,19

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature AC CHARACTERISTICS (Continued) Parameter Symbol -45 -50 -60 Units Note Min Max Min Max Min Max Data hold time tDH 7 7 10 ns 9,19 Refresh period (Normal) tREF 64 64 64 ms Refresh period (L-ver) tREF 128 128 128 ms Write command set-up time tWCS 0 0 0 ns 7 CAS to W delay time tCWD 24 27 32 ns 7,15 RAS to W delay time tRWD 57 64 77 ns 7 Column address to W delay time tAWD 35 39 47 ns 7 CAS set-up time ( CAS -before- RAS refresh) tCSR 5 5 5 ns 17 CAS hold time ( CAS -before- RAS refresh) tCHR 10 10 10 ns 18 RAS to CAS precharge time tRPC 5 5 5 ns Access time from CAS precharge tCPA 24 28 35 ns 3 Hyper Page cycle time tHPC 17 20 25 ns 21 Hyper Page read-modify-write cycle time tHPRWC 47 47 56 ns 21 CAS precharge time (Hyper page cycle) tCP 6.5 7 10 ns 14 RAS pulse width (Hyper page cycle) tRASP 45 200K 50 200K 60 200K ns RAS hold time from CAS precharge tRHCP 24 30 35 ns OE access time tOEA 12 13 15 ns 3 OE to data delay tOED 8 10 13 ns CAS precharge to W delay time tCPWD 36 41 52 ns Output buffer turn off delay time from OE tOEZ 3 11 3 13 3 13 ns 6 OE command hold time tOEH 5 5 5 ns Write command set-up time (Test mode in) tWTS 10 10 10 ns 11 Write command hold time (Test mode in) tWTH 10 10 10 ns 11 W to RAS precharge time (C-B-R refresh) tWRP 10 10 10 ns W to RAS hold time (C-B-R refresh) tWRH 10 10 10 ns Output data hold time tDOH 4 5 5 ns Output buffer turn off delay from RAS tREZ 3 13 3 13 3 13 ns 6,20 Output buffer turn off delay from W tWEZ 3 13 3 13 3 13 ns 6 W to data delay tWED 8 15 15 ns OE to CAS hold time tOCH 5 5 5 ns CAS hold time to OE tCHO 5 5 5 ns OE precharge time tOEP 5 5 5 ns W pulse width (Hyper Page Cycle) tWPE 5 5 5 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 22,23,24 RAS precharge time (C-B-R self refresh) tRPS 74 90 110 ns 22,23,24 CAS hold time (C-B-R self refresh) tCHS -50 -50 -50 ns 22,23,24

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature TEST MODE CYCLE Parameter Symbol -45 -50 -60 Units Note Min Max Min Max Min Max Random read or write cycle time tRC 79 89 109 ns Read-modify-write cycle time tRWC 110 121 145 ns Access time from RAS tRAC 50 55 65 ns 3,4,10,12 Access time from CAS tCAC 17 18 20 ns 3,4,5,12 Access time from column address tAA 28 30 35 ns 3,10,12 RAS pulse width tRAS 50 10K 55 10K 65 10K ns CAS pulse width tCAS 12 10K 13 10K 15 10K ns RAS hold time tRSH 18 18 20 ns CAS hold time tCSH 39 43 50 ns Column Address to RAS lead time tRAL 28 30 35 ns CAS to W delay time tCWD 29 35 39 ns 7 RAS to W delay time tRWD 62 72 84 ns 7 Column Address to W delay time tAWD 40 47 54 ns 7 Hyper Page cycle time tHPC 22 25 30 ns 21 Hyper Page read-modify-write cycle time tHPRWC 52 53 61 ns 21 RAS pulse width (Hyper page cycle) tRASP 50 200K 55 200K 65 200K ns Access time from CAS precharge tCPA 29 33 40 ns 3 OE access time tOEA 17 18 20 ns 3 OE to data delay tOED 13 18 20 ns OE command hold time tOEH 13 18 20 ns ( Note 11 )

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature NOTES An initial pause of 200us is required after power-up followed by any 8 RAS -only or CAS -before- RAS refresh cycles before proper device operation is achieved. Input voltage levels are Vih/Vil. V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH (min) and V IL (max) and are assumed to be 2ns for all inputs. Measured with a load equivalent to 1 TTL load and 100pF. Operation within the t RCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If t RCD is greater than the specified t RCD (max) limit, then access time is controlled exclusively by tCAC . Assumes that t RCD ≥t RCD (max). This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V oh or V ol . t WCS , tRWD , tCWD and t AWD are non restrictive operating parameters. They are included in the data sheet as electric charac- teristics only. If tWCS ≥tWCS (min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥t CWD (min), t RWD ≥t RWD (min) and t AWD ≥t AWD (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or t RRH must be satisfied for a read cycle. This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write cycle and read-modify-write cycles. Operation within the t RAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If t RAD is greater than the specified t RAD (max) limit, then access time is controlled by t AA . These specifiecations are applied in the test mode. In test mode read cycle, the value of t RAC , tAA , tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. t ASC , t CAH are referenced to the earlier CAS falling edge. t CP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. t CWD is referenced to the later CAS falling edge at word read-modify-write cycle. K4E64(6)1612D Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H X X X X Hi-Z Hi-Z Standby L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z - 10. 13. 12. 11. 15. 14.

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tCWL is specified from W falling edge to the earlier CAS rising edge. tCSR is referenced to earlier CAS falling before RAS transition low. tCHR is referenced to the later CAS rising high after RAS transition low. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. tASC ≥6ns, Assume t T=2.0ns, if t ASC ≤ 6ns, then t HPC (min) and t CAS (min) must be increased by the value of "6ns-t ASC ". If t RASS ≥100us, then RAS precharge time must use tRPS instead of t RP . For RAS -only-Refresh and Burst CAS -before- RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. For distributed CAS -before- RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. t CSR t CHR RAS LCAS UCAS tDS tDH LCAS UCAS DQ0 ~ DQ15 Din 22. 21. 20. 19. 18. 17. 16. 23. 24.

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tCRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS t RC tCRP tRP tCSH t RSHt RCD tCAS t RAL t ASR tRAH t ASC tCAH tCRP tAA t OEA tCAC t CLZ t RAC OPEN t CEZ tRCH Don ′t care Undefined LCAS V IH - V IL - tCRP tCSH tRSHtRCD tCAS tRAD tRRH V OH - V OL - DQ8 ~ DQ15 tCAC tCLZ t RAC OPEN DATA-OUT DATA-OUT t CEZ tOEZ tOEZ tRCS WORD READ CYCLE tOLZ

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature NOTE : D IN = OPEN LOWER BYTE READ CYCLE RAS V IH - V IL - LCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS t RAS t RC t RP t CSH tRSHtRCD tCAS tRAL tRAD t ASR t RAH tASC tCAH tCRP t AA t OEA t CAC t CLZ t RAC OPEN DATA-OUT tOEZ tCEZ tRRH t RCH Don ′t care Undefined tCRP tRPC UCAS V IH - V IL - OPEN V OH - V OL - DQ8 ~ DQ15 t RCS tOLZ

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature NOTE : D IN = OPEN UPPER BYTE READ CYCLE RAS V IH - V IL - LCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC t CRP tRP tCSH tRSHt RCD t CAS t RAL t RAD tASR tRAH t ASC t CAH t CRP tAA t OEA t CAC tCLZ tRAC OPEN DATA-OUT t OEZ t CEZ tRRH t RCH Don ′t care Undefined UCAS V IH - V IL - OPEN V OH - V OL - DQ8 ~ DQ15 t CRP tRPC t RCS tOLZ

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS t RAS t RC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD t ASR t RAH tASC tCAH t CRP Don ′t care WORD WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - tWCS V IH - V IL - DQ0 ~ DQ7 tDS V IH - V IL - DQ8 ~ DQ15 tCRP tCSH tRSHt RCD tCAS t CRP t WCH tWP t DH DATA-IN tDS t DH DATA-IN

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature t CRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS t RAS tRC t RP tRAL t RAD tASR t RAH tASC tCAH Don ′t care LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - t WCS V IH - V IL - DQ0 ~ DQ7 tDS V IH - V IL - DQ8 ~ DQ15 tCRP tCSH t RSHtRCD tCAS t WCH t WP tDH DATA-IN t CRP

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC t CRP t RP tCSH t RSHt RCD t CAS t RAL t RAD tASR tRAH tASC tCAH tCRP Don ′t care UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - t WCS V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tWCH t WP t DS tDH DATA-IN tCRP

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS t RAS t RC tCRP t RP t CSH tRSHtRCD tCAS tRAL t RAD t ASR t RAH t ASC tCRP Don ′t care WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tCRPtRSHt RCD t CAS tCRP tRWL tWP t CWL t DH t DH DATA-IN COLUMN ADDRESS t OEHtOED t DS t DS DATA-IN tCSH t CAH

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS t RC tRP t RAL t RAD tASR tRAH t ASC t CAH Don ′t care LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - t RWL V IH - V IL - DQ0 ~ DQ7 tDS V IH - V IL - DQ8 ~ DQ15 tCRP t CSH tRSHt RCD t CAS t CRP tWP tCWL tDH DATA-IN t CRP tRPC t OEH t OED

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC t CRP tRP tCSH tRSHtRCD tCAS tRAL tRAD t ASR t RAH tASC t CAH tCRP Don ′t care UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - V IH - V IL - V IH - V IL - tCRP tRWL t WP t CWL t DS tDH DATA-IN tOEH tOED DQ0 ~ DQ7 DQ8 ~ DQ15 t CRP

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tRWL RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR. t RAS t RWC t RP t RSHtRCD t CAS t CSH t RAD tASR tRAH tASC t CAH t CRP Don ′t care WORD READ - MODIFY - WRITE CYCLE Undefined LCAS V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 V I/OH - V I/OL - DQ8 ~ DQ15 tWP t CWL tDS tDH t RSHtRCD t CAS t CRP tAWD tCWD tOEA t RWD tOED t OEZtRAC tAA t OEZtRAC tAA tDS tOED tDH VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tCAC tCLZ tCAC tCLZ tOLZ tOLZ

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tRWL RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR. tRAS tRWC tRP tCSH tRAD tASR tRAH tASC tCAH tCRP Don′t care LOWER-BYTE READ - MODIFY - WRITE CYCLE Undefined LCAS VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 tWP tCWL tDS tDH tRSHtRCD tCAS tCRP tAWD tCWD tOEA tRWD tOED tOEZtRAC tAA VALID DATA-OUT VALID DATA-IN tRPC tCAC tCLZ OPEN tOLZ

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tRWL RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP Don′t care UPPER-BYTE READ - MODIFY - WRITE CYCLE Undefined LCAS VIH - VIL - VOH - VOL - DQ0 ~ DQ7 VI/OH - VI/OL - DQ8 ~ DQ15 tWP tCWL tAWD tCWD tOEA tRWD tOEZtRAC tAA tDS tOED tDH VALID DATA-OUT VALID DATA-IN tCRP tRPC tCAC tCLZ OPEN tOLZ

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tASC tOLZ tCLZ tOLZ tCLZ RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tCRP Don′t care HYPER PAGE MODE WORD READ CYCLE Undefined LCAS VIH - VIL - VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tCP tREZ tHPC tHPC tHPC tRHCPtCSH tRCD tCRP tCAS tCAS tCAS tCAS tCP tCP tCP tRAD tRCS tOEA tRCH tRRH COLUMN ADDRESS COLUMN ADDR tOEZ tOEP tCHO tAA tCPA tAA tCAC VALID DATA-OUT tOEP tOEZtRAC tCAC tDOH VALID DATA-OUT VALID DATA-OUT tOCH tCPA tAA tCAC tCAC tCPA tOEZ VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT tOEP tOEZtRAC tCAC VALID DATA-OUT VALID DATA-OUT tOEZ VALID DATA-OUT VALID DATA-OUT tDOH tOEA tASR tRAH tASC tCAH tASC tCAH tCAH tCAHtASC tRAL

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tOEA tOLZ tCLZ RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tCRP Don′t care HYPER PAGE MODE LOWER BYTE READ CYCLE Undefined LCAS VIH - VIL - VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 COLUMN ADDRESS tREZ tRHCPtCSH tRCD tCAS tCAS tCAS tCAS tCP tCP tCP tRAD tRCS tRCH tRRH COLUMN ADDRESS COLUMN ADDR tOEZ tOEP tCHO tCPAtCAC VALID DATA-OUT tOEP tOEZtRAC tCAC tDOH VALID DATA-OUT VALID DATA-OUT tOCH tCPA tCAC tCAC tCPA tOEZ VALID DATA-OUT VALID DATA-OUT OPEN tRPC tASR tRAH tASC tCAH tASC tCAH tCAH tASC tCAHtASC tAA tHPC tHPC tHPC tAAtAA tAA tOEA tRAL

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR. tRASP tRP tRCD tASR tCRP Don′t care HYPER PAGE MODE UPPER BYTE READ CYCLE Undefined LCAS VIH - VIL - VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tCP tREZ tHPC tHPC tHPC tRHCPtCSH tCRP tRAH tASC tCAH tCAH tCAH tASC tCAH tRCS tOEA tRCH tRRH COLUMN ADDRESS COLUMN ADDR. tOEZ tOEP tCHO tCPAtCAC VALID DATA-OUT tOEP tOEZtRAC tCAC tOLZ tCLZ tDOH VALID DATA-OUT VALID DATA-OUT tOCH tCPA tCAC tCAC tCPA tOEZ VALID DATA-OUT VALID DATA-OUT OPEN tASC tRPC tRPC tRAD tASC tAAtAA tAA tOEA tRAL

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tASR tCRP Don′t care HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) Undefined LCAS VIH - VIL - VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tCRP tHPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tCAS tCP tCAS tCP tCAS tRSH tRCD tCRP tHPC tHPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH VALID DATA-IN VALID DATA-IN VALID DATA-IN tDH tDH tDHtDStDStDS NOTE : D OUT = OPEN tHPC tRAL

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tASR tCRP Don′t care HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) Undefined LCAS VIH - VIL - VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tRPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tRCD tCRP tHPC tHPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH NOTE : D OUT = OPEN tRAL

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tWCS RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP tASR tCRP Don′t care HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) Undefined LCAS VIH - VIL - VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tRPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tRCD tCRP tHPC tHPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH NOTE : D OUT = OPEN tRAL

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don′t care HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE Undefined tRCD tCP tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAS tCAS tCRP tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tASC tCLZ tOEA tCAC tAA tDH tOED LCAS VIH - VIL - tRCD tCP tCAS tCAS tCRP tCRP tCRP VI/OH - VI/OL - DQ8 ~ DQ15 VALID DATA-OUT tDH tAA tRAC tCLZ tCAC VALID DATA-IN VALID DATA-OUT VALID DATA-IN tCLZ tCAC tAA tDH tOEZ tOED tDS tDS tDS tOED tOEZ tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tHPRWC tRSH tRWL tRCS tRAH

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tASC RAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don′t care HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE Undefined tRAD tCAH tWP tDH COL. ADDR COL. ADDR tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tCLZ tOEA tCAC tAA tDH tOED tRWL tRCD tCP tCAS tCAS tCRP tCRP tCRP VI/OH - VI/OL - DQ8 ~ DQ15 tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tRPC tRSH OPEN LCAS VIH - VIL - UCAS VIH - VIL - tHPRWC tRCS tOLZ tOLZ tRAH

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tASC tCRP RAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - VI/OH - VI/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don′t care HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE Undefined tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tCLZ tOEA tCAC tAA tDH tOED tRWL tRCD tCP tCAS tCAS tCRP tCRP VI/OH - VI/OL - DQ8 ~ DQ15 tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tRPC tRSH OPEN LCAS VIH - VIL - UCAS VIH - VIL - tHPRWC tASC tRCS tRAH tOLZ tOLZ

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature HYPER PAGE READ AND WRITE MIXED CYCLE RAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - COLUMN ADDRESS ROW ADDR tRASP tRP Don′t care Undefined VI/OH - VI/OL - DQ0 ~ DQ7 tWEZ tCP tHPC tHPC tHPC tRCD tRAH tASC tCAH tCAH tCAH tASC tCAH tRCHtRCS tRCS tRCH tASC COLUMN ADDRESS COL. ADDR VALID DATA-OUT tREZtAA tWCS VALID DATA-OUT VALID DATA-OUT VALID DATA-IN tRAC COL. ADDR tCAS tASR tCAStCAS tCAS tASC tCP tRCH tWCH tWPE tCLZ tCPA tWED tAA tWEZ tDS tDH tCAC tOEA tCP tHPC tHPC tCAS tCAStCAS tCAS tCP VI/OH - VI/OL - DQ8 ~ DQ15 tWEZ VALID DATA-OUT tREZtAA VALID DATA-OUT VALID DATA-OUT VALID DATA-IN tRAC tAA tWEZ tDS tDH tCAC tOEA LCAS VIH - VIL - UCAS VIH - VIL - tCP tHPC tCP READ( tCAC ) READ( tCPA) WRITE READ( tAA ) tRAD tRHCP tRAL

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tCRP OPEN RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - ROW ADDR tRC tRP tASR tCRP RAS - ONLY REFRESH CYCLE LCAS VIH - VIL - tRAS tRAH NOTE : W, OE , DIN = Don′t care DOUT = OPEN tRPC CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care RAS VIH - VIL - UCAS VIH - VIL - tRC tRP LCAS VIH - VIL - tRAS tRPC tCP tRPC tCSR tCHR tCP tCSR tCHR tCEZ OPEN VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 tWRP tWRH W VIH - VIL - Don′t care tRP Undefined

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tOEZ DATA-IN DATA-OUT tRP RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don′t care HIDDEN REFRESH CYCLE ( READ ) Undefined LCAS VIH - VIL - VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 tRSHtRCD tCRP tWRH COLUMN ADDRESS tOEA tRAS tRC tCHR tCAH tRCS tAA tRAC tCLZ tCAC DATA-OUT tCEZ OPEN OPEN tRP tREZ tWEZ tOLZ * In Hidden refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off. tRAL

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature tWCS tRP RAS VIH - VIL - UCAS VIH - VIL - A VIH - VIL - W VIH - VIL - OE VIH - VIL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don′t care HIDDEN REFRESH CYCLE ( WRITE ) Undefined LCAS VIH - VIL - VIH - VIL - DQ0 ~ DQ7 VIH - VIL - DQ8 ~ DQ15 tRSHtRCD tCRP tWRH COLUMN ADDRESS tRAS tRC tCHR tCAH tWRP tDS NOTE : D OUT = OPEN tWP tWCH DATA-IN tDH tDS DATA-IN tDH tRP

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature OPEN CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don′t care RAS VIH - VIL - UCAS VIH - VIL - tRPS LCAS VIH - VIL - tRASS tRPC tCP tRPC tCSR tCEZ OPEN VOH - VOL - DQ0 ~ DQ7 VOH - VOL - DQ8 ~ DQ15 tWRP tWRH W VIH - VIL - tCHS tCP tCSR tCHS TEST MODE IN CYCLE NOTE : OE , A = Don′t care RAS VIH - VIL - UCAS VIH - VIL - tRP LCAS VIH - VIL - tRC tRPC tCP tRPC tCSR OPEN VOH - VOL - DQ0 ~ DQ15 tCHR tCP tCSR tCHR tRP tRP Don′t care Undefined tWTS tWTH W VIH - VIL - tCEZ tRAS

CMOS DRAMK4E661612D,K4E641612D Industrial Temperature

50 TSOP(II) 400mil Units : Inches (millimeters)

0.047 (1.20) MIN 0.002 (0.05) 0.018 (0.45) 0.010 (0.25) 0.821 (20.85) 0.829 (21.05) 0.841 (21.35) MAX 0.010 (0.25) 0.004 (0.10) 0.400 (10.16) 0.471 (11.96) 0.455 (11.56) 0~8 0.030 (0.75) 0.018 (0.45) TYP 0.010 (0.25) O PACKAGE DIMENSION