K4E641611D-TC60

K4E661611D SAMSUNG | Alldatasheet

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Technical content

CMOS DRAMK4E661611D, K4E641611D This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-50 or -60) are optional features of this family. All of this family have CAS -before- RAS refresh, RAS -only refresh and Hidden refresh capabilities. This 4Mx16 EDO Mode DRAM family is fabricated using Samsung ′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS -before- RAS refresh capability
• RAS -only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) package
• +5.0V ±10% power supply Control Clocks Lower Data out Buffer RAS UCAS LCAS W Vcc Vss DQ0 to DQ7 A0~A12 (A0~A11)*1 A0~A8 (A0~A9)*1 Memory Array 4,194,304 x 16 Cells SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 4M x 16bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

Note) *1 : 4K Refresh S e n s e A m p s & I /O Upper Data in Buffer Upper Data out Buffer Lower Data in Buffer DQ 8 to DQ15 OE Row Decoder Column Decoder VBB Generator Refresh Timer Refresh Control Refresh Counter Row Address Buffer Col. Address Buffer

• Part Identification - K4E661611D-TC(5.0V, 8K Ref.) - K4E641611D-TC(5.0V, 4K Ref.)

FEATURES

• Refresh Cycles Part NO. Refresh cycle Refresh time Normal K4E661611D* 8K 64ms K4E641611D 4K
• Performance Range Speed tRAC tCAC tRC tHPC -50 50ns 13ns 84ns 20ns -60 60ns 15ns 104ns 25ns
• Active Power Dissipation Speed 8K 4K -50 495 660 -60 440 605 Unit : mW * Access mode & RAS only refresh mode : 8K cycle/64ms CAS -before- RAS & Hidden refresh mode : 4K cycle/64ms

CMOS DRAMK4E661611D, K4E641611D V CC DQ0 DQ1 DQ2 DQ3 V CC DQ4 DQ5 DQ6 DQ7 N.C V CC W RAS N.C N.C N.C N.C V CC V SS DQ15 DQ14 DQ13 DQ12 V SS DQ11 DQ10 DQ9 DQ8 N.C V SS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 V SS PIN CONFIGURATION (Top Views) Pin Name Pin function A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 15 Data In/Out V SS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable V CC Power(+5.0V) N.C No Connection (400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product

• K4E661611D-T
• K4E641611D-T

CMOS DRAMK4E661611D, K4E641611D ABSOLUTE MAXIMUM RATINGS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. Parameter Symbol Rating Units Voltage on any pin relative to V SS V IN, V OUT -1.0 to +7.0 V Voltage on V CC supply relative to V SS V CC -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 °C Power Dissipation P D 1 W Short Circuit Output Current IOS Address 50 mA RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A = 0 to 70 °C) *1 : V CC +2.0V at pulse width ≤20ns which is measured at V CC *2 : -2.0 at pulse width ≤20ns which is measured at V SS Parameter Symbol Min Typ Max Units Supply Voltage V CC 4.5 5.0 5.5 V Ground V SS 0 0 0 V Input High Voltage V IH 2.6 - V CC +1.0 *1 V Input Low Voltage V IL -1.0 *2 - 0.7 V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0 ≤V IN ≤V CC +0.5V, all other pins not under test=0 Volt) I I(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V ≤V OUT ≤V CC ) IO(L) -5 5 uA Output High Voltage Level(I OH =-5mA) V OH 2.4 - V Output Low Voltage Level(I OL =4.2mA) V OL - 0.4 V

CMOS DRAMK4E661611D, K4E641611D *Note : ICC1 , I CC3 , I CC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 , I CC3 and I CC6, address can be changed maximum once while RAS =V IL . In I CC4 , address can be changed maximum once within one EDO mode cycle time tHPC . DC AND OPERATING CHARACTERISTICS (Continued) ICC1 * : Operating Current ( RAS and UCAS , LCAS , Address cycling @ tRC =min.) ICC2 : Standby Current ( RAS = UCAS = LCAS = W =V IH ) ICC3 * : RAS -only Refresh Current ( UCAS = LCAS =V IH , RAS , Address cycling @ tRC =min.) ICC4 * : Extended Data Out Mode Current ( RAS =V IL , UCAS or LCAS , Address cycling @ tHPC =min.) ICC5 : Standby Current ( RAS = UCAS = LCAS = W =V CC -0.2V) ICC6 * : CAS -Before- RAS Refresh Current ( RAS and UCAS or LCAS cycling @ tRC =min) Symbol Power Speed Max Units K4E661611D K4E641611D ICC1 Don ′t care -50 -60 120 110 mA mA ICC2 Normal Don ′t care 2 2 mA ICC3 Don ′t care -50 -60 120 110 mA mA ICC4 Don ′t care -50 -60 100 110 100 mA mA ICC5 Normal Don ′t care 1 1 mA ICC6 Don ′t care -50 -60 120 110 120 110 mA mA

CMOS DRAMK4E661611D, K4E641611D CAPACITANCE (T A =25 °C, V CC =5.0V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A12] C IN1 - 5 pF Input capacitance [ RAS , UCAS , LCAS , W , OE ] C IN2 - 7 pF Output capacitance [DQ0 - DQ15] C DQ - 7 pF AC CHARACTERISTICS (0 °C ≤T A ≤70 °C, See note 1,2) Parameter Symbol -50 -60 Units Note Min Max Min Max Random read or write cycle time tRC 84 104 ns Read-modify-write cycle time tRWC 116 138 ns Access time from RAS tRAC 50 60 ns 3,4,10 Access time from CAS tCAC 13 15 ns 3,4,5 Access time from column address tAA 25 30 ns 3,10 CAS to output in Low-Z tCLZ 3 3 ns 3 Output buffer turn-off delay from CAS tCEZ 3 13 3 13 ns 6,21 OE to output in Low-Z tOLZ 3 3 ns 3 Transition time (rise and fall) tT 1 50 1 50 ns 2 RAS precharge time tRP 30 40 ns RAS pulse width tRAS 50 10K 60 10K ns RAS hold time tRSH 13 15 ns CAS hold time tCSH 38 45 ns CAS pulse width tCAS 8 10K 10 10K ns RAS to CAS delay time tRCD 20 37 20 45 ns 4 RAS to column address delay time tRAD 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns Column address hold time tCAH 8 10 ns 13 Column address to RAS lead time tRAL 25 30 ns 13 Read command set-up time tRCS 0 0 ns Read command hold time referenced to CAS tRCH 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 ns 8 Write command hold time tWCH 10 10 ns Write command pulse width tWP 10 10 ns Write command to RAS lead time tRWL 13 15 ns Write command to CAS lead time tCWL 8 10 ns 16 Data set-up time tDS 0 0 ns 9,19

CMOS DRAMK4E661611D, K4E641611D AC CHARACTERISTICS (Continued) Parameter Symbol -50 -60 Units Note Min Max Min Max Data hold time tDH 8 10 ns 9,19 Refresh period (4K, Normal) tREF 64 64 ms Refresh period (8K, Normal) tREF 64 64 ms Write command set-up time tWCS 0 0 ns 7 CAS to W delay time tCWD 30 32 ns 7,15 RAS to W delay time tRWD 67 77 ns 7 Column address W delay time tAWD 42 47 ns 7 CAS set-up time ( CAS -before- RAS refresh) tCSR 5 5 ns 17 CAS hold time ( CAS -before- RAS refresh) tCHR 10 10 ns 18 RAS to CAS precharge time tRPC 5 5 ns Access time from CAS precharge tCPA 28 35 ns 3 Hyper Page cycle time tHPC 20 25 ns 20 Hyper Page read-modify-write cycle time tHPRWC 47 56 ns 20 CAS precharge time (Hyper page cycle) tCP 8 10 ns 14 RAS pulse width (Hyper page cycle) tRASP 50 200K 60 200K ns RAS hold time from CAS precharge tRHCP 30 35 ns OE access time tOEA 13 15 ns OE to data delay tOED 13 13 ns CAS precharge to W delay time tCPWD 45 54 ns Output buffer turn off delay time from OE tOEZ 3 13 3 13 ns 6 OE command hold time tOEH 13 15 ns Write command set-up time (Test mode in) tWTS 10 10 ns 11 Write command hold time (Test mode in) tWTH 10 10 ns 11 W to RAS precharge time ( C -B- R refresh) tWRP 10 10 ns W to RAS hold time ( C -B- R refresh) tWRH 10 10 ns Output data hold time tDOH 5 5 ns Output buffer turn off delay from RAS tREZ 3 13 3 13 ns 6,21 Output buffer turn off delay from W tWEZ 3 13 3 13 ns 6 W to data delay tWED 15 15 ns OE to CAS hold time tOCH 5 5 ns CAS hold time to OE tCHO 5 5 ns OE precharge time tOEP 5 5 ns W pulse width (Hyper page cycle) tWPE 5 5 ns RAS pulse width ( C -B- R self refresh) tRASS 100 100 us 22,23,24 RAS precharge time ( C -B- R self refresh) tRPS 90 110 ns 22,23,24 CAS hold time ( C -B- R self refresh) tCHS -50 -50 ns 22,23,24

CMOS DRAMK4E661611D, K4E641611D TEST MODE CYCLE Parameter Symbol -50 -60 Units Note Min Max Min Max Random read or write cycle time tRC 89 109 ns Read-modify-write cycle time tRWC 121 145 ns Access time from RAS tRAC 55 65 ns 3,4,10,12 Access time from CAS tCAC 18 20 ns 3,4,5,12 Access time from column address tAA 30 35 ns 3,10,12 RAS pulse width tRAS 55 10K 65 10K ns CAS pulse width tCAS 13 10K 15 10K ns RAS hold time tRSH 18 20 ns CAS hold time tCSH 43 50 ns Column Address to RAS lead time tRAL 30 35 ns CAS to W delay time tCWD 35 39 ns 7 RAS to W delay time tRWD 72 84 ns 7 Column Address to W delay time tAWD 47 54 ns 7 Hyper Page cycle time tHPC 25 30 ns 20 Hyper Page read-modify-write cycle time tHPRWC 53 61 ns 20 RAS pulse width (Hyper page cycle) tRASP 55 200K 65 200K ns Access time from CAS precharge tCPA 33 40 ns 3 OE access time tOEA 18 20 ns OE to data delay tOED 18 20 ns OE command hold time tOEH 18 20 ns ( Note 11 )

CMOS DRAMK4E661611D, K4E641611D K4E64(6)1611C Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H X X X X Hi-Z Hi-Z Standby L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z - NOTES An initial pause of 200us is required after power-up followed by any 8 RAS -only refresh or CAS -before- RAS refresh cycles before proper device operation is achieved. V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH (min) and V IL (max) and are assumed to be 2ns for all inputs. Measured with a load equivalent to 2 TTL load and 100pF. Operation within the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . Assumes that tRCD ≥tRCD (max). These parameter defines the time at which the output achieves the open circuit condition and is not referenced to V oh or V ol . tWCS , tRWD , tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical charac- teristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the dura- tion of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min) and tAWD ≥tAWD (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA . These specifications are applied in the test mode. In test mode read cycle, the value of tRAC , tAA , tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. tASC , tCAH are referenced to the earlier CAS falling edge. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. 10. 13. 12. 11. 15. 14.

CMOS DRAMK4E661611D, K4E641611D tCWL is specified from W falling edge to the earlier CAS rising edge. tCSR is referenced to the earlier CAS falling edge before RAS transition low. tCHR is referenced to the later CAS rising edge after RAS transition low. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle. tASC ≥6ns, Assume t T = 2.0ns If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP . For RAS -only refresh and burst CAS -before- RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. For distributed CAS -before- RAS with 15.6us interval CAS -before- RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. tCSR tCHR RAS LCAS UCAS tDS tDH LCAS UCAS DQ0 ~ DQ15 Din 22. 21. 20. 19. 18. 17. 16. 23. 24.

CMOS DRAMK4E661611D, K4E641611D tCRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRALtASR tRAH tASC tCAH tCRP tAA tOEA tCAC tCLZ tRAC OPEN tCEZ tRCH Don ′t care Undefined LCAS V IH - V IL - tCRP tCSH tRSHtRCD tCAS tRAD tRRH V OH - V OL - DQ8 ~ DQ15 tCAC tCLZ tRAC OPEN DATA-OUT DATA-OUT tCEZ tOEZ tOEZ tRCS WORD READ CYCLE tOLZ

CMOS DRAMK4E661611D, K4E641611D NOTE : D IN = OPEN LOWER BYTE READ CYCLE RAS V IH - V IL - LCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP tAA tOEA tCAC tCLZ tRAC OPEN DATA-OUT tOEZ tCEZ tRRH tRCH Don ′t care Undefined tCRP tRPC UCAS V IH - V IL - OPEN V OH - V OL - DQ8 ~ DQ15 tRCS tOLZ

CMOS DRAMK4E661611D, K4E641611D NOTE : D IN = OPEN UPPER BYTE READ CYCLE RAS V IH - V IL - LCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP tAA tOEA tCAC tCLZ tRAC OPEN DATA-OUT tOEZ tCEZ tRRH tRCH Don ′t care Undefined UCAS V IH - V IL - OPEN V OH - V OL - DQ8 ~ DQ15 tCRP tRPC tRCS tOLZ

CMOS DRAMK4E661611D, K4E641611D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don ′t care WORD WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - tWCS V IH - V IL - DQ0 ~ DQ7 tDS V IH - V IL - DQ8 ~ DQ15 tCRP tCSH tRSHtRCD tCAS tCRP tWCH tWP tDH DATA-IN tDS tDH DATA-IN

CMOS DRAMK4E661611D, K4E641611D tCRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tRP tRAL tRAD tASR tRAH tASC tCAH Don ′t care LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - tWCS V IH - V IL - DQ0 ~ DQ7 tDS V IH - V IL - DQ8 ~ DQ15 tCRP tCSH tRSHtRCD tCAS tWCH tWP tDH DATA-IN tCRP

CMOS DRAMK4E661611D, K4E641611D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don ′t care UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - tWCS V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tWCH tWP tDS tDH DATA-IN tCRP

CMOS DRAMK4E661611D, K4E641611D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCRP Don ′t care WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tCRPtRSHtRCD tCAS tCRP tRWL tWP tCWL tDH tDH DATA-IN COLUMN ADDRESS tOEHtOED tDS tDS DATA-IN tCSH tCAH

CMOS DRAMK4E661611D, K4E641611D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tRP tRAL tRAD tASR tRAH tASC tCAH Don ′t care LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - tRWL V IH - V IL - DQ0 ~ DQ7 tDS V IH - V IL - DQ8 ~ DQ15 tCRP tCSH tRSHtRCD tCAS tCRP tWP tCWL tDH DATA-IN tCRP tRPC tOEH tOED

CMOS DRAMK4E661611D, K4E641611D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don ′t care UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - V IH - V IL - V IH - V IL - tCRP tRWL tWP tCWL tDS tDH DATA-IN tOEH tOED DQ0 ~ DQ7 DQ8 ~ DQ15 tCRP

CMOS DRAMK4E661611D, K4E641611D tRWL RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR. tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP Don ′t care WORD READ - MODIFY - WRITE CYCLE Undefined LCAS V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 V I/OH - V I/OL - DQ8 ~ DQ15 tWP tCWL tDS tDH tRSHtRCD tCAS tCRP tAWD tCWD tOEA tRWD tOED tOEZtRAC tAA tOEZtRAC tAA tDS tOED tDH VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tCAC tCLZ tCAC tCLZ tOLZ tOLZ

CMOS DRAMK4E661611D, K4E641611D tRWL RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR. tRAS tRWC tRP tCSH tRAD tASR tRAH tASC tCAH tCRP Don ′t care LOWER-BYTE READ - MODIFY - WRITE CYCLE Undefined LCAS V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 tWP tCWL tDS tDH tRSHtRCD tCAS tCRP tAWD tCWD tOEA tRWD tOED tOEZtRAC tAA VALID DATA-OUT VALID DATA-IN tRPC tCAC tCLZ OPEN tOLZ

CMOS DRAMK4E661611D, K4E641611D tRWL RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP Don ′t care UPPER-BYTE READ - MODIFY - WRITE CYCLE Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V I/OH - V I/OL - DQ8 ~ DQ15 tWP tCWL tAWD tCWD tOEA tRWD tOEZtRAC tAA tDS tOED tDH VALID DATA-OUT VALID DATA-IN tCRP tRPC tCAC tCLZ OPEN tOLZ

CMOS DRAMK4E661611D, K4E641611D tASC tOLZ tCLZ tOLZ tCLZ RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tCRP Don ′t care HYPER PAGE MODE WORD READ CYCLE Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tCP tREZ tHPC tHPC tHPC tRHCPtCSH tRCD tCRP tCAS tCAS tCAS tCAS tCP tCP tCP tRAD tRCS tOEA tRCH tRRH COLUMN ADDRESS COLUMN ADDR tOEZ tOEP tCHO tAA tCPA tAA tCAC VALID DATA-OUT tOEP tOEZtRAC tCAC tDOH VALID DATA-OUT VALID DATA-OUT tOCH tCPA tAA tCAC tCAC tCPA tOEZ VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT tOEP tOEZtRAC tCAC VALID DATA-OUT VALID DATA-OUT tOEZ VALID DATA-OUT VALID DATA-OUT tDOH tOEA tASR tRAH tASC tCAH tASC tCAH tCAH tCAHtASC tRAL

CMOS DRAMK4E661611D, K4E641611D tOEA tOLZ tCLZ RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tCRP Don ′t care HYPER PAGE MODE LOWER BYTE READ CYCLE Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 COLUMN ADDRESS tREZ tRHCPtCSH tRCD tCAS tCAS tCAS tCAS tCP tCP tCP tRAD tRCS tRCH tRRH COLUMN ADDRESS COLUMN ADDR tOEZ tOEP tCHO tCPAtCAC VALID DATA-OUT tOEP tOEZtRAC tCAC tDOH VALID DATA-OUT VALID DATA-OUT tOCH tCPA tCAC tCAC tCPA tOEZ VALID DATA-OUT VALID DATA-OUT OPEN tRPC tASR tRAH tASC tCAH tASC tCAH tCAH tASC tCAHtASC tAA tHPC tHPC tHPC tAAtAA tAA tOEA tRAL

CMOS DRAMK4E661611D, K4E641611D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR. tRASP tRP tRCD tASR tCRP Don ′t care HYPER PAGE MODE UPPER BYTE READ CYCLE Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tCP tREZ tHPC tHPC tHPC tRHCPtCSH tCRP tRAH tASC tCAH tCAH tCAH tASC tCAH tRCS tOEA tRCH tRRH COLUMN ADDRESS COLUMN ADDR. tOEZ tOEP tCHO tCPAtCAC VALID DATA-OUT tOEP tOEZtRAC tCAC tOLZ tCLZ tDOH VALID DATA-OUT VALID DATA-OUT tOCH tCPA tCAC tCAC tCPA tOEZ VALID DATA-OUT VALID DATA-OUT OPEN tASC tRPC tRPC tRAD tASC tAAtAA tAA tOEA tRAL

CMOS DRAMK4E661611D, K4E641611D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tASR tCRP Don ′t care HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tCRP tHPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tCAS tCP tCAS tCP tCAS tRSH tRCD tCRP tHPC tHPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH VALID DATA-IN VALID DATA-IN VALID DATA-IN tDH tDH tDHtDStDStDS NOTE : D OUT = OPEN tHPC tRAL

CMOS DRAMK4E661611D, K4E641611D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tASR tCRP Don ′t care HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tRPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tRCD tCRP tHPC tHPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH NOTE : D OUT = OPEN tRAL

CMOS DRAMK4E661611D, K4E641611D tWCS RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tASR tCRP Don ′t care HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tRPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tRCD tCRP tHPC tHPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH NOTE : D OUT = OPEN tRAL

CMOS DRAMK4E661611D, K4E641611D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don ′t care HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE Undefined tRCD tCP tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAS tCAS tCRP tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tASC tCLZ tOEA tCAC tAA tDH tOED LCAS V IH - V IL - tRCD tCP tCAS tCAS tCRP tCRP tCRP V I/OH - V I/OL - DQ8 ~ DQ15 VALID DATA-OUT tDH tAA tRAC tCLZ tCAC VALID DATA-IN VALID DATA-OUT VALID DATA-IN tCLZ tCAC tAA tDH tOEZ tOED tDS tDS tDS tOED tOEZ tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tHPRWC tRSH tRWL tRCS tRAH

CMOS DRAMK4E661611D, K4E641611D tASC RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don ′t care HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE Undefined tRAD tCAH tWP tDH COL. ADDR COL. ADDR tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tCLZ tOEA tCAC tAA tDH tOED tRWL tRCD tCP tCAS tCAS tCRP tCRP tCRP V I/OH - V I/OL - DQ8 ~ DQ15 tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tRPC tRSH OPEN LCAS V IH - V IL - UCAS V IH - V IL - tHPRWC tRCS tOLZ tOLZ tRAH

CMOS DRAMK4E661611D, K4E641611D tASC tCRP RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don ′t care HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE Undefined tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tCLZ tOEA tCAC tAA tDH tOED tRWL tRCD tCP tCAS tCAS tCRP tCRP V I/OH - V I/OL - DQ8 ~ DQ15 tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tRPC tRSH OPEN LCAS V IH - V IL - UCAS V IH - V IL - tHPRWC tASC tRCS tRAH tOLZ tOLZ

CMOS DRAMK4E661611D, K4E641611D HYPER PAGE READ AND WRITE MIXED CYCLE RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP Don ′t care Undefined V I/OH - V I/OL - DQ0 ~ DQ7 tWEZ tCP tHPC tHPC tHPC tRCD tRAH tASC tCAH tCAH tCAH tASC tCAH tRCHtRCS tRCS tRCH tASC COLUMN ADDRESS COL. ADDR VALID DATA-OUT tREZtAA tWCS VALID DATA-OUT VALID DATA-OUT VALID DATA-IN tRAC COL. ADDR tCAS tASR tCAStCAS tCAS tASC tCP tRCH tWCH tWPE tCLZ tCPA tWED tAA tWEZ tDS tDH tCAC tOEA tCP tHPC tHPC tCAS tCAStCAS tCAS tCP V I/OH - V I/OL - DQ8 ~ DQ15 tWEZ VALID DATA-OUT tREZtAA VALID DATA-OUT VALID DATA-OUT VALID DATA-IN tRAC tAA tWEZ tDS tDH tCAC tOEA LCAS V IH - V IL - UCAS V IH - V IL - tCP tHPC tCP READ( t CAC ) READ( tCPA ) WRITE READ( tAA ) tRAD tRHCP tRAL

CMOS DRAMK4E661611D, K4E641611D tCRP OPEN RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - ROW ADDR tRC tRP tASR tCRP RAS - ONLY REFRESH CYCLE LCAS V IH - V IL - tRAS tRAH NOTE : W , OE , D IN = Don ′t care D OUT = OPEN tRPC CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - UCAS V IH - V IL - tRC tRP LCAS V IH - V IL - tRAS tRPC tCP tRPC tCSR tCHR tCP tCSR tCHR tCEZ OPEN V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 tWRP tWRH W V IH - V IL - Don ′t care tRP Undefined

CMOS DRAMK4E661611D, K4E641611D tOEZ DATA-IN DATA-OUT tRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don ′t care HIDDEN REFRESH CYCLE ( READ ) Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 tRSHtRCDtCRP tWRH COLUMN ADDRESS tOEA tRAS tRC tCHR tCAH tRCS tAA tRAC tCLZ tCAC DATA-OUT tCEZ OPEN OPEN tRP tREZ tWEZ tOLZ * In Hidden refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off. tRAL

CMOS DRAMK4E661611D, K4E641611D tWCS tRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don ′t care HIDDEN REFRESH CYCLE ( WRITE ) Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tRSHtRCD tCRP tWRH COLUMN ADDRESS tRAS tRC tCHR tCAH tWRP tDS NOTE : D OUT = OPEN tWP tWCH DATA-IN tDH tDS DATA-IN tDH tRP

CMOS DRAMK4E661611D, K4E641611D OPEN CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - UCAS V IH - V IL - tRPS LCAS V IH - V IL - tRASS tRPC tCP tRPC tCSR tCEZ OPEN V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 tWRP tWRH W V IH - V IL - tCHS tCP tCSR tCHS TEST MODE IN CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - UCAS V IH - V IL - tRP LCAS V IH - V IL - tRC tRPC tCP tRPC tCSR OPENV OH - V OL - DQ0 ~ DQ15 tCHR tCP tCSR tCHR tRP tRP Don ′t care Undefined tWTS tWTH W V IH - V IL - tCEZ tRAS

CMOS DRAMK4E661611D, K4E641611D

50 TSOP(II) 400mil Units : Inches (millimeters)

0.047 (1.20) MIN 0.002 (0.05) 0.018 (0.45) 0.010 (0.25) 0.821 (20.85) 0.829 (21.05) 0.841 (21.35) MAX 0.010 (0.25) 0.004 (0.10) 0 .4 0 0 ( 1 0 . 1 6 ) 0 .4 7 1 ( 1 1 . 9 6 ) 0 .4 5 5 ( 1 1 . 5 6 ) 0~8 0.030 (0.75) 0.018 (0.45) TYP 0.010 (0.25) O PACKAGE DIMENSION